International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
Designing and Characterization of koggestone, Sparse Kogge stone, Spanning tr...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
This paper presents a recursive designing approach for high energy efficient carry select adder (CSA). Nowadays, the portable equipment’s like mobile phones and laptops have higher demands in the market. So, the designers must focus greater attention while designing such devices. Which means that have the devices must have lesser power consumption, low cost and have a better performance. The customers mainly focus on the equipment’s which have lesser power consumption, low cost and better performance. As we all know that the adders are the basic building block of microprocessors. The performance of the adders greatly influences the performance of those processors. The carry select adder is most suitable among other adders which have fast addition operation at low cost. The carry select adder (CSA) consists of chain full adders (FAs) and multiplexers. Here a carry select adder is designed with four FAs and four multiplexers. The proposed structure is assessed by the power consumption of the carry select adder using a 32-nm static CMOS technology for a wide range of supply voltages. The simulation results are obtained using Tanner EDA which reveals that the carry select adder has low power consumption.
A Novel Distribution System Power Flow Algorithm using Forward Backward Matri...iosrjce
IOSR Journal of Electrical and Electronics Engineering(IOSR-JEEE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of electrical and electronics engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electrical and electronics engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
Designing and Characterization of koggestone, Sparse Kogge stone, Spanning tr...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
This paper presents a recursive designing approach for high energy efficient carry select adder (CSA). Nowadays, the portable equipment’s like mobile phones and laptops have higher demands in the market. So, the designers must focus greater attention while designing such devices. Which means that have the devices must have lesser power consumption, low cost and have a better performance. The customers mainly focus on the equipment’s which have lesser power consumption, low cost and better performance. As we all know that the adders are the basic building block of microprocessors. The performance of the adders greatly influences the performance of those processors. The carry select adder is most suitable among other adders which have fast addition operation at low cost. The carry select adder (CSA) consists of chain full adders (FAs) and multiplexers. Here a carry select adder is designed with four FAs and four multiplexers. The proposed structure is assessed by the power consumption of the carry select adder using a 32-nm static CMOS technology for a wide range of supply voltages. The simulation results are obtained using Tanner EDA which reveals that the carry select adder has low power consumption.
A Novel Distribution System Power Flow Algorithm using Forward Backward Matri...iosrjce
IOSR Journal of Electrical and Electronics Engineering(IOSR-JEEE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of electrical and electronics engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electrical and electronics engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
A comparative study of full adder using static cmos logic styleeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Highly -increasing requirement for mobile and several electronic devices want the use of VLSI circuits which are highly power efficient. The most primitive arithmetic operation in processors is addition and the adder is the most highly used arithmetic component of the processor. Carry Select Adder (CSA) is one of the fastest adders and the structure of the CSA shows that there is a possibility for increasing its efficiency by reducing the power dissipation and area in the CSA. This research paper presents power and delay analysis of various adders and proposed a 32-bit CSA that is implemented using variable size of the combination of adders, thus the proposed Carry select Adder (CSA) which has minimum Delay, and less power consumption hence improving the efficiency and speed of the Carry Select Adder.
Control of a Three-Phase Hybrid Converter for a PV Charging StationAsoka Technologies
Hybrid boost converter (HBC) has been proposed to replace a dc/dc boost converter and a dc/ac converter to reduce conversion stages and switching loss. In this paper, control of a three-phase HBC in a PV charging station is designed and tested. This HBC interfaces a PV system, a dc system with hybrid plugin electrical vehicles (HPEVs) and a three-phase ac grid. The control of the HBC is designed to realize maximum power point tracking (MPPT) for PV, dc bus voltage regulation, and ac voltage or reactive power regulation. A test bed with power electronics switching details is built in MATLAB/SimPowersystems for validation. Simulation results demonstrate the feasibility of the designed control architecture. Finally, lab experimental testing is conducted to demonstrate HBC’s control performance.
— Parallel Prefix adders have been one of the most
notable among several designs proposed in the past. The
advantage of utilizing the flexibility in implementing these
structures based upon through put requirements. Due to
continuing integrating intensity and the growing needs of
portable devices, low power and high performance designs are of
prime importance. The classical parallel prefix adder structures
presented in the literature over the years optimize for logic depth,
area, and fan-out and interconnect count of logic circuits. In this
proposed system, Kogge-Stone adder which is one of types of
parallel prefix adder is used. Kogge stone is the fastest adder
because of its minimum fan-out. When parallel prefix adder is
compared with classical adders it is advantageous in every aspect.
The study reveals that Parallel Prefix adder has the least power
delay product when compared with its peer existing adder
structures (Ripple carry adder, Carry save adders etc).
Simulation results are verified using Xilinx 10.1 and
MODELSIM 6.4a softwares.
Design Of 64-Bit Parallel Prefix VLSI Adder For High Speed Arithmetic CircuitsIJRES Journal
Parallel prefix adder is a kind of process for speeding up the addition of the system of writing and calculating with numbers which use only two digits. Parallel prefix adders are also known as carry-tree adders and they are known to have the best performance in VLSI designs. Due to constraints on logic blog configurations a routing overhead, this performance advantage does not translate directly into FPGA implementations. Identifying the absolutely accurate area-delay tradeoff curve of the parallel prefix is an interesting problem that has received more attention in research because parallel prefix adder on the other hand represents a type of general adder structure that displays publically in flexible area-time tradeoffs for the design of adder. Many different types of parallel prefix adders are made to increase for optimizing area, fan out, speed and performance. For high speed performance tree like structure is must which helps in greater way. There are many different method used for designing parallel prefix adder based on their speed, size and performance. For area optimization we use Brent-Kung method. If our main purpose is to get the least timing then we have to use Kogg-Stone adder method.
Implementation of Low Power and Area Efficient Carry Select Adderinventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Design and Verification of Area Efficient Carry Select Adderijsrd.com
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 16, 32 square - root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area.
Most importantly one can identify locations of inputs and outputs of the portions of a model and specify the operating conditions about which the model is linearized for further analysis. Other important feature of Simulink is a Linear-Quadratic-Gaussian LQG control technique which is used to design optimal dynamic regulators, Kalman estimators and filters.
A comparative study of full adder using static cmos logic styleeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Highly -increasing requirement for mobile and several electronic devices want the use of VLSI circuits which are highly power efficient. The most primitive arithmetic operation in processors is addition and the adder is the most highly used arithmetic component of the processor. Carry Select Adder (CSA) is one of the fastest adders and the structure of the CSA shows that there is a possibility for increasing its efficiency by reducing the power dissipation and area in the CSA. This research paper presents power and delay analysis of various adders and proposed a 32-bit CSA that is implemented using variable size of the combination of adders, thus the proposed Carry select Adder (CSA) which has minimum Delay, and less power consumption hence improving the efficiency and speed of the Carry Select Adder.
Control of a Three-Phase Hybrid Converter for a PV Charging StationAsoka Technologies
Hybrid boost converter (HBC) has been proposed to replace a dc/dc boost converter and a dc/ac converter to reduce conversion stages and switching loss. In this paper, control of a three-phase HBC in a PV charging station is designed and tested. This HBC interfaces a PV system, a dc system with hybrid plugin electrical vehicles (HPEVs) and a three-phase ac grid. The control of the HBC is designed to realize maximum power point tracking (MPPT) for PV, dc bus voltage regulation, and ac voltage or reactive power regulation. A test bed with power electronics switching details is built in MATLAB/SimPowersystems for validation. Simulation results demonstrate the feasibility of the designed control architecture. Finally, lab experimental testing is conducted to demonstrate HBC’s control performance.
— Parallel Prefix adders have been one of the most
notable among several designs proposed in the past. The
advantage of utilizing the flexibility in implementing these
structures based upon through put requirements. Due to
continuing integrating intensity and the growing needs of
portable devices, low power and high performance designs are of
prime importance. The classical parallel prefix adder structures
presented in the literature over the years optimize for logic depth,
area, and fan-out and interconnect count of logic circuits. In this
proposed system, Kogge-Stone adder which is one of types of
parallel prefix adder is used. Kogge stone is the fastest adder
because of its minimum fan-out. When parallel prefix adder is
compared with classical adders it is advantageous in every aspect.
The study reveals that Parallel Prefix adder has the least power
delay product when compared with its peer existing adder
structures (Ripple carry adder, Carry save adders etc).
Simulation results are verified using Xilinx 10.1 and
MODELSIM 6.4a softwares.
Design Of 64-Bit Parallel Prefix VLSI Adder For High Speed Arithmetic CircuitsIJRES Journal
Parallel prefix adder is a kind of process for speeding up the addition of the system of writing and calculating with numbers which use only two digits. Parallel prefix adders are also known as carry-tree adders and they are known to have the best performance in VLSI designs. Due to constraints on logic blog configurations a routing overhead, this performance advantage does not translate directly into FPGA implementations. Identifying the absolutely accurate area-delay tradeoff curve of the parallel prefix is an interesting problem that has received more attention in research because parallel prefix adder on the other hand represents a type of general adder structure that displays publically in flexible area-time tradeoffs for the design of adder. Many different types of parallel prefix adders are made to increase for optimizing area, fan out, speed and performance. For high speed performance tree like structure is must which helps in greater way. There are many different method used for designing parallel prefix adder based on their speed, size and performance. For area optimization we use Brent-Kung method. If our main purpose is to get the least timing then we have to use Kogg-Stone adder method.
Implementation of Low Power and Area Efficient Carry Select Adderinventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Design and Verification of Area Efficient Carry Select Adderijsrd.com
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 16, 32 square - root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area.
Most importantly one can identify locations of inputs and outputs of the portions of a model and specify the operating conditions about which the model is linearized for further analysis. Other important feature of Simulink is a Linear-Quadratic-Gaussian LQG control technique which is used to design optimal dynamic regulators, Kalman estimators and filters.
ELECTRIC AND SOLAR VEHICLE-DESIGN AND DEVELOPMENT.pptxsrinivasarao8004
By this training I have learnt So much about Electric Vehicles, advantages, disadvantages, and its Components. Also, I have learnt more about MATLAB, like how to design battery circuit, how to give required amount of current to the battery circuit and how to Identify the resultant Voltage etc. Modeling and simulation of electric vehicle’s battery is done on MATLAB/Simulink. Designed a battery circuit with 9 batteries with a voltage of 3.7V each and we have noticed that state of charge is decreases with respective to the Time. This model can be used to estimate how long the battery can be used in electric vehicles. From the plot of State of Charge is observed that after the vehicle has started running, after some time the graph has decreased in terms of charge stored in the battery. Further from the engine speed and Motor Speed, shows smooth functioning of vehicle without any distortions. This means the graph of SOC with respective to the time shown above decreases with increase in acceleration of the vehicle. Here the current is constant throughout the process because of we have connected the circuit in series, so the voltage and SOC decrease with increase in acceleration of Vehicle.
[9_CV] FCS-Model Predictive Control of Induction Motors feed by MultilLevel C...Nam Thanh
Ha Thanh Vo, Nam Thanh Hoang, Phuong Hoang Vu, Minh Trong Tran, Dich Quang Nguyen, “FCS-Model Predictive Control of Induction Motors feed by MultilLevel Casaded H-Bridge Inverter”, RCEEE-2018.
This paper propose a new approach to determine a linear mathematical model of a PV moduel based on an accurate nonlinear model . In this study, electrical parameters at only one operating condition are calculated based on an accurate model. Then, first-order Taylor series approximations apply on the nonlinear model to estimate the proposed model at any operating conditionts. The proposed method determines the number of iteration times. This decreases calculation time and the speed of numerical convergence will be increased. And, it is observed that owing to this method, the system converged and the problem of failing to solve the system because of inappropriate initial values is eliminated. The proposed model is requested in order to allow photovoltaic plants simulations using low-cost computer platforms. The effectiveness of the proposed model is demonstrated for different temperature and irradiance values through conducting a comparison between result of the proposed model and experimental results obtained from the module data-sheet information.
This project is proposed to integrate the Fuel cell emulator with a boost converter and load the DC motor
and the performance analysis is done. Fuel cell as a renewable energy source is considered to be one of the most
promising sources of electrical power. The characteristics of fuel cell is such that the DC power extracted from it is
at low voltage level, this project proposes a prototype of a new power electronics based fuel cell emulator. After
proposing a fuel cell emulator, it is integrated with a boost converter and DC motor is loaded. After the successful
working of the boost converter, it can be directly connected with the actual Fuel Cell Systems (FCS) to satisfy the
DC motor load which is integrated with fuel cell emulator and boost converter.
This project proposes to estimate SOC of the LIB from a reduced-order electrochemical model (ROEM) using an Extended Kalman Filter (EKF). To reduce the model complexity, the solid phase equations will be reconstructed by combining the Pade approximation and quadratic polynomial method. Volume averaging technique will be used for electrolyte physics simplification. Then an EKF will be used to estimate the SOC of the battery.
A NEW APPROACH TO DTC METHOD FOR BLDC MOTOR ADJUSTABLE SPEED DRIVEScscpconf
This paper proposes a new approach to direct torque control (DTC) method for brushless direct current (BLDC) motor drives. In conventional DTC method, two main reference parameters are used as: flux and torque. In this paper, the new approach has been proposed to improve the BLDC motor dynamic performance. A main difference from the conventional method of it was that only one reference parameter (speed) was used to control the BLDC motor and the second control parameter (flux) was obtained from speed error through the proposed control algorithm. Thus, the DTC performance has been especially improved on systems which need variable speed and torque during operation, like electric vehicles. The dynamic models of the BLDC and the DTC method have been created on Matlab/Simulink. The proposed method has been confirmed and verified by the dynamic simulations on different working conditions.
A Novel Multi Port Dc/Dc Converter Topology Using Zero Voltage Switching For...IJMER
This paper proposes a novel dc/dc converter topology that interfaces the non-conventional
energy sources. It consists of four power ports: two sources (namely solar and wind), one bidirectional
storage port, and one isolated load port. The proposed four-port dc/dc converter is derived by simply
adding two switches and two diodes to the traditional half-bridge topology. Zero-voltage switching is
realized for all four main switches. This paper proposes a new four-port-integrated dc/dc topology, which
is suitable for various renewable energy harvesting applications. An application interfacing hybrid
photovoltaic (PV) and wind sources, one bidirectional battery port, and an isolated output port is given as
a design example. It can achieve maximum power-point tracking (MPPT) for both PV and wind power
simultaneously or individually, while maintaining a regulated output voltage.
Mathematical Modelling of Semiconductor Devices and Circuits: A Review
Sanjay Kumar Roy, Manwinder Singh, Kamal Kumar Sharma
and Brahmadeo Prasad Singh
A new bidirectional multilevel inverter topology with a high number of voltage levels with a very reduced number of power components is proposed in this paper. Only TEN power switches and four asymmetric DC voltage sources are used to generate 25 voltage levels in this new topology. The proposed multilevel converter is more suitable for e-mobility and photovoltaic applications where the overall energy source can be composed of a few units/associations of several basic source modules. Several benefits are provided by this new topology: Highly sinusoidal current and voltage waveforms, low Total Harmonic Distortion, very low switching losses, and minimum cost and size of the device. For optimum control of this 25-level voltage inverter, a special Modified Hybrid Modulation technique is performed. The proposed 25-level inverter is compared to various topologies published recently in terms of cost, the number of active power switches, clamped diodes, flying capacitors, DC floating capacitors, and the number of DC voltage sources. This comparison clearly shows that the proposed topology is cost-effective, compact, and very efficient. The effectiveness and the good performance of the proposed multilevel power converter (with and without PWM control) are verified and checked by computational simulations.
Modeling and test validation of a 15 kV - 24 MVA superconducting fault curren...Franco Moriconi
High-power short-circuit test results and numerical simulations of a 15kV–24MVA distribution-class High Temperature Superconductor (HTS) Fault Current Limiters (FCL) are presented and compared in this paper. The FCL design was based on the nonlinear inductance model here described, and the device was tested at 13.1kV line-to-line voltage for prospective fault currents up to 23kArms, prior to its installation in the electric grid. Comparison between numerical simulations and fault test measurements show good agreement. Some simulations and field testing results are depicted. The FCL was energized in the Southern California Edison grid on March 9, 2009.
Neuro-symbolic is not enough, we need neuro-*semantic*Frank van Harmelen
Neuro-symbolic (NeSy) AI is on the rise. However, simply machine learning on just any symbolic structure is not sufficient to really harvest the gains of NeSy. These will only be gained when the symbolic structures have an actual semantics. I give an operational definition of semantics as “predictable inference”.
All of this illustrated with link prediction over knowledge graphs, but the argument is general.
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
Securing your Kubernetes cluster_ a step-by-step guide to success !KatiaHIMEUR1
Today, after several years of existence, an extremely active community and an ultra-dynamic ecosystem, Kubernetes has established itself as the de facto standard in container orchestration. Thanks to a wide range of managed services, it has never been so easy to set up a ready-to-use Kubernetes cluster.
However, this ease of use means that the subject of security in Kubernetes is often left for later, or even neglected. This exposes companies to significant risks.
In this talk, I'll show you step-by-step how to secure your Kubernetes cluster for greater peace of mind and reliability.
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
Builder.ai Founder Sachin Dev Duggal's Strategic Approach to Create an Innova...Ramesh Iyer
In today's fast-changing business world, Companies that adapt and embrace new ideas often need help to keep up with the competition. However, fostering a culture of innovation takes much work. It takes vision, leadership and willingness to take risks in the right proportion. Sachin Dev Duggal, co-founder of Builder.ai, has perfected the art of this balance, creating a company culture where creativity and growth are nurtured at each stage.
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf91mobiles
91mobiles recently conducted a Smart TV Buyer Insights Survey in which we asked over 3,000 respondents about the TV they own, aspects they look at on a new TV, and their TV buying preferences.
Key Trends Shaping the Future of Infrastructure.pdfCheryl Hung
Keynote at DIGIT West Expo, Glasgow on 29 May 2024.
Cheryl Hung, ochery.com
Sr Director, Infrastructure Ecosystem, Arm.
The key trends across hardware, cloud and open-source; exploring how these areas are likely to mature and develop over the short and long-term, and then considering how organisations can position themselves to adapt and thrive.
Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
This presentation was delivered at K8SUG Singapore. See https://feryn.eu/presentations/accelerate-your-kubernetes-clusters-with-varnish-caching-k8sug-singapore-28-2024 for more details.
Slack (or Teams) Automation for Bonterra Impact Management (fka Social Soluti...Jeffrey Haguewood
Sidekick Solutions uses Bonterra Impact Management (fka Social Solutions Apricot) and automation solutions to integrate data for business workflows.
We believe integration and automation are essential to user experience and the promise of efficient work through technology. Automation is the critical ingredient to realizing that full vision. We develop integration products and services for Bonterra Case Management software to support the deployment of automations for a variety of use cases.
This video focuses on the notifications, alerts, and approval requests using Slack for Bonterra Impact Management. The solutions covered in this webinar can also be deployed for Microsoft Teams.
Interested in deploying notification automations for Bonterra Impact Management? Contact us at sales@sidekicksolutionsllc.com to discuss next steps.
Mission to Decommission: Importance of Decommissioning Products to Increase E...
Mems paper
1. A Single-Platform Simulation and Design Technique for
CMOS-MEMS Based on a Circuit Simulator with Hardware
Description Language
BITS Pilani
Hyderabad Campus
Mayank Garg
2013H140040H
ME Embedded System
2. Motivation
MEMS and CMOS technology has transformed the world
in last 3 decades.
Most Of the MEMS today fabricated in the same way as
the silicon integrated system.
Silicon in good for Both MEMS and CMOS.
It is motivated us to integrate both the technology.
Use of MEMS as important components and subsystems
in RF circuits has led a new dimensions in CMOS-MEMS
integration.
A number of CMOS-MEMS devices have been fabricated
and delivered.
Challenge in this is, CAD tool for co-design with MEMS
and CMOS integrated system need to be developed.
3. *
Design Flow
Flowchart based on circuit simulator
Electrostatic parallel-plate actuator.
Sub-Circuits for simulator
Verilog-A expressions
Result analysis
Comparison
Simulation and experiment result
Conclusion
10. MODULE I: Sub-circuit model for the parallel-plate electrostatic
actuator, and it has been designed to calculate the electrostatic force F1
as electrical current output as a function of drive voltage(s).
Module II: For the viscoelastic suspension to calculate the restoring force
F2 as current output.
Module III: which has been inserted between the viscoelastic suspension
and the electrostatic actuator, is the EOM cosolver to calculate the
velocity and the displacement x as a function of the electrostatic and
restoring forces.
Module IV: the mechanical anchor
Those sub-circuit symbols I–IV have been designed to visually represent
the elements.
11. Verilog-A expressions: We are using Verilog-A, which is an
HDL that can handle various mathematical
operations, including derivation and integration as well
as logical expressions such as an if–then–else clause. It
also has versatility of defining the input and output ports
in either the electrical current and voltage modes.
Verilog-A description can be placed in a more
straightforward manner by using mathematical
expressions
13. Block1: defines the initial conditions
for the displacement
Block 2:the acceleration a is
calculated from the net electrostatic
attractive force and the restoring
force, divided by the lumped mass m.
Block 3: where a logical flag vi0integ
is set to be one when the
displacement x1 comes into contact
with the mechanical stoppers at limit
or limit on the positive and negative
directions, respectively. When vi0integ
is fulfilled to be one, the velocity is
forced to be null by the conditional
description in the idt function, and
accordingly, displacement x1 remains
at the stopper position.
In a similar manner, the displacement
is obtained by integrating the velocity;
the value of v1 is read as voltage, as
described in block.
14. Block 4: To avoid accumulative error in calculating the displacement
Block 5: Finally, in block
Block 6: the resultant displacement x1 is exported to the output ports
HDL equivalent circuit description for viscoelastic
suspension
15. Transient analysis result of
electrostatic parallel-plate actuator;
dis- placement as a function of
applied voltage.
Dashed Line: Triangular drive Voltage
Solid line: displacement of movable
plate
AC harmonic analysis result of
electrostatic parallel-plate
actuator; input reactance spectrum
16. Automatically synthesized mask layout for the electrostatic
silicon resonator. Dimensional parameters are used in the
corresponding PCell script code.
Part of PCell script codes to automatically
generate layout patterns for the viscoelastic
suspension module
COMSOL simulation results of modal analysis
18. Simulation and experimental results
of the actual electrostatic parallelplate actuator.
(a) Capacitance-versus-drive-voltage
curve.
(b) Capacitance-versus-frequency
characteristics
19. Conclusion
We have studied a
novel multiphysics simulation and design
technique for CMOS-MEMS based on an electrical circuit simulator
with a Verilog-A-compatible HDL in the Cadence Virtuoso
environment.
The EOM for mechanical behavior can be implemented as an
equivalent circuit in an analog-computation style such that
electromechanical motion can be cosolved with electrical circuitry
on a single platform without transferring FEM-generated data set
between different simulation tools.
An electrostatic MEMS resonator can be modeled within the
developed simulation platform to show the multiphysics handling
capability for the microelectromechanical behavior and the
electrical transistor circuit.