This paper presents the design of high-speed full adder circuits using a new CMOS mixed mode logic family. The objective of this work is to present a new full adder design circuits combined with current mode circuit in one unit to implement a full adder cell. This paper also discusses a high- speed hybrid majority function based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure with conventional static and dynamic CMOS logic circuit. The static Majority function (bridge) design style enjoys a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as lower power consumption by using bridge transistors. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of mixedmode logic designs. Dynamic CMOS circuits enjoy area, delay and testability advantages over static CMOS circuits. Simulation results illustrate the superiority of the new designed adder circuits against the reported conventional CMOS, dynamic and majority function adder circuits, in terms of power, delay, power delay product (PDP) and energy delay product (EDP). The design is implemented on UMC 0.18µm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.
Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Fu...VLSICS Design
This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).
Evaluation of Energy Consumption of Reactive and Proactive Routing Protocols ...IJCNCJournal
Mobile Ad hoc Network (MANET) is a distributed, infrastructure-less and decentralized network. A routing
protocol in MANET is used to find routes between mobile nodes to facilitate communication within the
network. Numerous routing protocols have been proposed for MANET. Those routing protocols are
designed to adaptively accommodate for dynamic unpredictable changes in network's topology. The mobile
nodes in MANET are often powered by limited batteries and network lifetime relies heavily on the energy
consumption of nodes. In consequence, the lack of a mobile node can lead to network partitioning. In this
paper we analyse, evaluate and measure the energy efficiency of three prominent MANET routing protocols
namely DSR, AODV and OLSR in addition to modified protocols. These routing protocols follow the
reactive and the proactive routing schemes. A discussion and comparison highlighting their particular
merits and drawbacks are also presented. Evaluation study and simulations are performed using NS-2 and
its accompanying tools for analysis and investigation of results.
A RELIABLE AND ENERGY EFFICIENCT ROUTING PROTOCOL FOR MANETs cscpconf
A mobile ad-hoc network (MANETs) is an infrastructure less network in which the mobile nodes
communicate with each other. Due to its various characteristics like highly dynamic topology
and limited battery power of the nodes, routing is one of the key issue. Also, it is not possible to
give a significant amount of power to the mobile nodes of ad-hoc networks. Because of all this
the energy consumption is also an important issue. Due to limited battery power, some other
issues like if some node gets fail, which results in loss of data packets and no reliable data
transfer has been raised. In this paper, an algorithm is proposed for data transmission which
detects the node failure (due to energy) before it actually happens. Because of this network
lifetime gets improved. The proposed routing algorithm is energy efficient as compared to
AODV routing algorithm. The performance is analyzed on the basis of various performance
metrics like Energy Consumption, Packet Delivery Ratio, Network Life Time, Network Routing
Overhead and number of Exhausted nodes in the network by using the NS2 Simulator.
AREA-EFFICIENT DESIGN OF SCHEDULER FOR ROUTING NODE OF NETWORK-ON-CHIPVLSICS Design
Traditional System-on-Chip (SoC) design employed shared buses for data transfer among various subsystems. As SoCs become more complex involving a larger number of subsystems, traditional busbased architecture is giving way to a new paradigm for on-chip communication. This paradigm is called Network-on-Chip (NoC). A communication network of point-to-point links and routing switches is used to facilitate communication between subsystems. The routing switch proposed in this paper consists of four components, namely the input ports, output ports, switching fabric, and scheduler. The scheduler design is described in this paper. The function of the scheduler is to arbitrate between requests by data packets for use of the switching fabric. The scheduler uses an improved round robin based arbitration algorithm. Due to the symmetric structure of the scheduler, an area-efficient design is proposed by folding the scheduler onto itself, thereby reducing its area roughly by 50%.
Energy Consumption Analysis of Ad hoc Routing Protocols for Different Energy ...IOSR Journals
Abstract : In Mobile Ad hoc Networks (MANETs), energy conservation is a critical issue as the nodes are powered by the batteries which have limited energy reservoir. Hence the power level of the nodes is a problematical factor that extensively affects the performance and efficiency of ad hoc routing protocols. The rapidly changing traffic pattern the mobility of the nodes and the lack of fixed infrastructure makes routing in a MANET a challenging issue. So one of the main issues in MANET routing protocols is the development of energy efficient and QoS aware routing protocols which requires the energy analysis of routing protocols so that some modifications can be suggested. This paper presents performance comparison of three categories of mobile ad hoc routing protocols i.e. proactive, reactive and hybrid. The performance analysis is based on different metrics of Physical Layer such as Power Consumed in Transmit Mode, Power Consumed in Receive and Idle Modes, and metrics of application layer like Average End to End Delay, Average Jitter, Throughput and Packet Delivery Ratio based on the simulation analysis. Simulation analysis is performed over well known network simulator QualNet 6.1. Keywords - MANET, AODV, DYMO, OLSR, PDR
Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Fu...VLSICS Design
This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).
Evaluation of Energy Consumption of Reactive and Proactive Routing Protocols ...IJCNCJournal
Mobile Ad hoc Network (MANET) is a distributed, infrastructure-less and decentralized network. A routing
protocol in MANET is used to find routes between mobile nodes to facilitate communication within the
network. Numerous routing protocols have been proposed for MANET. Those routing protocols are
designed to adaptively accommodate for dynamic unpredictable changes in network's topology. The mobile
nodes in MANET are often powered by limited batteries and network lifetime relies heavily on the energy
consumption of nodes. In consequence, the lack of a mobile node can lead to network partitioning. In this
paper we analyse, evaluate and measure the energy efficiency of three prominent MANET routing protocols
namely DSR, AODV and OLSR in addition to modified protocols. These routing protocols follow the
reactive and the proactive routing schemes. A discussion and comparison highlighting their particular
merits and drawbacks are also presented. Evaluation study and simulations are performed using NS-2 and
its accompanying tools for analysis and investigation of results.
A RELIABLE AND ENERGY EFFICIENCT ROUTING PROTOCOL FOR MANETs cscpconf
A mobile ad-hoc network (MANETs) is an infrastructure less network in which the mobile nodes
communicate with each other. Due to its various characteristics like highly dynamic topology
and limited battery power of the nodes, routing is one of the key issue. Also, it is not possible to
give a significant amount of power to the mobile nodes of ad-hoc networks. Because of all this
the energy consumption is also an important issue. Due to limited battery power, some other
issues like if some node gets fail, which results in loss of data packets and no reliable data
transfer has been raised. In this paper, an algorithm is proposed for data transmission which
detects the node failure (due to energy) before it actually happens. Because of this network
lifetime gets improved. The proposed routing algorithm is energy efficient as compared to
AODV routing algorithm. The performance is analyzed on the basis of various performance
metrics like Energy Consumption, Packet Delivery Ratio, Network Life Time, Network Routing
Overhead and number of Exhausted nodes in the network by using the NS2 Simulator.
AREA-EFFICIENT DESIGN OF SCHEDULER FOR ROUTING NODE OF NETWORK-ON-CHIPVLSICS Design
Traditional System-on-Chip (SoC) design employed shared buses for data transfer among various subsystems. As SoCs become more complex involving a larger number of subsystems, traditional busbased architecture is giving way to a new paradigm for on-chip communication. This paradigm is called Network-on-Chip (NoC). A communication network of point-to-point links and routing switches is used to facilitate communication between subsystems. The routing switch proposed in this paper consists of four components, namely the input ports, output ports, switching fabric, and scheduler. The scheduler design is described in this paper. The function of the scheduler is to arbitrate between requests by data packets for use of the switching fabric. The scheduler uses an improved round robin based arbitration algorithm. Due to the symmetric structure of the scheduler, an area-efficient design is proposed by folding the scheduler onto itself, thereby reducing its area roughly by 50%.
Energy Consumption Analysis of Ad hoc Routing Protocols for Different Energy ...IOSR Journals
Abstract : In Mobile Ad hoc Networks (MANETs), energy conservation is a critical issue as the nodes are powered by the batteries which have limited energy reservoir. Hence the power level of the nodes is a problematical factor that extensively affects the performance and efficiency of ad hoc routing protocols. The rapidly changing traffic pattern the mobility of the nodes and the lack of fixed infrastructure makes routing in a MANET a challenging issue. So one of the main issues in MANET routing protocols is the development of energy efficient and QoS aware routing protocols which requires the energy analysis of routing protocols so that some modifications can be suggested. This paper presents performance comparison of three categories of mobile ad hoc routing protocols i.e. proactive, reactive and hybrid. The performance analysis is based on different metrics of Physical Layer such as Power Consumed in Transmit Mode, Power Consumed in Receive and Idle Modes, and metrics of application layer like Average End to End Delay, Average Jitter, Throughput and Packet Delivery Ratio based on the simulation analysis. Simulation analysis is performed over well known network simulator QualNet 6.1. Keywords - MANET, AODV, DYMO, OLSR, PDR
Link Stability and Energy Aware routing Protocol for Mobile Adhoc NetworkIOSR Journals
Abstract: MOBILE ad hoc networks (MANETs) have more popularity among mobile network devices and
wireless communication technologies. A MANET is multihop mobile wireless network that have neither a fixed
infrastructure nor a central server. Every node in a MANET will act as a router, and also communicates with
each other. The mobility constraints in mobile nodes will lead to problems in link stability. Energy saving, path
duration and stability will be two major efforts and to satisfy them can be difficult task. A self node which is
present in the network may also consume little energy during the transmission. This proposed approach tries to
account for link stability and for minimum drain rate energy consumption. In order to verify the correctness of
the proposed solution a objective optimization formulation has been designed and a novel routing protocol
called Link-Stability and Energy aware Routing protocols is proposed. This novel routing scheme has been
compared with other two protocols: PERRA and GPSR. The protocol performance has been evaluated in terms
of Data Packet Delivery Ratio, Normalized Control Overhead, Link duration, Nodes lifetime, and Average
energy consumption.
Keywords-component; Energy Consumption, Link Stability, Routing, Self node
Performance evaluation of MANET routing protocols based on QoS and energy p...IJECEIAES
Routing selection and supporting Quality of Service (QoS) are fundamental problems in Mobile Ad Hoc Network (MANET). Many different protocols have been proposed in the literature and some performance simulations are made to address this challenging task. This paper discusses the performance evaluation and comparison of two typical routing protocols; Ad Hoc On-Demand Distance Vector (AODV) and Destination-Sequenced DistanceVector (DSDV) based on measuring the power consumption in network with varing of the QoS parameters. In this paper, we have studied and analyzed the impact of variations in QoS parameter combined with the choice of routing protocol, on network performance. The network performance is measured in terms of average throughput, packet delivery ratio (PDR), average jitter and energy consumption. The simulations are carried out in NS-3. The simulation results show that DSDV and AODV routing protocols are less energy efficient. The main aim of this paper is to highlight the directions for the future design of routing protocol which would be better than the existing ones in terms of energy utilization and delivery ratio.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Ijeee 24-27-energy efficient communication for adhoc networksKumar Goud
Energy Efficient Communication for Adhoc Networks
1SK.Nagula Meera 2Dr. D.Srinivasa Kumar 3Dr. D.Srinivasa Rao
Research Scholar Professor & Principal Professor, ECE department
ECE department, JNTU Hyderabad Hosur Institute of Technology and Science
Errandapalli Village, Beerpalli PO JNTU College of Engineering Hyderabad(Autonomous)
Ramapuram (via), Krishnagri Dt., Tamilnadu
Abstract: A mobile accidental network (MANET) may be an assortment of nodes equipped with wireless communications and a networking capability while not central network management. The method of wireless networks within the applications like transferring video files is subjected to twin constraints. Each step-down of power and different QOS needs like delay, throughputs square measure need to be bewaring properly. Mobile accidental Networks square measure a lot of perceptive to those problems wherever every mobile device is active sort of a router and consequently, routing delay adds significantly to overall end-to-end delay. This paper presents a survey on power economical routing protocols for Mobile Ad-Hoc Networks. This survey focused on recent progress on power saving algorithms. Additionally we recommend one power aware technique which can cut back power consumption yet as increase the lifespan of node and network.
Keywords: Mobile, Ad-Hoc networks, QOS, MANET, IBSS, ATIM, DPSM.
ENERGY EFFICIENT NODE RANK-BASED ROUTING ALGORITHM IN MOBILE AD-HOC NETWORKSIJCNCJournal
Mobile Ad-hoc Network (MANET) is an emerging technology, infrastructure less with self-organizing, selfhealing, multi-hop wireless routing networks in real time. In such networks, many routing problems arise due to complexity in the network mobility which results from difficulty in achieving energy efficient routing
in the field of MANET. Due to the dynamic nature and the limited battery energy of the mobile nodes, the communication links between intermediate relay nodes may fail frequently, thus affecting the routing performance of the network and also the availability of the nodes. Though existing protocols are not
concentrating about communication links and battery energy, node links are very important factor for improving quality of routing protocols because Node Rank helps us to determine whether the node is within transmission range or out of transmission range through considering residual energy of the node during the routing process. This paper proposes a novel Energy Efficient Node Rank-based Routing (EENRR)
algorithm which includes certain performance metrics such as control overhead and residual energy in order to improve the Packet Delivery Ratio (PDR), and Network Life Time (NLT) from its originally observed routing performance obtained through other existing protocols. Simulation results show that, when the number of nodes increases from 10 to 100 nodes, EENRR algorithm increases the average residual energy by 31.08% and 21.26% over the existing Dynamic Source Routing (DSR) and Energy Efficient Delay Time Routing (EEDTR) protocols, respectively. Similarly it increases the PDR by 45.38% and 28.3% over the existing DSR and EEDTR protocols respectively.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
WISHBONE BUS ARCHITECTURE – A SURVEY AND COMPARISONVLSICS Design
The performance of an on-chip interconnection architecture used for communication between IP cores depends on the efficiency of its bus architecture. Any bus architecture having advantages of faster bus clock speed, extra data transfer cycle, improved bus width and throughput is highly desirable for a low cost, reduced time-to-market and efficient System-on-Chip (SoC). This paper presents a survey of WISHBONE bus architecture and its comparison with three other on-chip bus architectures viz. Advanced Microcontroller Bus Architecture (AMBA) by ARM, CoreConnect by IBM and Avalon by Altera. The WISHBONE Bus Architecture by Silicore Corporation appears to be gaining an upper edge over the other three bus architecture types because of its special performance parameters like the use of flexible
arbitration scheme and additional data transfer cycle (Read-Modify-Write cycle). Moreover, its IP Cores are available free for use requiring neither any registration nor any agreement or license.
Energy Aware Routing Protocol for Energy Constrained Mobile Ad-hoc Networks IJECEIAES
Dynamic topology change and decentralized makes routing a challenging task in mobile ad hoc network. Energy efficient routing is the most challenging task in MANET due to limited energy of mobile nodes. Limited power of batteries typically use in MANET, and this is not easy to change or replace while running communication. Network disorder can occur for many factors but in middle of these factors deficiency of energy is the most significant one for causing broken links and early partition of the network. Evenly distribution of power between nodes could enhance the lifetime of the network, which leads to improving overall network transmission and minimizes the connection request. To discourse this issue, we propose an Energy Aware Routing Protocol (EARP) which considers node energy in route searching process and chooses nodes with higher energy levels. The EARP aim is to establish t he shortest route from source to destination that contains energy efficient nodes. The performance of EARP is evaluated in terms of packet delivery ratio, network lifetime, end-to-end delay and throughput. Results of simulation done by using NS2 network simulator shows that EARP can achieve both high throughput and delivery ratio, whereas increase network lifetime and decreases end-to-end delay.
SECTOR TREE-BASED CLUSTERING FOR ENERGY EFFICIENT ROUTING PROTOCOL IN HETEROG...IJCNCJournal
One of the main challenges for researchers to build routing protocols is how to use energy efficiently to extend the lifespan of the whole wireless sensor networks (WSN) because sensor nodes have limited battery power resources. In this work, we propose a Sector Tree-Based clustering routing protocol (STB-EE) for Energy Efficiency to cope with this problem, where the entire network area is partitioned into dynamic sectors (clusters), which balance the number of alive nodes. The nodes in each sector only communicate with their nearest neighbour by constructing a minimum tree based on the Kruskal algorithm and using mixed distance from candidate node to base station (BS) and remaining energy of candidate nodes to determine which node will become the cluster head (CH) in each cluster? By calculating the duration of time in each round for suitability, STB-EE increases the number of data packets sent to the BS. Our simulation results show that the network lifespan using STB-EE can be improved by about 16% and 10% in comparison to power-efficient gathering in sensor information system (PEGASIS) and energy-efficient PEGASIS-based protocol (IEEPB), respectively.
Energy efficient load balanced routing protocol for wireless sensor networkscsandit
Telecommunications is increasingly vital to the society at large, and has become essential to
business, academic, as well as social activities. Due to the necessity to have access to
telecommunications, the deployment requires regulations and policy. Otherwise, the deployment
of the infrastructures would contribute to environment, and human complexities rather than
ease of use.
However, the formulation of telecommunication infrastructure deployment regulation and
policy involve agents such as people and processes. The roles of the agents are critical, and are
not as easy as it meant to belief. This could be attributed to different factors, as they produce
and reproduce themselves overtime.
This paper presents the result of a study which focused on the roles of agents in the formulation
of telecommunication infrastructures deployment regulation and policy. In the study, the
interactions that take place amongst human and non-human agents were investigated. The study
employed the duality of structure, of Structuration theory as lens to understand the effectiveness
of interactions in the formulation of regulations, and how policy is used to facilitate the
deployment of telecommunications infrastructure in the South African environment.
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Addition is a fundamental arithmetic operation that is broadly used in many VLSI systems, such as application-specific digital signal processing (DSP) architectures and microprocessors. This addition module is also the core of other arithmetic operations such as subtraction, multiplication, division and address generation. The prime objective of this project is to design a full-adder having low-power consumption and low propagation delay which may result in the efficient implementation of modern digital systems. This model is referred as “hybrid” because of the combination of two different design logic styles namely CMOS logic and pass transistor logic. Performance parameters such as power, delay and hence energy were compared with the existing designs such as complementary CMOS logic full adder. In the existing hybrid systems, over 28 transistors were used. While the optimized hybrid full adder circuit reduces this count to 8 transistors, it still obtains better energy efficiency. Further the proper working of proposed full adder is verified by applying it in a Ripple carry Adder circuit.
Low Power-Area Design of Full Adder Using Self Resetting Logic with GDI Techn...VLSICS Design
Various electronic devices such as mobile phones, DSPs,ALU etc., are designed by using VLSI (Very
Large Scale Integration) technology. In VLSI dynamic CMOS logic circuits are concentrating on the Area
,reducing the power consumption and increasing the Speed by reducing the delay. ALU (Arithmetic Logic
Circuits) are designed by using adder, subtractors, multiplier, divider, etc.Various adder circuits designs
have been proposed over last few years with different logic styles. To reduce the power consumption
several parameters are to be taken into account, such as feedthrough, leakage power single-event upsets,
charge sharing by parasitic components while connecting source and drain of CMOS transistors There are
situations in a logic that permit the use of circuits that can automatically precharge themselves (i.e., reset
themselves) after some prescribed delays. These circuits are hence called postcharge or self-resetting logic
which are widely used in dynamic logic circuits. Overall performance of various adder designs is
evaluated by using Tanner tool . The earlier and the proposed SRLGDI primitives are simulated using
Tanner EDA with BSIM 0.250 lm technology with supply voltage ranging from 0 V to 5 V in steps of 0.2 V.
On comparing the various SRLGDI logic adders, the proposed adder shows low power, delay and low
PDP among its counterparts.
Link Stability and Energy Aware routing Protocol for Mobile Adhoc NetworkIOSR Journals
Abstract: MOBILE ad hoc networks (MANETs) have more popularity among mobile network devices and
wireless communication technologies. A MANET is multihop mobile wireless network that have neither a fixed
infrastructure nor a central server. Every node in a MANET will act as a router, and also communicates with
each other. The mobility constraints in mobile nodes will lead to problems in link stability. Energy saving, path
duration and stability will be two major efforts and to satisfy them can be difficult task. A self node which is
present in the network may also consume little energy during the transmission. This proposed approach tries to
account for link stability and for minimum drain rate energy consumption. In order to verify the correctness of
the proposed solution a objective optimization formulation has been designed and a novel routing protocol
called Link-Stability and Energy aware Routing protocols is proposed. This novel routing scheme has been
compared with other two protocols: PERRA and GPSR. The protocol performance has been evaluated in terms
of Data Packet Delivery Ratio, Normalized Control Overhead, Link duration, Nodes lifetime, and Average
energy consumption.
Keywords-component; Energy Consumption, Link Stability, Routing, Self node
Performance evaluation of MANET routing protocols based on QoS and energy p...IJECEIAES
Routing selection and supporting Quality of Service (QoS) are fundamental problems in Mobile Ad Hoc Network (MANET). Many different protocols have been proposed in the literature and some performance simulations are made to address this challenging task. This paper discusses the performance evaluation and comparison of two typical routing protocols; Ad Hoc On-Demand Distance Vector (AODV) and Destination-Sequenced DistanceVector (DSDV) based on measuring the power consumption in network with varing of the QoS parameters. In this paper, we have studied and analyzed the impact of variations in QoS parameter combined with the choice of routing protocol, on network performance. The network performance is measured in terms of average throughput, packet delivery ratio (PDR), average jitter and energy consumption. The simulations are carried out in NS-3. The simulation results show that DSDV and AODV routing protocols are less energy efficient. The main aim of this paper is to highlight the directions for the future design of routing protocol which would be better than the existing ones in terms of energy utilization and delivery ratio.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Ijeee 24-27-energy efficient communication for adhoc networksKumar Goud
Energy Efficient Communication for Adhoc Networks
1SK.Nagula Meera 2Dr. D.Srinivasa Kumar 3Dr. D.Srinivasa Rao
Research Scholar Professor & Principal Professor, ECE department
ECE department, JNTU Hyderabad Hosur Institute of Technology and Science
Errandapalli Village, Beerpalli PO JNTU College of Engineering Hyderabad(Autonomous)
Ramapuram (via), Krishnagri Dt., Tamilnadu
Abstract: A mobile accidental network (MANET) may be an assortment of nodes equipped with wireless communications and a networking capability while not central network management. The method of wireless networks within the applications like transferring video files is subjected to twin constraints. Each step-down of power and different QOS needs like delay, throughputs square measure need to be bewaring properly. Mobile accidental Networks square measure a lot of perceptive to those problems wherever every mobile device is active sort of a router and consequently, routing delay adds significantly to overall end-to-end delay. This paper presents a survey on power economical routing protocols for Mobile Ad-Hoc Networks. This survey focused on recent progress on power saving algorithms. Additionally we recommend one power aware technique which can cut back power consumption yet as increase the lifespan of node and network.
Keywords: Mobile, Ad-Hoc networks, QOS, MANET, IBSS, ATIM, DPSM.
ENERGY EFFICIENT NODE RANK-BASED ROUTING ALGORITHM IN MOBILE AD-HOC NETWORKSIJCNCJournal
Mobile Ad-hoc Network (MANET) is an emerging technology, infrastructure less with self-organizing, selfhealing, multi-hop wireless routing networks in real time. In such networks, many routing problems arise due to complexity in the network mobility which results from difficulty in achieving energy efficient routing
in the field of MANET. Due to the dynamic nature and the limited battery energy of the mobile nodes, the communication links between intermediate relay nodes may fail frequently, thus affecting the routing performance of the network and also the availability of the nodes. Though existing protocols are not
concentrating about communication links and battery energy, node links are very important factor for improving quality of routing protocols because Node Rank helps us to determine whether the node is within transmission range or out of transmission range through considering residual energy of the node during the routing process. This paper proposes a novel Energy Efficient Node Rank-based Routing (EENRR)
algorithm which includes certain performance metrics such as control overhead and residual energy in order to improve the Packet Delivery Ratio (PDR), and Network Life Time (NLT) from its originally observed routing performance obtained through other existing protocols. Simulation results show that, when the number of nodes increases from 10 to 100 nodes, EENRR algorithm increases the average residual energy by 31.08% and 21.26% over the existing Dynamic Source Routing (DSR) and Energy Efficient Delay Time Routing (EEDTR) protocols, respectively. Similarly it increases the PDR by 45.38% and 28.3% over the existing DSR and EEDTR protocols respectively.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
WISHBONE BUS ARCHITECTURE – A SURVEY AND COMPARISONVLSICS Design
The performance of an on-chip interconnection architecture used for communication between IP cores depends on the efficiency of its bus architecture. Any bus architecture having advantages of faster bus clock speed, extra data transfer cycle, improved bus width and throughput is highly desirable for a low cost, reduced time-to-market and efficient System-on-Chip (SoC). This paper presents a survey of WISHBONE bus architecture and its comparison with three other on-chip bus architectures viz. Advanced Microcontroller Bus Architecture (AMBA) by ARM, CoreConnect by IBM and Avalon by Altera. The WISHBONE Bus Architecture by Silicore Corporation appears to be gaining an upper edge over the other three bus architecture types because of its special performance parameters like the use of flexible
arbitration scheme and additional data transfer cycle (Read-Modify-Write cycle). Moreover, its IP Cores are available free for use requiring neither any registration nor any agreement or license.
Energy Aware Routing Protocol for Energy Constrained Mobile Ad-hoc Networks IJECEIAES
Dynamic topology change and decentralized makes routing a challenging task in mobile ad hoc network. Energy efficient routing is the most challenging task in MANET due to limited energy of mobile nodes. Limited power of batteries typically use in MANET, and this is not easy to change or replace while running communication. Network disorder can occur for many factors but in middle of these factors deficiency of energy is the most significant one for causing broken links and early partition of the network. Evenly distribution of power between nodes could enhance the lifetime of the network, which leads to improving overall network transmission and minimizes the connection request. To discourse this issue, we propose an Energy Aware Routing Protocol (EARP) which considers node energy in route searching process and chooses nodes with higher energy levels. The EARP aim is to establish t he shortest route from source to destination that contains energy efficient nodes. The performance of EARP is evaluated in terms of packet delivery ratio, network lifetime, end-to-end delay and throughput. Results of simulation done by using NS2 network simulator shows that EARP can achieve both high throughput and delivery ratio, whereas increase network lifetime and decreases end-to-end delay.
SECTOR TREE-BASED CLUSTERING FOR ENERGY EFFICIENT ROUTING PROTOCOL IN HETEROG...IJCNCJournal
One of the main challenges for researchers to build routing protocols is how to use energy efficiently to extend the lifespan of the whole wireless sensor networks (WSN) because sensor nodes have limited battery power resources. In this work, we propose a Sector Tree-Based clustering routing protocol (STB-EE) for Energy Efficiency to cope with this problem, where the entire network area is partitioned into dynamic sectors (clusters), which balance the number of alive nodes. The nodes in each sector only communicate with their nearest neighbour by constructing a minimum tree based on the Kruskal algorithm and using mixed distance from candidate node to base station (BS) and remaining energy of candidate nodes to determine which node will become the cluster head (CH) in each cluster? By calculating the duration of time in each round for suitability, STB-EE increases the number of data packets sent to the BS. Our simulation results show that the network lifespan using STB-EE can be improved by about 16% and 10% in comparison to power-efficient gathering in sensor information system (PEGASIS) and energy-efficient PEGASIS-based protocol (IEEPB), respectively.
Energy efficient load balanced routing protocol for wireless sensor networkscsandit
Telecommunications is increasingly vital to the society at large, and has become essential to
business, academic, as well as social activities. Due to the necessity to have access to
telecommunications, the deployment requires regulations and policy. Otherwise, the deployment
of the infrastructures would contribute to environment, and human complexities rather than
ease of use.
However, the formulation of telecommunication infrastructure deployment regulation and
policy involve agents such as people and processes. The roles of the agents are critical, and are
not as easy as it meant to belief. This could be attributed to different factors, as they produce
and reproduce themselves overtime.
This paper presents the result of a study which focused on the roles of agents in the formulation
of telecommunication infrastructures deployment regulation and policy. In the study, the
interactions that take place amongst human and non-human agents were investigated. The study
employed the duality of structure, of Structuration theory as lens to understand the effectiveness
of interactions in the formulation of regulations, and how policy is used to facilitate the
deployment of telecommunications infrastructure in the South African environment.
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Addition is a fundamental arithmetic operation that is broadly used in many VLSI systems, such as application-specific digital signal processing (DSP) architectures and microprocessors. This addition module is also the core of other arithmetic operations such as subtraction, multiplication, division and address generation. The prime objective of this project is to design a full-adder having low-power consumption and low propagation delay which may result in the efficient implementation of modern digital systems. This model is referred as “hybrid” because of the combination of two different design logic styles namely CMOS logic and pass transistor logic. Performance parameters such as power, delay and hence energy were compared with the existing designs such as complementary CMOS logic full adder. In the existing hybrid systems, over 28 transistors were used. While the optimized hybrid full adder circuit reduces this count to 8 transistors, it still obtains better energy efficiency. Further the proper working of proposed full adder is verified by applying it in a Ripple carry Adder circuit.
Low Power-Area Design of Full Adder Using Self Resetting Logic with GDI Techn...VLSICS Design
Various electronic devices such as mobile phones, DSPs,ALU etc., are designed by using VLSI (Very
Large Scale Integration) technology. In VLSI dynamic CMOS logic circuits are concentrating on the Area
,reducing the power consumption and increasing the Speed by reducing the delay. ALU (Arithmetic Logic
Circuits) are designed by using adder, subtractors, multiplier, divider, etc.Various adder circuits designs
have been proposed over last few years with different logic styles. To reduce the power consumption
several parameters are to be taken into account, such as feedthrough, leakage power single-event upsets,
charge sharing by parasitic components while connecting source and drain of CMOS transistors There are
situations in a logic that permit the use of circuits that can automatically precharge themselves (i.e., reset
themselves) after some prescribed delays. These circuits are hence called postcharge or self-resetting logic
which are widely used in dynamic logic circuits. Overall performance of various adder designs is
evaluated by using Tanner tool . The earlier and the proposed SRLGDI primitives are simulated using
Tanner EDA with BSIM 0.250 lm technology with supply voltage ranging from 0 V to 5 V in steps of 0.2 V.
On comparing the various SRLGDI logic adders, the proposed adder shows low power, delay and low
PDP among its counterparts.
Implementation of Area Effective Carry Select AddersKumar Goud
Abstract: In the design of Integrated circuit area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data processing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this paper 16 bit, 32 bit, 64 bit and 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. However, the Regular CSLA is still area-consuming due to the dual Ripple-Carry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA; the Modified SQRT CSLA has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT CSLA provide better outcomes than the Regular Linear CSLA and Regular SQRT CSLA respectively. This project was aimed for implementing high performance optimized FPGA architecture. Modelsim 10.0c is used for simulating the CSLA and synthesized using Xilinx PlanAhead13.4. Then the implementation is done in Virtex5 FPGA Kit.
Keywords: Field Programmable Gate Array (FPGA), efficient, Carry Select Adder (CSLA), Square-root CSLA (SQRTCSLA).
DESIGN AND PERFORMANCE ANALYSIS OF HYBRID ADDERS FOR HIGH SPEED ARITHMETIC CI...VLSICS Design
Adder cells using Gate Diffusion Technique (GDI) & PTL-GDI technique are described in this paper. GDI technique allows reducing power consumption, propagation delay and low PDP (power delay product) whereas Pass Transistor Logic (PTL) reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Performance comparison with various Hybrid Adder is been presented. In this paper, we propose two new designs based on GDI & PTL techniques, which is found to be much more power efficient in comparison with existing design technique. Only 10 transistors are used to implement the SUM & CARRY function for both the designs. The SUM and CARRY cell are implemented in a cascaded way i.e. firstly the XOR cell is implemented and then using XOR as input SUM as well as CARRY cell is implemented. For Proposed GDI adder the SUM as well as CARRY cell is designed using GDI technique. On the other hand in Proposed PTL-GDI adder the SUM cell is constructed using PTL technique and the CARRY cell is designed using GDI technique. The advantages of both the designs are discussed. The significance of these designs is substantiated by the simulation results obtained from Cadence Virtuoso 180nm environment.
Comparative Performance Analysis of Low Power Full Adder Design in Different ...ijcisjournal
This paper gives the comparison of performance of full adder design in terms of area, power and delay in
different logic styles. Full adder design achieves low power using the Transmission Gate logic compared to
all other topologies such as Basic CMOS, Pass Transistor and GDI techniques but it make use of more
number of transistors compared to GDI. GDI occupies less area compared to all other logic design styles.
This paper presents the simulated outcome using Tanner tools and also H-Spice tool which shows power
and speed comparison of different full adder designs. All simulations have been performed in 90nm, 45nm
and 22nm scaling parameters using Predictive Technology Models in H-Spice tool.
The paper presents a low Power consumption plays a vital role in the present day VLSI technology. Power consumption of an electronic device can be reduced by adopt changed design styles. Multipliers play a most important role in high concert systems. This project focus on a novel energy efficient technique called adiabatic logic which is based on energy renewal principle and power is compared by designing a multiplier. CMOS technology plays a main role in designing low power consuming devices, compared to different logic family CMOS has less power dissipation. Adiabatic logic method is assumed to be an attractive solution for low power electronic applications. By using Adiabatic techniques energy dissipation in PMOS network can be minimized and selection of energy stored at load capacitance can be recycled instead of dissipated as heat. Tanner EDA tools are used for simulation.
PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED VLSICS Design
Designing high-speed low-power circuits with CMOS technology has been a major research problem for many years. Several logic families have been proposed and used to improve circuit performance beyond that of conventional static CMOS family. Fast circuit families are becoming attractive in deep submicron technologies since the performance benefits obtained from process scaling are decreasing as feature size decreases. This paper presents CMOS differential circuit families such as Dual rail domino logic and pseudo Nmos logic their delay and power variations in terms of adder design and logical design. Domino CMOS has become the prevailing logic family for high performance CMOS applications and it is extensively used in most state-of-the-art processors due to its high speed capabilities. The drawback of domino CMOS is that it provides only non-inverting functions because of its monotonic nature. Dual-Rail Domino logic, (also known as clocked Cascade voltage switch logic where both polarities of the output are generated, provides a robust solution to this problem.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 7, JULY 199MalikPinckney86
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 7, JULY 1997 1079
Low-Power Logic Styles: CMOS
Versus Pass-Transistor Logic
Reto Zimmermann and Wolfgang Fichtner,Fellow, IEEE
Abstract—Recently reported logic style comparisons based on
full-adder circuits claimed complementary pass-transistor logic
(CPL) to be much more power-efficient than complementary
CMOS. However, new comparisons performed on more efficient
CMOS circuit realizations and a wider range of different logic
cells, as well as the use of realistic circuit arrangements demon-
strate CMOS to be superior to CPL in most cases with respect
to speed, area, power dissipation, and power-delay products.
An implemented 32-b adder using complementary CMOS has
a power-delay product of less than half that of the CPL version.
Robustness with respect to voltage scaling and transistor sizing,
as well as generality and ease-of-use, are additional advantages
of CMOS logic gates, especially when cell-based design and logic
synthesis are targeted. This paper shows that complementary
CMOS is the logic style of choice for the implementation of
arbitrary combinational circuits if low voltage, low power, and
small power-delay products are of concern.
Index Terms—Adder circuits, CPL, complementary CMOS,
low-voltage low-power logic styles, pass-transistor logic, VLSI
circuit design.
I. I NTRODUCTION
T HE increasing demand for low-power very large scaleintegration (VLSI) can be addressed at different de-
sign levels, such as the architectural, circuit, layout, and
the process technology level [1]. At the circuit design level,
considerable potential for power savings exists by means of
proper choice of a logic style for implementing combinational
circuits. This is because all the important parameters governing
power dissipation—switching capacitance, transition activity,
and short-circuit currents—are strongly influenced by the
chosen logic style. Depending on the application, the kind
of circuit to be implemented, and the design technique used,
different performance aspects become important, disallowing
the formulation of universal rules for optimal logic styles. In-
vestigations of low-power logic styles reported in the literature
so far, however, have mainly focused on particular logic cells,
namely full-adders, used in some arithmetic circuits. In this
paper, these investigations are extended to a much wider set of
logic gates, and with that, to arbitrary combinational circuits.
The power dissipation characteristics of various existing logic
styles are compared qualitatively and quantitatively by actual
logic gate implementations and simulations under realistic cir-
cuit arrangements and operating conditions [2]. Investigations
of sequential elements, such as latches and flip-flops, were
Manuscript received November 20, 1996; revised January 29, 1997.
The authors are with the Integrated Systems Laboratory, Swiss Federal
Institute of Technology (ETH), CH-8092 Zurich, Switzerland.
Publisher It ...
Digital standard cell library Design flowijsrd.com
Commercial library cells are companies 'proprietary information and understandably companies usually impose certain restrictions on the access and use of their library cells. Those restrictions on commercial library cells severely hamper VLSI research and teaching activities of academia. To address the problem the goal of this paper is to discuss the development of standard cell library. This involves in creating new standard cells, layout design, simulation and verification of each standard cell and finally characterization of all cells for timing and functional properties.
CMOS LOW POWER CELL LIBRARY FOR DIGITAL DESIGNVLSICS Design
Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems.
However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have
brought power dissipation as another critical design factor. Low power design reduces cooling cost and
increases reliability especially for high density systems. Moreover, it reduces the weight and size of
portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since
dynamic power is proportional to V2
dd and static power is proportional to Vdd, lowering the supply voltage
and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required
performance.
In case of static power, the power is consumed during the steady state condition i.e when there are no
input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to
facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized.
Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel
devices. In this paper we have been proposed the new CMOS library for the complex digital design using
scaling the supply voltage and device dimensions and also suggest the methods to control the leakage
current to obtain the minimum power dissipation at optimum value of supply voltage and transistor
threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um) and TSMC
(90nm) technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and
simulations.
HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...VLSICS Design
High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and 0.9v). The observed results reveal power consumption and power delay product (PDP) improvements compared to existing FA counterparts.
Current Comparison Domino based CHSK Domino Logic Technique for Rapid Progres...IJECEIAES
The proposed domino logic is developed with the combination of Current Comparison Domino (CCD) logic and Conditional High Speed Keeper (CHSK) domino logic. In order to improve the performance metrics like power, delay and noise immunity, the redesign of CHSK is proposed with the CCD. The performance improvement is based on the parasitic capacitance, which reduces on the dynamic node for robust and rapid process of the circuit. The proposed domino logic is designed with keeper and without keeper to measure the performance metrics of the circuit. The outcomes of the proposed domino logic are better when compared to the existing domino logic circuits. The simulation of the proposed CHSK based on the CCD logic circuit is carried out in Cadence Virtuoso tool.
Design High Performance Combinational Circuits Using Output Prediction Logic-...IOSRJECE
With the continuously increasing demand for low power & high speed VLSI circuits the brain storming among the scientists, inventors & researchers to find the techniques required to design such high performance circuits is also increasing day by day. In the answer to this search several design techniques have been found. Output prediction logic-OPL technique is one of such newly introduced techniques. OPL is a technique that can be applied to conventional CMOS logic families in order to obtain considerable speedups. Speedups of two to three times over static CMOS logic are demonstrated for a variety of combinational circuits. When applied to static CMOS the OPL retains the restoring nature of underlying logic family. In case of OPL applied to the pseudo NMOS & domino logic, the problem of excessive power dissipation is solved & speedups more than static CMOS logic is obtained
LOGIC OPTIMIZATION USING TECHNOLOGY INDEPENDENT MUX BASED ADDERS IN FPGAVLSICS Design
Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. Therefore, careful optimization of the adder is of the greatest importance. This optimization can be attained
in two levels; it can be circuit or logic optimization. In circuit optimization the size of transistors are manipulated, where as in logic optimization the Boolean equations are rearranged (or manipulated) to optimize speed, area and power consumption. This paper focuses the optimization of adder through technology independent mapping. The work presents 20 different logical construction of 1-bit adder cell in CMOS logic and its performance is analyzed in terms of transistor count, delay and power dissipation. These performance issues are analyzed through Tanner EDA with TSMC MOSIS 250nm technology. From this analysis the optimized equation is chosen to construct a full adder circuit in terms of multiplexer. This logic optimized multiplexer based adders are incorporated in selected existing adders like ripple carry
adder, carry look-ahead adder, carry skip adder, carry select adder, carry increment adder and carry save adder and its performance is analyzed in terms of area (slices used) and maximum combinational path delay as a function of size. The target FPGA device chosen for the implementation of these adders was Xilinx ISE 12.1 Spartan3E XC3S500-5FG320. Each adder type was implemented with bit sizes of: 8, 16, 32, 64 bits. This variety of sizes will provide with more insight about the performance of each adder in terms of area and delay as a function of size.
Extremely Low Power FIR Filter for a Smart Dust Sensor ModuleCSCJournals
Digital filters are common components in many applications today, also in for sensor systems, such as large-scale distributed smart dust sensors. For these applications the power consumption is very critical, it has to be extremely low. With the transistor technology scaling becoming more and more sensitive to e.g. gate leakage, it has become a necessity to find ways to minimize the flow of leakage in current CMOS logic. This paper studies sub-threshold source coupled logic (STSCL) in a 45-nm process. The STSCL can be used instead of traditional CMOS to meet the low power and energy consumption requirements. The STSCL style is in this paper used to design a digital filter, applicable for the audio interface of a smart dust sensor where the sample frequency will be 44.1 kHz. A finite-length impulse response (FIR) filter is used with transposed direct form structure and for the coefficient multiplication five-bit canonic signed digit [7] based serial/parallel multipliers were used. The power consumption is calculated along with the delay in order to present the power delay product (PDP) such that the performance of the sub-threshold logic can be compared with corresponding CMOS implementation. The simulated results shows a significant reduction in energy consumption (in terms of PDP) with the system running at a supply voltage as low as 0.2 V using STSCL.
Design and Analysis of Multi Vt and Variable Vt based Pipelined Adder for Lo...VLSICS Design
Majority of Digital Signal Processing (DSP) applications require arithmetic blocks such as multipliers and adders for hardware realization of complex algorithms. Power consumption of arithmetic blocks need to be minimized by use of low power techniques. In this paper, an experimental setup is developed to identify the sources of power dissipation and remedies that can be adopted to minimize power dissipation in arithmetic blocks. Use of low power techniques such as Multi Vt, variable Vt, pipelining, geometry scaling and use of appropriate load capacitance have been used to reduce power dissipation. A 4-bit pipelined adder is designed and the power dissipation is reduced to 4.17µW from 9.6µW. The designed pipelined adder can be used for DSP applications.
.
Design and Analysis of Multi Vt and Variable Vt based Pipelined Adder for Low...VLSICS Design
Majority of Digital Signal Processing (DSP) applications require arithmetic blocks such as multipliers and adders for hardware realization of complex algorithms. Power consumption of arithmetic blocks need to be minimized by use of low power techniques. In this paper, an experimental setup is developed to identify the sources of power dissipation and remedies that can be adopted to minimize power dissipation in arithmetic blocks. Use of low power techniques such as Multi Vt, variable Vt, pipelining, geometry scaling and use of appropriate load capacitance have been used to reduce power dissipation. A 4-bit pipelined adder is designed and the power dissipation is reduced to 4.17µW from 9.6µW. The designed pipelined adder can be used for DSP applications.
Similar to NEW DESIGN METHODOLOGIES FOR HIGH-SPEED MIXED-MODE CMOS FULL ADDER CIRCUITS (20)
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Online aptitude test management system project report.pdfKamal Acharya
The purpose of on-line aptitude test system is to take online test in an efficient manner and no time wasting for checking the paper. The main objective of on-line aptitude test system is to efficiently evaluate the candidate thoroughly through a fully automated system that not only saves lot of time but also gives fast results. For students they give papers according to their convenience and time and there is no need of using extra thing like paper, pen etc. This can be used in educational institutions as well as in corporate world. Can be used anywhere any time as it is a web based application (user Location doesn’t matter). No restriction that examiner has to be present when the candidate takes the test.
Every time when lecturers/professors need to conduct examinations they have to sit down think about the questions and then create a whole new set of questions for each and every exam. In some cases the professor may want to give an open book online exam that is the student can take the exam any time anywhere, but the student might have to answer the questions in a limited time period. The professor may want to change the sequence of questions for every student. The problem that a student has is whenever a date for the exam is declared the student has to take it and there is no way he can take it at some other time. This project will create an interface for the examiner to create and store questions in a repository. It will also create an interface for the student to take examinations at his convenience and the questions and/or exams may be timed. Thereby creating an application which can be used by examiners and examinee’s simultaneously.
Examination System is very useful for Teachers/Professors. As in the teaching profession, you are responsible for writing question papers. In the conventional method, you write the question paper on paper, keep question papers separate from answers and all this information you have to keep in a locker to avoid unauthorized access. Using the Examination System you can create a question paper and everything will be written to a single exam file in encrypted format. You can set the General and Administrator password to avoid unauthorized access to your question paper. Every time you start the examination, the program shuffles all the questions and selects them randomly from the database, which reduces the chances of memorizing the questions.
NUMERICAL SIMULATIONS OF HEAT AND MASS TRANSFER IN CONDENSING HEAT EXCHANGERS...ssuser7dcef0
Power plants release a large amount of water vapor into the
atmosphere through the stack. The flue gas can be a potential
source for obtaining much needed cooling water for a power
plant. If a power plant could recover and reuse a portion of this
moisture, it could reduce its total cooling water intake
requirement. One of the most practical way to recover water
from flue gas is to use a condensing heat exchanger. The power
plant could also recover latent heat due to condensation as well
as sensible heat due to lowering the flue gas exit temperature.
Additionally, harmful acids released from the stack can be
reduced in a condensing heat exchanger by acid condensation. reduced in a condensing heat exchanger by acid condensation.
Condensation of vapors in flue gas is a complicated
phenomenon since heat and mass transfer of water vapor and
various acids simultaneously occur in the presence of noncondensable
gases such as nitrogen and oxygen. Design of a
condenser depends on the knowledge and understanding of the
heat and mass transfer processes. A computer program for
numerical simulations of water (H2O) and sulfuric acid (H2SO4)
condensation in a flue gas condensing heat exchanger was
developed using MATLAB. Governing equations based on
mass and energy balances for the system were derived to
predict variables such as flue gas exit temperature, cooling
water outlet temperature, mole fraction and condensation rates
of water and sulfuric acid vapors. The equations were solved
using an iterative solution technique with calculations of heat
and mass transfer coefficients and physical properties.
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
An Approach to Detecting Writing Styles Based on Clustering Techniquesambekarshweta25
An Approach to Detecting Writing Styles Based on Clustering Techniques
Authors:
-Devkinandan Jagtap
-Shweta Ambekar
-Harshit Singh
-Nakul Sharma (Assistant Professor)
Institution:
VIIT Pune, India
Abstract:
This paper proposes a system to differentiate between human-generated and AI-generated texts using stylometric analysis. The system analyzes text files and classifies writing styles by employing various clustering algorithms, such as k-means, k-means++, hierarchical, and DBSCAN. The effectiveness of these algorithms is measured using silhouette scores. The system successfully identifies distinct writing styles within documents, demonstrating its potential for plagiarism detection.
Introduction:
Stylometry, the study of linguistic and structural features in texts, is used for tasks like plagiarism detection, genre separation, and author verification. This paper leverages stylometric analysis to identify different writing styles and improve plagiarism detection methods.
Methodology:
The system includes data collection, preprocessing, feature extraction, dimensional reduction, machine learning models for clustering, and performance comparison using silhouette scores. Feature extraction focuses on lexical features, vocabulary richness, and readability scores. The study uses a small dataset of texts from various authors and employs algorithms like k-means, k-means++, hierarchical clustering, and DBSCAN for clustering.
Results:
Experiments show that the system effectively identifies writing styles, with silhouette scores indicating reasonable to strong clustering when k=2. As the number of clusters increases, the silhouette scores decrease, indicating a drop in accuracy. K-means and k-means++ perform similarly, while hierarchical clustering is less optimized.
Conclusion and Future Work:
The system works well for distinguishing writing styles with two clusters but becomes less accurate as the number of clusters increases. Future research could focus on adding more parameters and optimizing the methodology to improve accuracy with higher cluster values. This system can enhance existing plagiarism detection tools, especially in academic settings.
Forklift Classes Overview by Intella PartsIntella Parts
Discover the different forklift classes and their specific applications. Learn how to choose the right forklift for your needs to ensure safety, efficiency, and compliance in your operations.
For more technical information, visit our website https://intellaparts.com
Harnessing WebAssembly for Real-time Stateless Streaming PipelinesChristina Lin
Traditionally, dealing with real-time data pipelines has involved significant overhead, even for straightforward tasks like data transformation or masking. However, in this talk, we’ll venture into the dynamic realm of WebAssembly (WASM) and discover how it can revolutionize the creation of stateless streaming pipelines within a Kafka (Redpanda) broker. These pipelines are adept at managing low-latency, high-data-volume scenarios.
6th International Conference on Machine Learning & Applications (CMLA 2024)ClaraZara1
6th International Conference on Machine Learning & Applications (CMLA 2024) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of on Machine Learning & Applications.
6th International Conference on Machine Learning & Applications (CMLA 2024)
NEW DESIGN METHODOLOGIES FOR HIGH-SPEED MIXED-MODE CMOS FULL ADDER CIRCUITS
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.2, June 2011
DOI : 10.5121/vlsic.2011.2207 78
NEW DESIGN METHODOLOGIES FOR
HIGH-SPEED MIXED-MODE CMOS
FULL ADDER CIRCUITS
Subodh Wairya1
, Rajendra Kumar Nagaria2
, Sudarshan Tiwari3
Department of Electronics & Communication Engineering,
M.N.N.I.T, Allahabad, India
swairya@gmail.com1
,rkn@mnnit.ac.in2
,stiwari@mnnit.ac.in3
ABSTRACT
This paper presents the design of high-speed full adder circuits using a new CMOS mixed mode logic
family. The objective of this work is to present a new full adder design circuits combined with current mode
circuit in one unit to implement a full adder cell. This paper also discusses a high- speed hybrid majority
function based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure with conventional
static and dynamic CMOS logic circuit. The static Majority function (bridge) design style enjoys a high
degree of regularity and symmetric higher density than the conventional CMOS design style as well as
lower power consumption by using bridge transistors. This technique helps in reducing power
consumption, propagation delay, and area of digital circuits while maintaining low complexity of mixed-
mode logic designs. Dynamic CMOS circuits enjoy area, delay and testability advantages over static
CMOS circuits. Simulation results illustrate the superiority of the new designed adder circuits against the
reported conventional CMOS, dynamic and majority function adder circuits, in terms of power, delay,
power delay product (PDP) and energy delay product (EDP). The design is implemented on UMC 0.18µm
process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and
simulations are carried out on Spectre S.
.
KEYWORDS
Full adder, Majority-Not gate, Dynamic circuits, MOSCAP, Power-delay product (PDP), Very Large Scale
Integrated (VLSI) Circuits, Current mode logic, Hybrid XOR-XNOR circuit, Bridge full adder.
1. INTRODUCTION
Low-power design of VLSI circuits has been identified as a critical technological need in recent
years due to high demand for portable consumer electronics products. With the explosive growth
in laptops, portable personal communication systems and the evolution of the shrinking
technology, the research effort in low-power microelectronics has been intensified and low-power
VLSI systems have emerged high in demand. Adder is one of the most important components of a
CPU (central processing unit), Arithmetic logic unit (ALU), floating-point unit and address
generation unit like cache or memory access unit.
Digital circuit designers have always been encountered in a tradeoff between speed and power
consumption to improve their design’s performance. There are standard implementations with
various logic styles that have been used in the past to design full-adder cells [16-38] and these are
used for the comparison in this paper. Although they all have similar function, the way of
producing the intermediate nodes and the transistor count are varied. Different logic styles tend to
favour one performance aspect at the expense of the others. The logic style used in logic gates
basically influences the speed, size, power dissipation, and the wiring complexity of a circuit. The
circuit delay is determined by the number of inversion levels, the number of transistors in series,
the transistor sizes (i.e. channel widths) and the intra-cell wiring capacitances. The circuit
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size depends on the number of transistors, their size and the wiring complexity. Some of them use
one logic style for the whole full adder and others use more than one logic style for their
implementation.
In addition, full-adders are important components in other applications such as digital signal
processing (DSP) architectures and microprocessor. Arithmetic functions such as addition,
subtraction, multiplication and division are some examples which use adder as a main building
block [1-7]. In nano-scaling, the biggest power consumption is static power dissipation.
Depending on the application, the kind of circuit implemented, and the design techniques used,
different performance aspects become important, disallowing the formulation of universal rules
for optimal logic styles.
There are two types of full adders in case of logic structure. One is static style and the other is
dynamic style. Static full adders are commonly more reliable, simpler and of lower power than
dynamic ones. Dynamic is an alternative logic style to design a logic function. It has some
advantages in comparison with static mode such as faster switching speeds, no static power
consumption, non-ratioed logic, full swing voltage levels and less number of transistors. For an N
input logic function, it requires N+2 transistors versus 2N transistors in the standard CMOS logic.
The area advantage comes from the fact that the pMOS network of a dynamic CMOS gate
consists of only one transistor. This also results in a reduction in the capacitive load at the output
node, which is the basis for the high-speed advantage. Dynamic CMOS logic style provides high
performance because this logic style is constructed with only high mobility nMOS transistors.
Also, due to the absence of the pMOS transistors, the input capacitance is lower. Dynamic full
adders suffer from charge sharing, high power due to high switching activity, clock load and
complexity. However, dynamic full adders are faster and some times more compact than static
full adders. Many researchers have combined these two structures and have proposed hybrid
dynamic-static full adders.
Domino CMOS circuits fall under the category of Dynamic CMOS logic, which gives advantage
in terms of testability over static CMOS circuits [31]. The inherent problem with Domino CMOS
circuit is that it suffers from noise margin problem due to charge redistribution between parasitic
capacitances at the internal nodes of the circuit, which may result in false output. Domino is
nonratioed logic with faster switching speed and less silicon area required as compared to the full
static CMOS logic [3-5]. Domino logic consists of a single clock, which is used to precharge the
dynamic node of the circuit in precharge phase and to evaluate the function made by nMOS
network in evaluation phase. As technology scaling continues, allowing for more logic gates per
chip, complex parallel prefix schemes, and fast adder design become viable. In modern CMOS
technologies, transistor sizing has been used to find the optimal trade off between speed and
energy consumption of an adder [32].
To summarize, some of the performance criteria are considered in the design and evaluation of
adder cells and some are utilized for the ease of design, robustness, silicon area, delay, and power
consumption. The rest of this paper is organized as follows: Power consideration in digital CMOS
circuits is explained in Section 2. Section 3 explores a review of the full adder design in different
logic styles. A review of logic styles with majority functions have been discussed in Section 4. In
Section 5, implementations of Majority Function based hybrid full adder methodologies (HyFA1-
HyFA5) and mixed mode full adder designs (MixFA1-MixFA3) are discussed. In Section 6 the
reported and new majority function based full adder design topologies are simulated and the
simulation results analyzed and compared. Finally, Section 7 concludes the paper.
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2. POWER CONSIDERATION IN DIGITAL CMOS
Power is one of the vital resources. Hence, the designers try to save it when designing a system.
Power dissipation is dependent on the switching activity, node capacitances (made up of gate,
diffusion, and wire capacitances), and control circuit size. There are four source of power
dissipation: dynamic switching power due to the charging and discharging of circuit capacitance,
leakage current power from reverse biased diodes and sub-threshold conduction, short-circuit
current power due to finite signal rise/fall times, and static biasing power found in some logic
styles (i.e. pseudo-nMOS).
Dynamic switching power is the major component of overall power dissipation, the low-power
design methodology concentrates on minimizing total capacitance, supply voltage, and frequency
of transistor. For most CMOS circuit design, the short circuit power dissipation is approximately
5-10% of the total dynamic power. The sub-threshold current is proportional to the transistor
device size (W/L) and an exponential function of the supply voltage. Thus, the current may be
minimized by reducing the transistor sizes, and by reducing the supply voltage.
Scaling in the supply voltage appears to be the most well-known means to reduce power
consumption. However, the lower-supply voltage increases circuit delay and degrades the
drivability of cells designed with certain logic style. One of the important obstacles in decreasing
the supply voltage is the large transistor count and Vth loss problem. By selecting proper (W/L)
ratio we can minimize the power dissipation without decreasing the supply voltage.
3. REVIEW OF FULL ADDER TOPOLOGIES
In recent years several variants of different logic styles have been proposed to implement 1-bit
adder cells [33-50]. These have investigated different approaches realizing adders using CMOS
technology, each having its own pros and cons. There are various issues related to the full adders.
Some of them are, power consumption, performance, area, noise immunity, regularity and good
driving ability. Voltage mode in a general shape contains two networks. Each of these networks
contains transistors which behave like a switch. The pull up network is responsible to produce
logical “1” and the pull down network is responsible to produce logical “0”. In these circuits, a
group of switches is connected and the other group is disconnected in every instant. So we need
two groups of switches in constructing these gates, which usually have a contrary operation with
each other and is dependent to the output function. The CMOS family gates are good example for
comprehension of the structure of these circuits. The logical Boolean expressions between the
inputs and outputs are expressed as:
C.B.AC.B.AC.B.AC.B.ASum +++= 1
C.B.AC.B.AC.B.AC.B.AMajorityCarry +++== C.AC.BB.A)BA(CB.A ++=++= 2
Concerns about energy consumption have force digital designers to develop techniques for
improving energy efficiency. Many approaches have been proposed for the optimal construction
of high-performance VLSI adders in a given technology such as: Proper selection of logic family
and prefix, reducing the number of logic stages without increasing gate count, reducing the
number of logic gates, reducing switching activity and reducing the wiring complexity [8-15].
The logic circuits are characterized based on the following logic conditions as defined below:
Logic Depth (LD): The maximum number of logic stages from output to inputs. Each logic gate
is counted as a stage for fully static implementation. However, in compound designs, the
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dynamic gate and the following static gate are counted as one stage. The number of stages
depends on the prefix of design. Minimum depth adders are used when high performance is
required.
Logic Family Selection: In VLSI design, the selection of logic family is dictated by the system
performance target. In structures where the performance target is relaxed or where energy is the
primary constraint, static circuits are preferred due to their lower switching activity. In addition to
that, static circuits are robust and have become more preferable as technology scales down.
However, in high-performance microprocessors, dynamic circuits are often required in order to
achieve desired target frequency. There are two types of dynamic circuit families used in modern
digital systems: (a) dynamic CMOS domino and (b) CMOS compound domino. The main
difference between these families is that CMOS domino utilizes a static inverter at the output,
while CMOS compound domino uses a static inverting logic stage. This helps in reducing the
power by eliminating power hungry dynamic stages and bundling their functionality in the static
CMOS inverting stage. As a summary, static circuits are good for power and domino circuits are
good for speed. Compound domino designs can combine the speed advantage of dynamic designs
and the power advantage of static designs.
Prefix (p): The number of bits combined at each logic stage as defined above. For example, the
two-input dynamic gate and the following two-input static gate is defined as prefix-2 stages for
domino designs. The two-input dynamic gate and the following two-input static gate is defined as
a prefix-4 stage for compound domino designs. Prefix adders are consisting of two blocks,
namely, Sum and Carry blocks. A basic cell in digital computing systems is 1-bit full adder which
has 1-bit inputs (A, B, C) and two 1-bit outputs (Sum and Carry).
Prefix Selection: In static CMOS logic, the prefix is mostly limited to 2 because of transistor
stack height limitation while dynamic designs enable to use of higher prefixes. As prefix of the
design increases the logic depth decreases and it is expected to lead to delay improvement.
However, higher prefix requires more complex gates with increased stack height resulting in
higher gate delay. Therefore, there is an optimal prefix that depends on the design constraints and
implementation.
Load Buffering: Addition of inverters is used to drive the output load because inverters are the
most energy-efficient drivers. Extra delays come from the parasitic and effort delay of the added
inverters. However, the delay of the original circuit will be reduced since it drives added inverters
that are smaller than the output load. In addition, extra energy is consumed by added inverters but
the original circuit’s size is reduced. There is a tradeoff between the saved delay/energy and extra
delay/energy coming from the added inverters. Load buffering provides energy savings for
heavily loaded designs under the same delay constraints. As the load is reduced, the energy
saving of the adder circuit cannot compensate for the extra energy consumed by the extra
inverters. The energy saving of load buffering depends on the driving strength of the original
circuit and the path gain.
3.1 Static Full Adder Topologies
Static CMOS logic styles have been used to implement the low-power 1-bit adder cells. In
general, they can be broadly divided into two major categories: the Complementary CMOS and
the Pass-Transistor logic circuits. The complementary CMOS (C-CMOS) full adder of Figure
1(a) is based on the regular CMOS structure with P type Metal Oxide Semiconductor (pMOS)
pull-up and N type Metal Oxide Semiconductor (nMOS) pull-down transistors [3-8]. The series
transistors in the output stage form a weak driver. Therefore, additional buffers at the last stage
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are required to provide the necessary driving power to the cascaded cells. The advantage of
complementary CMOS style is its robustness against voltage scaling and transistor sizing, which
are essential to provide reliable operation at low voltage and arbitrary transistor sizes. Moreover,
the layout of complementary CMOS circuit is straightforward and area-efficient due to the
complementary transistor pairs and smaller number of interconnecting wires. Another adder
shown in Figure 1(b) is the Complementary Pass Transistor Logic (CPL) with swing restoration,
which uses 32 transistors [6-9].
(a) C-CMOS full adder cell (b) CPL full adder cell (c) Hybrid full adder cell
Figure1. Conventional Static full adders
The Pass-Transistor Logic (PTL) is a better way to implement circuits designed for low power
applications. The low power pass-transistor logic and its design analysis procedures were reported
in [18-21]. The advantage is that one pass-transistor network (either pMOS or nMOS) is
sufficient to implement the logic function, which results in smaller number of transistors and
smaller input load. Moreover, direct VDD-to-ground paths, which may lead to short-circuit energy
dissipation, are eliminated. However, pass-transistor logic has an inherent threshold voltage (Vth)
drop problem. The output is a weak logic “1” when “1” is passed through a nMOS and is a weak
logic “0” when “0” is passed through a pMOS. Therefore, output inverters are used to ensure the
drivability.
Pseudo NMOS full adder cell operates based on pseudo logic, which is referred to ratioed style.
The advantage of pseudo nMOS adder cell is its higher speed (compared to conventional full
adder) and less transistor count. The disadvantage of pseudo nMOS cell is the static power
consumption of the pull-up transistor as well as the reduced output voltage swing, which makes
this adder cell more susceptible to noise. New designed hybrid adder [24] is based on low power
transmission gate and pseudo NMOS gate. Transmission gate consists of a PMOS transistor and
an NMOS transistor that are connected in parallel way, which is a particular type of pass
transistor logic circuit.
Bridge circuits provide a conditional conjunction between two circuit nodes. Since one of the
important parameters in circuit design is the chip area, the bridge style might reduce area or
increase density of transistors in unit of area. Circuits can be implemented faster and smaller than
the conventional as shown in Figure 2(a). Bridge transistors make it possible to create a new path
from supply lines to an output through sharing transistors of different paths [37-39]. These
transistors are arranged in such a way that validates the correctness of the circuit, and also
preserves pull-up and pull-down networks mutually exclusive.
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Figure 2(a) Bridge full adder Figure 2(b) Modified Bridge full adder (24T)
The modified bridge (FA24T) has 24 transistors shown in Figure 2(b) [39]. In FA24T a bridge
circuit generates Carry and another bridge circuit is utilized in series with the prior one to
generate Sum, while in bridge full adder carry and sum signals are produced in a parallel way.
FA24T has a better drivability than bridge. The bridge style circuits can be classified into two
structures. One of them is fully-symmetric style and another one is semi-symmetric. This
classification is based on the similarities amount of P and N networks implementation. If the
implementation of P and N is fully-similar then the style of circuit is fully-symmetric, and if those
implementations are not similar then we could say it is semi-symmetric. A bridge style enables
implementation of CMOS circuits in a symmetric manner which is very useful for VLSI layout
design, placement and routing.
There are standard implementations topologies for the full-adder cell design that have been used
as the basis of comparison in this paper. The Complementary CMOS full adder (C-CMOS) has 28
transistors and the Complementary pass-transistor logic (CPL) full adder has 32 transistors. The
hybrid (26T) full adder is designed in two stages as shown in Figure 1(c). First stage is composed
of six transistors to produce the balanced XOR and XNOR function and additional two series
pMOS and two series nMOS transistors are used to improve the speed of XOR/XNOR circuit.
Second stage is made up of ten transistors and six transistors to create a Carry and Sum output
functions respectively. The transmission gate adder (TGA) uses CMOS transmission gate logic
[27]. It requires complementary input but features a lower transistor number per stack than in the
conventional CMOS) full adder. A XOR circuit based Transmission gate full adder (20T) and
Transmission function full adder (16T) are designed to improve the circuit performance
parameters. Although TGA has few transistors, it has been shown in [27] that extra buffer is
needed at each output due to their weak driving capability. A detailed analysis of adder topologies
is provided in [27]. Reference [17] has proposed a full adder combining both complementary
pass-transistor logic and transmission gate logic. A CPL XOR gate is used to generate the signal
A⊕B, and then, transmission-gate logic based circuits are used to generate full-swing Sum and
Carry outputs. A CPL-TG full adder has better speed and power dissipation than the conventional
CMOS full adder. A low power and high-performance XOR-XNOR based hybrid adder cell
called 3T XOR circuit is discussed in ref. [32]. This technique helps in reducing the power
consumption, the propagation delay, and the area of digital circuits while maintaining low
complexity of full adder logic designs.
3.2. Dynamic Full Adder Topologies
Several variants of Dynamic CMOS logic styles have been used to implement 1-bit full adder cell
[33-34]. The main advantages of these logic styles are: high driving capability, low input
capacitance and high speed operation due to their characteristics, but the main drawback in these
logic styles is power-dissipation due to the higher switching activity than the static logic
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designs. There are two phases in dynamic logic. For a structure where output node is connected to
VDD by a precharge pMOS transistor, there has to be a pull-down network implemented in nMOS.
When Clock=0, circuit enters the precharge phase and when Clock=1, the evaluation phase starts.
All the input values should be changed at precharge phase to avoid the charge sharing problem
and incorrect functionality. It is because once the output discharges at evaluation phase, there will
be no path between output and VDD to charge it again until the next precharge phase.The Sum
output function can be described by the following equation:
Sum = Carry . (A + B + C) + A.B.C 3
3(a) NP CMOS logic 3(b) Dynamic NP-CMOS (Dyn1) 3(c) PN logic
The NP complementary dynamic CMOS full adder [7] is shown in Figure 3(a). It is based on
regular dynamic CMOS designing in two levels with Zipper (NP) technique. The advantage of
NP complementary dynamic CMOS style is its performance, but power consumption is high. The
reported circuit is to use NP-CMOS (Zipper) logic style to implement the 1-bit full adder cell as
shown in Figure 4(a) [34]. In the first stage the Carry function is obtained by using the bridge
style [9]. In the second stage the Sum function is gained according to the equation (3). This
design has 16 transistors. It has full swing voltage levels. Clock and Clock signals cause both
stages of the circuit to enter the evaluation phase simultaneously. The PN complementary
dynamic CMOS full adder is shown in Figure 3(c). It is implemented in two level dynamic
CMOS logic style with PN technique.
4(a) Multi-output Dynamic logic 4(b) Multi-output Dynamic (Dyn2) adder
Figure 3-4 Conventional Dynamic full adders
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The Multi Output dynamic logic is shown in Figure 4(a) [3]. This design uses one clock signal,
which is in contrast to NP and PN complementary designs that use two complementary clock
signals, but the speed of this circuit is reduced due to the pMOS transistors used in its design. The
other disadvantage of this implementation is that this circuit is not full swing, because discharging
the load capacitance of Sum is done through pMOS transistors. Multi-Output dynamic logic
design is introduced with the aim of enhancing the previous reported design as shown in Figure
4(b). Two pMOS transistors are used to charge the outputs in precharge phase. The bridge style is
used to obtain Carry function and then, Carry itself creates the Sum function. After adding the
transistors needed for the inverted inputs to the ones in the design, there will be total 21
transistors.
4. LOGIC STYLES WITH MOSCAP MAJORITY FUNCTION
The Majority function is a logic circuit that performs as a majority vote to determine the output of
the circuits [35-36]. This function has only odd numbers of input. Its output is equal to ‘1’ when
the number of inputs logic ‘1’ is more than logic ‘0’. An efficient majority function may be
designed by using MOSCAP.
4.1. Majority Not Function
The majority structure is implemented by three input capacitors. These three input capacitors
prepare an input voltage that is applied for driving static CMOS inverter. For implementation, the
majority not function circuit as shown in Figure 5(a), high threshold voltage (Vth) transistors have
been used.
Figure 5(a) Implementation of MOSCAP Majority Not Function
The majority gates may be designed with more inputs by this method by increasing the number of
input capacitors. The capacitor network is used to provide voltage division for implementing
majority logic. When the majority of inputs are ‘0’, the output of capacitor network is considered
as logic ‘0’ by the CMOS inverter and consequently the output of inverter is VDD. When the
majority of inputs are logic ‘1’, the output of capacitor network is considered logic ‘1’ by the
CMOS inverter and consequently the output of inverter is 0V. The input capacitance of the
CMOS inverter is negligible and has no effect on operation of the circuit.
Maj
Function
A
B
C
Carry
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4.2. Majority Not Function based Static Logic Gates
Figure 5(b) MOSCAP 10.4f F (NAND, NOR and Majority-NOT) gate
Majority Not function is a logic gate with odd numbers of inputs, and its output is high when the
numbers of logic ‘1’s is less then the number of ‘logic 0’s in the input of the logic gate. The
Majority not function is implemented efficiently by using only capacitors and a static CMOS
inverter. Figure 5(b) shows a circuit used to implement majority-not function with inverter
utilizing high-Vth for both nMOS and pMOS. This circuit can be used to implement NAND gate
using high-Vth nMOS and low-Vth pMOS, and NOR gate using low-Vth nMOS and high-Vth
pMOS.
4.3. Majority Function based Dynamic Logic Gates
The design of three input Majority Not Function, NAND and NOR dynamic CMOS circuits are
shown in Figure 6 [52]. It uses three input capacitances in order to implement different functions
with unique circuit implementation. As shown, the number of transistors is reduced leading to
lower power dissipation. The three inputs Majority Not Function which is implemented with pre-
charge and pre-discharge dynamic CMOS circuit are shown in Figure 6(a) &6(b). In order to
make the pre-discharge circuit working as a Majority Not Function, the threshold voltages of
pMOS transistor is reduced to-0.9 V and the values of input capacitances is selected accurately as
shown in Figure 6 [52]. This reduction in Vth influenced the performance of the circuit, but on the
other side the lower power dissipation is gained.
In order to make the circuit shown in Figure 6(c) working as a Majority Not Function, transistor
MN1must be turned on (Vgs>Vth) when at least two out of the three inputs are high, but if the
transistor turns on when one of its input goes high, the NOR function is implemented and for
implementing NAND function, transistors MN1 must be turned on whenever all the inputs are
high. All these function could be designed by selecting the correct values for input capacitances.
The values of input capacitances for building majority not Function, NAND and NOR is shown in
Figure 6. Simulation results in Table 1 illustrate the comparison of logic gates with MOSCAP
based majority function, static and dynamic logic style at 1V [49].
(a) Majority Function (pre-charge) (b) Majority Function (pre-discharge)
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(c) Majority Not Function (d) NAND (e) NOR
Figure 6. Dynamic CMOS MOSCAP (NAND, NOR and Majority-NOT) logic gate
Table 1. Simulation results of NAND, NOR, Majority Not gates in 0.18µm at room temp.
Design Static logic Majority Function (Dynamic logic)
Delay
(ps)
Power
(µw)
PDP
(10-18
j)
Delay
(ps)
Power(
µw)
PDP
(10-18
j)
Delay
(ps)
Power
(µw)
PDP
(10-
18
j)
NAND 36 0.041 1.47 23 0.038 0.87 27 0.051 1.38
NOR 40 0.042 1.68 27 0.039 1.05 26 0.051 1.33
Maj.NOT 43 0.048 2.06 18 0.038 0.68 36 0.049 1.76
4.4. Majority Function based Current Mode Logic
Current Mode Logic (CML) has some advantages over voltage mode MVL. Implementing
voltage-mode multiple-valued logic (MVL) requires partitioning the total voltage range, zero to
supply voltage in to many discrete levels. Thus, the dynamic range and the noise margin are
highly dependent on the supply voltage. In current-mode circuits, currents are usually defined to
have logical levels that are integer multiple of a reference current unit. Current can be copied,
scaled and algebraically sign-changed with a simple current mirror circuit. The main advantage of
current mode comparing to the voltage mode is that the summation in current mode requires no
extra elements. Another feature in current mode is that the direction of current can be used to
show the sign and as a result the additional bit for representing the sign in numeric system, can be
eliminated.
The main feature in current mode circuits is that we can design various logic circuits using
threshold detector by changing threshold value and sometimes by increasing or decreasing the
number of inputs. The designing of threshold value is possible by changing only the threshold
detector transistors dimensions. As can be observed, the uniform structure of current mode
circuits, easily allows the designer to increase the number of inputs, while in the voltage mode,
this is only possible with increasing the number of transistors. The implementation of majority
function in current mode [53-58] with given equation I1I2+I1I3+I2I3, is shown in Figure 7. If the
sum of the inputs is greater than logic 1.5 (threshold value) then the output current will be equal
to reference current else, there is no current at the output.
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(a) Current mode with a source output (b) Current mode with a sink output
Figure7. Logic Circuit in Current Mode Majority Function
The threshold function is simply implemented by CMOS inverter. In the circuit illustrated in Figure
7(a), both inputs and outputs are of current in gender. M1 transistor converts quantities of the input
currents into voltage and provide it to an inverter. The threshold voltage of the inverter is pointed out
with TD and provided to the designer. M2 transistor is switched on and off under the control of the
inverter, thus connects and disconnects the output current. Despite of the constant shape of this circuit,
it can implement the functions of AND, OR, Majority Function, Majority Not Function and many
other functions. If different quantities of TD are specified, the produced functions in the output of this
circuit are also changed. As an instance, with a threshold detector from 0.5 OR gate, with the threshold
detector from 2.5 AND gate and also with TD from 2 majority function shall be obtained. The circuit
in Figure 7(b) is same as the circuit of Figure 7(a) with a difference that in the output which is sinking
instead of source.
5. MAJORITY FUNCTION ADDER TOPOLOGIES.
The basic design full adder includes two 3-input NAND and NOR gates with majority not function
inputs as shown in Figure 8. As the Table 2 exhibit, Sum is different in merely two places with
Majority not function when inputs are 000 or 111. The value of these two functions are not equal at
A=B=C= ‘0’ and A=B=C= ‘1’. Therefore, we correct these two states by using a pMOS and an nMOS
transistor. These transistors must be arranged in such a way that ensures the correctness of the circuit
as shown in Figure 8. Three capacitors are used to generate the Carry (majority not function) output.
In six mid-states of the Table 2 the Sum output is equal to Carry (majority not function) and the MP1
and MN1 transistors are off. But in all one input state and all zero input state the Sum is obtained by
the NAND and NOR gates, respectively. In order to design circuit operations in the given state one
nMOS and one pMOS pass transistor are added to the circuit as shown in Figure 5.
Table 2. Truth table for Majority function full adder outputs
Inputs Full adder output functions
A B C Carry Carry Sum ),,,,( CarryCarryCBAMajSum= ),,,,( SumSumCBAMajCarry=
0 0 0 0 1 0 0 0
0 0 1 0 1 1 1 0
0 1 0 0 1 1 1 0
0 1 1 1 0 0 0 1
1 0 0 0 1 1 1 0
1 0 1 1 0 0 0 1
1 1 0 1 0 0 0 1
1 1 1 1 0 1 1 1
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Figure 8 Basic design methodologies for Majority function based full adder circuit
As discussed before, using a static CMOS inverter and three capacitors, the majority
function is attained by replacing NAND and NOR gates with three capacitor and inverter.
In view of the fact that three separate capacitors are used for designing each of these
gates and that these input capacitors influence the circuit performance by replacing the
number of capacitors, the overall performance of the system can be improved. Therefore
we have eliminated six out of the nine capacitors.
(MajFA1) (MajFA2)
Figure 9 Majority full adder topologies using 3input MOSCAP with CMOS inverters
The schematic of the majority full adder is based on MOSCAP majority not function with only
static CMOS inverter as shown in Figure 9. Simulation results illustrate that the reported adder
circuits having low PDP works properly at low voltage [49]. Outputs of the circuit will be
connected to power supply or ground and therewith, the circuit has good drive capability. In this
design, “a” and” b” inverters implement NOR and NAND functions respectively. These inverter
based full adders are a suitable structure for the construction of low-power and high-performance
VLSI systems.
The basic idea to generate Sumfrom Carry by using 5 inputs majority-not function with three
input signals (A,B,C ) and with two Carry input signals are illustrated in Table 2 [47-48].
)C,B,A(MajCarry = , )C.,B,A(MajCarry = 4
)Carry,Carry,C,B,A(MajSum = 5
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The majority full adder design is implemented by means of majority function, based on CMOS
technology. This design is based on the idea that the carry output function is the same as 3- input
majority function shown in Figure 10.
Figure 10 Basic design approach for Majority Not function based full adder cell
5.1 Reported Majority Function Hybrid and Mixed mode Full Adder Topologies
As reported in HyFA1, hybrid full adder circuit of Figure 11(a) uses 16 transistors. Its output Sum
function is based on 5 input majority-not gates. In this design, the first majority-not gate is
implemented with a high-performance CMOS bridge circuit [48]. This design uses more
transistors, called bridge transistors, sharing transistors of different paths to generate new paths
from supply lines to circuit outputs. The bridge design style offers more regularity and higher
performance than the other CMOS design styles and is completely symmetric in structure. Using
the bridge circuit leads to reduction of delay and power consumption of the full adder cell and it
also increases the robustness of the circuit
Figure 11(a) HyFA1 (Majority Bridge) Figure 11(b) MixFA1 (Current mode Dynamic)
In MixFA1 mixed mode full adder circuit of Figure 11(b) uses 16 transistors. Its output Sum
function is based on Current mode majority function. In this design, the first majority-not gate is
implemented with a high-performance dynamic CMOS bridge circuit [48]. The advantage of this
adder cell is higher speed, lower transistor count and it compromises noise margin.
Maj.
Function
A
B
Carry
C
Maj.
Function
B
C
Sum
A
14. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.2, June 2011
91
5.2 Newly Design Hybrid Full Adder Topologies
Figure 12(a) Design 1(HyFA2) Figure 12(b) Design 2 (HyFA3)
The design1 HyFA2 uses 14 transistors and 3 input capacitors. Full adder output Carry function is
designed with 3 input Majority Not function logic and output Sum function generated in bridge
logic style as shown in Figure 12(a). In this design, the majority-not gate is implemented with a
capacitors and high-performance CMOS bridge circuit. The advantage of this adder cell is higher
speed, lower transistor count and it compromises noise margin. This type of circuit is preferred in
smaller area requirement with lesser delay at low voltage.
The design2 (HyFA3) uses 15 transistors and is based on dynamic CMOS structure. Full adder
output Carry function is designed with 3 input Majority Not function logic and output Sum
function generated in dynamic C-CMOS logic style as shown in Figure 12(b). The advantages of
the dynamic CMOS logic style are its robustness against voltage scaling and transistor sizing
(high noise margins) and thus reliable operation at low voltages and arbitrary (even minimal)
transistor sizes (ratio less logic) are possible. Input signals are connected to transistors gates only,
which facilitates the usage and characterization of logic cells.
Figure 13(a) Design 3 (HyFA4) Figure 13(b) Design 4 (HyFA5)
The design3 HyFA4 uses 16 transistors and is based on regular CMOS structure with pull-up and
pull-down transistors. Full adder output Carry function is designed in C-CMOS logic style and
output Sum function generated from 5 input Majority Not function logic as shown in Figure
13(a). The Pseudo nMOS based Majority-Function full adder design4 (HyFA5) operates on
pseudo logic, which is referred to ratioed style. Full adder output Carry function is designed in
Pseudo logic style and output Sum function generated from 5 input Majority Not function logic as
shown in Figure 13(b). This adder circuit uses 12 transistors to realize the negative addition
15. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.2, June 2011
92
function. In this circuit all the pMOS are replaced with a single pMOS and its gate is connected to
ground terminal. The advantage of this adder cell is higher speed, lower transistor count and it
compromises noise margin.
5.3 Newly Design Mixed Mode Full Adder Topologies
In mixed mode designing the majority not function in voltage mode is the matching part of
majority function in current mode. In the current mode, the current which is pulled from the Carry
transistor must be twice as much as the current from input transistors to satisfy the following
equations [33]. ),,,,( CarryCarryCBAMajSum = 5
Figure 14(a) Design 5 (MixFA2) Figure 14(b) Design 6 (MixFA3)
In MixFA2, full adder circuit of Figure 14(a) uses 19 transistors. Its output Sum function is based
on current mode majority function. In this design, the first majority-not gate is implemented with
a high-performance Static CMOS bridge circuit [35]. In MixFA3 full adder output Carry function
is designed with 3 input Majority Not function logic and output Sum function generated in current
mode majority function logic style as shown in Figure 14(b). In this design, the majority-not gate
is implemented with capacitors. The advantage of this adder cell is higher speed, lower transistor
count and it compromises noise margin. This type of circuit is preferred in smaller area
requirement with lesser delay at low voltage.
6. SIMULATION RESULTS
The simulation have been performed for different supply voltage ranging from 1V to 1.8V, which
allow us to compare the speed degradation and average power dissipation of the reported adder
topologies. The results of the designed circuits in this paper are compared with a reported
standard CMOS full adder circuits. To compare 1-bit full adder’s performance, we have evaluated
delay and power dissipation by performing simulation runs on a Cadence environment using
0.18-µm CMOS technology at room temperature. To perform a comparative study of simulation
performance of various full adder topologies, the same input test pattern have used 3input signals
(A, B, C) and these signals are square waves of equal on and off times.
Each 1-bit full adder has been analyzed in terms of propagation delay, average power dissipation
and their products. The values of delay, power, power-delay product and energy delay product of
C-CMOS, CPL, Hybrid Majority design full adders are measured. The PDP (10-15
)j and EDP (10-
24
)sj are a quantitative measure of the efficiency and a compromise
16. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.2, June 2011
93
between power dissipation and speed. PDP and EDP are particularly important when low power
and high speed operation are needed and its comparison at 1.8V is shown in Figure 16.
For each transition, the delay is measured from 50% of the input voltage swing to 50% of the
output voltage swing. The maximum delay is taken as the cell delay. The delays of the newly
designed circuits are compared with other reported circuits. Figure 15 shows that the delay of the
reported dynamic adders is low as compared with conventional static full adder circuits. Newly
designed mixed mode (MixFA2 & MixFA3) adder circuits have very low propagation delay as
shown in Figure 16.
Delay (ns) comparison of full adder cells Power (µW) comparison of full adder cells
Figure 15 Delay & Power comparison of conventional full adder cells
Power, delay, PDP and EDP factors of the designed circuits are simulated at 1.8V for 0.18µm
CMOS technology. However, simulation results show that the newly designed circuits can work
at other supply voltages and also it is completely robust to voltage variations. The area overhead
of the designed circuits is lower than that of reported conventional adders and also than that of
some other adder circuits. By optimizing the capacitance parameters and transistor sizes of the
full adders that have been considered, it is possible to reduce the delay of all adders without
significantly increasing the power consumption, and transistor sizes can be set to achieve
minimum power delay product (PDP) and energy delay product (EDP). All adders are designed
with minimum transistor sizes initially and then simulated.
Table 3. Simulation results for delay, power, PDP and EDP of the Majority Hybrid and Current
Mixed Mode adder cells at 1.8V VDD
Design MajFA1 MajFA2 HyFA1 HyFA2 HyFA3 HyFA4 HyFA5 MixFA1 MixFA2 MixFA3
Delay
(ns)
0.291 0.162 0.086 0.112 0.057 0.109 0.112 0.013 0.014 0.014
Power
(µW)
26.51 55.62 4.40 12.70 14.22 2.91 57.2 231 285 301
PDP
(10-15
)
7.710 9.010 0.380 1.422 0.811 0.317 6.406 3.003 3.93 4.214
EDP
(10-24
)
2.24 1.460 0.033 0.159 0.046 0.035 0.718 0.039 0.054 0.059
17. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.2, June 2011
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Figure16 Delay and EDP of Hybrid and Mixed mode adder cells at 1.8V VDD
6.1. Results and Discussion
6.1.1. Average Power Comparison
In this section, we discuss the effect of supply voltage variation v/s. average power. In our
analysis the current mode full adders (MixFA1-MixFA3) are the most power consuming circuit at
1.8V due to constant current source. The power consumption worsens with the increase in the
voltage supply. Hybrid full adder HyFA4 has the lowest power consumption in comparison to the
other simulated adder circuits. It worked successfully at low voltage supply. The MixFA3 full
adder consumes higher power due to use of high power consuming current mode majority
function in a single unit.
6.1.2. Delay Comparison
Similar to previous simulation setup, the average propagation delay has been studied with the
supply voltage variation in all circuits. Simulation results in Figure 14 show that MajFA1 is the
best circuit in terms of speed at 1.8V VDD. It has high delay and high sensitivity against voltage
scaling. Design2 HyFA3 is the fastest full adder circuit. MixFA2 keeps a high distance from
design MixFA1 and shows better performance than MixFA3. Mixed mode adders have almost the
same delay at 1.8V.
6.1.3. Energy delay product (EDP) Comparison
Figure 16 shows the energy delay product of the Hybrid and mixed mode adder circuits. The
conditions are same as power and delay simulation setups. In low voltages, designed MixFA1 is
better than MixFA2 and new hybrid adders. Table 3 shows HyFA1 and HyFA4 have almost same
EDP. All the HyFA4 has better EDP than all new design circuits.
7. CONCLUSION
In this paper, we designed a new class of mixed mode logic family for CMOS technology. An
extensive performance analysis of 1-bit MOSCAP based hybrid majority function and current
mixed mode function full adders have been presented. Different adder logic styles have been
implemented, simulated, analyzed and compared. Using the adder categorization and hybrid-
CMOS design style, many full adders can be conceived. As an example, new full adders designed
using hybrid-majority function design style with C-CMOS, Bridge and Pseudo logic circuit are
presented in this paper that targets minimum delay and EDP. The characteristics of the newly
18. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.2, June 2011
95
designed adder circuits are compared against reported designed adders based on the worst case
delay, average power dissipation, power-delay product (PDP) and energy delay product (EDP).
The comparison of simulation results shows that the performance of the newly mixed mode
designs are superior in terms of high-speed as against other reference designs of full adder
circuits.
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Authors
Subodh Wairya is an Assistant Professor of Electronics Engineering department at the
Institute of Engineering & Technology, (IET) Lucknow, Uttar Pradesh, India. He did M.E.
(Telecommunication) from Jadavpur University, Kolkata and B.TECH (Electronics
Engineering.) from H.B.T.I., Kanpur, India. He has more than fifteen years experience in
academics. He has contributed research papers in National & International reputes. He has
also served as Scientist ‘B’ in Defence Research & Development Organization (DRDO)
and Graduate Engineer (Design Project) in Hindustan Aeronautical Limited (HAL),
Lucknow. He has been on several academic examination assignments for different
Universities. He is a life member for professional & Technical societies like ISTE
(LM33784), IETE (M189081L), Institute of Engineers (MIE M133861-1). Pursuing Ph.D
on “Performance Evaluation of High-Speed CMOS Circuit Designs” from Motilal Nehru
National Institute of Technology (M.N.N.I.T) Allahabad, India. Email:
swairya@gmail.com
Rajendra Kumar Nagaria is an Associate Professor of Electronics & Communication
Engineering at Motilal Nehru National Institute of Technology (MNNIT), Allahabad,
India. He received B.Tech. and M.Tech. in Electronics Engineering from Kamla Nehru
Institute of Technology (KNIT) Sultanpur, India and Ph.D. (Engg.) from Jadavpur
University, Kolkata, India. He has been over 22 years of teaching & research experience.
He has published more than forty research papers of National & International reputes. His
name is enlisted in an exclusive directory Marquis Who’s Who in the world. He is also
nominated for the award as International Educator of the year 2005, by International
Biographical Centre, Cambridge England. He is fellow of professional bodies like Institute
of Engineers (India) and Indian Society for Technical Education. He has guided the thesis
of many PG students and presently Six research scholars are working under his
supervision. His area of interest is Mixed-mode signal processing, High-Speed
networks/VLSI Design. Email: rkn@mnnit.ac.in
Sudarshan Tiwari received the B.Tech. degree in Electronics Engineering from I.T.BHU,
Varanasi, India in 1976, the M.Tech. degree in Communication Engineering from the same
institution in 1978 and PhD degree in Electronics and Computer Engineering from IIT
Roorkee, India in 1993. Presently, he is Professor and Head of Department of Electronics
and Communication Engineering. Motilal Nehru National Institute of Technology
(M.N.N.I.T), Allahabad, India. He has also worked as Dean Research and Consultancy of
the institute from June 2006 till June 2008. He has more than 28 years of teaching and
research experience in the area of communication engineering and networking. He has
supervised a number of M.Tech and PhD thesis. He has served on the program committee
of several seminars, workshops and conferences. He has worked as a reviewer for several
conferences and Journals both nationally and internationally. He has published over 100
research papers in different Journals and Conferences. He has served as a visiting
professor at Liverpool John Moore’s University, Liverpool, UK. He has completed several
research projects sponsored by government of India. He is a life member of Institution of
Engineers (India) and Indian society of Technical Education (India), he is a member of
Institution of Electrical and Electronics Engineers (USA). His current research interest
include, in the area of WDM optical networks, wireless ad hoc & sensor networks and next
generation networks. Email: stiwari@mnnit.ac.in.