UPTU 3rd yr seminar presentation on the said topic for Electronics And Communication Engineering Branch.

1. mGate : Magnetologic Gate
Bundelkhand Institute Of Engineering And Technology
Electronics And Communication Engineering Department
Submitted By :-
Sumit Sagar
150433****
Under Guidance Of :-
Dr. Satish Kumar Singh
(Assistant Professor)
B.I.E.T. ,Jhansi.

2. Outline Of Presentation
 Introduction
 MTJ
 Previous Works
 Structure of Proposed mGate
 Basic Logic Gates Using mGate
o Inverter
o AND-OR
o XOR-XNOR
 Parameter Analysis
 Simulation Environment
 Advantages
 Disadvantages
 Conclusion
 References

3. Introduction
• In this presentation we introduce a universal magnetologic gate, the mGate for the design of energy
efficient digital circuits.
• Ever decreasing CMOS technology size has enabled the integration of large number of transistors in a
unit of area.
• However there are serious concerns such as power consumption and temperature that has limited the
design of such systems.
• Higher power consumption increases the chip temperature, which in turn severely challenges the chip
reliability.
• To provide an attractive tradeoff between the mentioned design issues, i.e., the low power consumption,
low occupied area, and high performance that are mostly conflicting, an emerging provision should be
devised.
• Recently, designers have focused on the design and implementation of circuits using spintronic devices
because of their great features, such as very low static power consumption, non-volatility, and low
occupation area to name a few.

4. MTJ : Magnetic Tunnel Junction
Spintronic devices are based on the up or down spin of the electrons, whereas the
traditional semiconductor electronics devices were based on electrons or holes. Magnetic
tunnel junction (MTJ), is one of the spintronic devices consisting of two ferromagnetic
thin-film layers (e.g., CoFe), the free layer and the fixed layer, with an oxide-tunneling
barrier (e.g., MgO) between the two magnetic layers. An MTJ resistance is different for
parallel and anti-parallel states.

5. The ratio between the two resistance values is named tunnel magnetoresistance ratio
(TMR) defined by :-
Since a large TMR ratio indicates a large difference between the P and AP state
resistances, it can provide a measure of how easily the two states of an MTJ can be
distinguished. These states can be used for creating logic “0” and logic “1” in
digital circuits. The main characteristics of MTJ include robustness to noise, robustness
to high energy particles, non-volatility, and programmability.

6. Previous Works
MTJ based MRAMs
To solve the power dissipation problem, researchers have recently focused on design of
MTJ-based circuit due to the aforementioned attractive features. These can store data
bits using magnetic charges instead of the electrical charges used by dynamic random
access memory. In particular, the non-volatility of MRAM is a major advantage.

7. Structure of Proposed mGate
The proposed multi-application mGate is a novel structure to design the logic gates in all-
magnetic logic circuits model. Figure shows a generic n-input mGate. As shown in
figure, the mGate is based on elements, called mCell. An mCell is a four-terminal element
that has electrically isolated read path (R and R*) and write path (W− and W+). When the
write path is magnetically coupled to the free layer of an MTJ, the resistance state of the
read path changes as determined by the element’s tunneling magnetoresistance. Briefly, by
sending a small current pulse from W− to W+ or W+ to W−, the mCell read path resistance
between R and R* is changed to be high (RH) or low (RL), respectively.

9. Basic Logic Gates Using mGate
Digital electronic circuits are represented by five basic logic operations (NOT, AND, OR,
NAND, and NOR). The electronic circuit performing one of these logic functions is
referred to as a gate.

10. Inverter
Given figure shows the current transfer characteristic of an mGate inverter circuit.
According to Figure, output high-to-low and low-to-high transitions occur at different
input currents. A high-to-low output transition occurs at an input current higher than
the threshold IID = 3.27 μA. A low-to-high output transition occurs at an input current
lower than thethreshold IIU = −4.25 μA. The output retains the value if the input is
within these two currents.This circuit can be employed for cleaning up noisy signals.

11. And-OR
According to figure, when Rref is 729 Ώ , only if one of mCells A or B is equal to Rh, their equal
resistance (Rfunc) is greater than Rref ; therefore, Isrc is created and the output is equal to “1.” If Rref is
1041 Ώ , mGate operates as an AND gate. As can be seen, an OR gate and an AND gate are designed only
by connecting three mCells and the regulating of reference part. Given table shows the truth table of these
gates. Given figure shows the inputs/outputs waveforms for AND and OR gates extracted by HSPICE
simulations.

12. XOR-XNOR
XOR and XNOR are very important gates in the design of various widely used circuits,
such as error detection and correction circuits.

13. Parameter Analysis

14. Simulation Environment
In order to evaluate the efficiency of the proposed mGate, various circuits have been
simulated. Simulations were performed by the HSPICE tool. A data analysis of signals has
been carried out by Cosmos scope software.

15. Advantages
o Simulation results reveal that the circuits designed by mGates exhibit ultra-low power
consumption, high logic density, and acceptable speed operation.
o Leakage currents, the main responsible parameter for static power dissipation during idle
mode, are increasing dramatically in sub-100 nm processes of CMOS. It was observed
that comparing with 32 nm CMOS circuits, mGate circuits reduce power consumption
by about 94%.

16. Disadvantages
o Despite the mentioned benefits, as opposed to pure transistor-based circuits, there is
no comprehensive standard and synthesis tool to produce gates and functions with
magnetologic elements.
o The delay of mGate is more than that of CMOS gate.

17. Conclusion
As silicon industry moves into the 45 nm technology and below, it has faced serious
challenges in CMOS device downscaling. Two of the most important challenges are
the ever-increasing static power dissipation and variation in device characteristics.
These complaints are the embodiments of CMOS approaching atomistic and quantum-
mechanical physics boundaries. They are frequently cited as the reason that why
Moore’s law has been broken. So we introduced mGate logic gates, which are based on
mCells, four-terminal MTJ cells, that have electrically separated read and write paths.
Very low power consumption make mGate-based circuits suitable for ultralow power
applications, such as wireless sensor nodes, implantable medical device, and even
spacecraft.

18. References
[1] N. S. Kim et al., “Leakage current: Moore’s law meets static power,” Computer, vol. 36, no.
12, pp. 68–75, Dec. 2003.
[2] W. N. He et al., CMOS VLSI Design: A Circuits And Systems Perspective, 3/E. India: Pearson
Ed., 2006.
[3] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage current mechanisms and
leakage reduction techniques in deep-submicrometer CMOS circuits,” Proc. IEEE, vol. 91, no.
2, pp. 305–327, Feb. 2003.
[4] P. Gupta, A. B. Kahng, P. Sharma, and D. Sylvester, “Gate-length biasing for runtime-leakage
control,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 8, pp. 1475–
1485, Aug. 2006.
[5] https://www.google.com
[6] https://www.wikipedia.org
[7] ieeexplore.ieee.org/
[8] IEEE Transactions On Magnetics, vol. 53, no. 10, Oct. 2017