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Low Voltage SRAM DesignChallenges and Solutions Adam Teman, Janna Mezhibovsky, Dr. Alexander Fish Low Power Circuits and Systems Lab (LPC&S) The VLSI Systems Center Ben-Gurion University May 4, 2011
Lecture Contents Introduction Standard SRAMs at Low Voltages Existing Solutions LPC&S SRAM Design Activities
Introduction SRAMs are one of the main on-chip power consumers, often comprising 50% of silicon area and 50% of static power. 3 Total cache size per chip www.anandtech.com
Introduction The standard SRAM implementation is the 6T bitcell. Both write and read power are quadratically dependenton VDD. 4
Introduction During hold cycles, the 6T SRAM presents both subthreshold (DIBL) and gateleakage. Both are exponentially dependent on supply voltage. 5 DIBL Gate Bias and Oxide Thickness
Cutoff Devices with VDS=VDD suffer from DIBL. ,[object Object],0 0 VDD VDD VDD VDD VDD VDD Introduction 6
Introduction The best way to aggressively reduce SRAM power is to lower the operating voltage. Quadratic reduction of Dynamic Power Exponential Reduction of DIBL Exponential Reduction of Gate Leakage 7
Standard SRAMs at Low Voltages The positive feedback of the 6T structure provides strong bi-stability and large noise margins. 8
Standard SRAMs at Low Voltages However, under read and write operations, the noise margins are depleted. 9
Standard SRAMs at Low Voltages Read and write accesses are ratioed operations and require two basic drive strength constraintsto succeed. 10
Standard SRAMs at Low Voltages Under strong-inversion operation, sizing the devices is usually sufficient. However, global and local mismatch cause loss of functionality at voltages under ~700mV-800mV 11
Existing Solutions The basic solution to the read margin problem is decoupling the readout path. 12
Existing Solutions A differential decoupled readout provides better Sense Amplifier operation: 13
Existing Solutions Write margin still limits 8T operation to ~700mV, therefore write assist techniques are required. 14 Virtual Supply
Existing Solutions Word Line boosting and RSCE sizing have been implemented to improve 8T functionality. 15 Boosted WL RSCE
Existing Solutions Several readout path implementations have been proposed to fight off-row leakage. 16
Our work Very few groups have tried to “think outside the box” and modify the internal cell structure. We have proposed an internal supply feedback concept that cuts off the supply to reduce internal leakage. 17
Our work One example is the Quasi-Static RAM cell that floats the internal nodes, drastically reducing leakage. This and other solutionsare under intensiveexamination and testing. 18
Questions? 19

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Track e low voltage sram - adam teman bgu

  • 1. Low Voltage SRAM DesignChallenges and Solutions Adam Teman, Janna Mezhibovsky, Dr. Alexander Fish Low Power Circuits and Systems Lab (LPC&S) The VLSI Systems Center Ben-Gurion University May 4, 2011
  • 2. Lecture Contents Introduction Standard SRAMs at Low Voltages Existing Solutions LPC&S SRAM Design Activities
  • 3. Introduction SRAMs are one of the main on-chip power consumers, often comprising 50% of silicon area and 50% of static power. 3 Total cache size per chip www.anandtech.com
  • 4. Introduction The standard SRAM implementation is the 6T bitcell. Both write and read power are quadratically dependenton VDD. 4
  • 5. Introduction During hold cycles, the 6T SRAM presents both subthreshold (DIBL) and gateleakage. Both are exponentially dependent on supply voltage. 5 DIBL Gate Bias and Oxide Thickness
  • 6.
  • 7. Introduction The best way to aggressively reduce SRAM power is to lower the operating voltage. Quadratic reduction of Dynamic Power Exponential Reduction of DIBL Exponential Reduction of Gate Leakage 7
  • 8. Standard SRAMs at Low Voltages The positive feedback of the 6T structure provides strong bi-stability and large noise margins. 8
  • 9. Standard SRAMs at Low Voltages However, under read and write operations, the noise margins are depleted. 9
  • 10. Standard SRAMs at Low Voltages Read and write accesses are ratioed operations and require two basic drive strength constraintsto succeed. 10
  • 11. Standard SRAMs at Low Voltages Under strong-inversion operation, sizing the devices is usually sufficient. However, global and local mismatch cause loss of functionality at voltages under ~700mV-800mV 11
  • 12. Existing Solutions The basic solution to the read margin problem is decoupling the readout path. 12
  • 13. Existing Solutions A differential decoupled readout provides better Sense Amplifier operation: 13
  • 14. Existing Solutions Write margin still limits 8T operation to ~700mV, therefore write assist techniques are required. 14 Virtual Supply
  • 15. Existing Solutions Word Line boosting and RSCE sizing have been implemented to improve 8T functionality. 15 Boosted WL RSCE
  • 16. Existing Solutions Several readout path implementations have been proposed to fight off-row leakage. 16
  • 17. Our work Very few groups have tried to “think outside the box” and modify the internal cell structure. We have proposed an internal supply feedback concept that cuts off the supply to reduce internal leakage. 17
  • 18. Our work One example is the Quasi-Static RAM cell that floats the internal nodes, drastically reducing leakage. This and other solutionsare under intensiveexamination and testing. 18