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AMBA_APB_pst

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AMBA_APB_pst

  1. 1. B.VAMSI KRISHNA ID:185 Under the guidance of Mrs.BHAVANI,Senior faculty,IIVDT.
  2. 2. •An AMBA-based microcontroller typically consists of a high-performance system backbone bus. •Bus can sustain CPU and DMA devices •Like Direct Memory Access (DMA) devices ,high performance arm processors or high band width memory interface. •Bridge to a narrower APB bus on which the lower bandwidth peripheral devices are located.
  3. 3. •The Advanced Peripheral Bus (APB) is part of the AMBA. •APB is optimized for minimal power consumption and reduced interface complexity. •The AMBA APB should be used to interface to any peripherals which are low bandwidth and do not require the high performance of a pipelined bus interface.
  4. 4. •APB ensures that all signal transitions are only related to the rising edge of the clock. •This improvement means the APB peripherals can be integrated easily into any design flow.
  5. 5. • State diagram • Write transfer • Read transfer • Error response
  6. 6. • Idle:The default state for the peripheral bus. • Setup:When a transfer is required the bus moves into the SETUP state. • Pselx is asserted • The bus only remains in the SETUP state for one clock cycle and will always move to the access state(enable is asserted) on the next rising edge of the clock. • Access: The address, write select, and write data signals must remain stable during the transition from the SETUP to ACCESS state.
  7. 7. • PREADY:Exit from the ACCESS state is controlled by the PREADY signal from the slave: • If PREADY is held LOW by the slave then the peripheral bus remains in the ACCESS state. • If PREADY is driven HIGH by the slave then the ACCESS state is exited and the bus returns to the IDLE state if no more transfers are required. • Alternatively, the bus moves directly to the SETUP state if another transfer follows.
  8. 8. • There are two types of write transfer • With no wait states • With wait states
  9. 9. With wait states With no wait states
  10. 10. •With no wait states•With wait states
  11. 11. Read transfer Write transfer
  12. 12. Master Slave
  13. 13. • The APB bridge is the only bus master on the AMBA APB. In addition, the APB bridge is also a slave on the higher-level system bus. • The bridge unit converts system bus transfers into APB transfers and performs the following functions: • Latches the address and holds it valid throughout the transfer.
  14. 14. • Decodes the address and generates a peripheral select, PSELx. Only one select signal can be active during a transfer. • Drives the data onto the APB for a write transfer. • Drives the APB data onto the system bus for a read transfer. • Generates a timing strobe, PENABLE, for the transfer.
  15. 15. • APB slaves interface very simple and flexible. • For a Write transfer the data can be latched at the following points: • on either rising edge of PCLK, when PSEL is HIGH • on the rising edge of PENABLE, when PSEL is HIGH. • The select signal PSELx, the address PADDR and the write signal PWRITE can be combined to determine which register should be updated by the write operation.
  16. 16. • For Read transfers the data can be driven on to the data bus when PWRITE is LOW and both PSELx and PENABLE are HIGH. While PADDR is used to determine which register should be read
  17. 17. Read Transfer TO AHB Write Transfer from AHB
  18. 18. • From AHB to APB PSLVERR is mapped back to HRESP[1:0] = ERROR for both reads and writes. This is achieved by mapping PSLVERR to the AHB signal HRESP[1:0]. • HRESP[1:0]:OKAY,ERROR,RETRY,SRLIT.
  19. 19. •performance is improved at high-frequency operation. •static timing analysis is simplified by the use of a single clock edge. •no special considerations are required for automatic test insertion. •many Application-Specific Integrated Circuit (ASIC) libraries have a better selection of rising edge registers. •easy integration with cycle based simulators.

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