APB

2. AMBA
 Advanced Microcontroller Bus Architecture (AMBA) is
an architecture that is widely used in system-on-chip
designs, which are found on chip buses.
 The AMBA specification standard is used for designing
high-level embedded microcontrollers.
 It provide technology independence and to encourage
modular system design.
 It strongly encourages the development of reusable
peripheral devices while minimizing silicon infrastructure

3. Typical AMBA system

4. AMBA
 AMBA 5.0 protocol defines six buses/interfaces:
 CHI (Coherent Hub Interface) : is targeting the interface to the
coherent hub that is found in many of today's SoCs
 ACE (AXI Coherency Extensions): It is targeted at high
bandwidth, high clock frequency system designs
 AXI (Advanced extensible Interface)-A high performance
,flexible protocol
 AHB (Advanced High-performance Bus)-retained for
compatibility and to ease the transition
 ASB (Advanced System Bus )- no longer actively supported
 APB (Advanced Peripheral Bus) - retained for support of
simple, low bandwidth peripherals

5. AMBA 2 APB (APB2) AMBA 3 APB 1.0(APB 3) AMBA 3 APB 2.0(APB4)
NO PREADY PREADY PPROT
PSLEVERR PSTROB

6.  PPROT A protection signal to support both non-secure
and secure transactions on APB.
 PSTRB A write strobe signal to enable sparse data
transfer on the write data bus.

7. Introduction:
APB stands for Advanced Peripheral Bus .
The APB is part of the Advanced Microcontroller Bus
Architecture (AMBA) protocol family.
Mainly used as general purpose register based peripherals
such as timers, interrupt controllers, UARTs, I/O ports, etc.
Optimized for minimal power consumption and reduced
interface complexity.
The APB protocol is non pipelined protocol.
In APB Every transfer takes at least two cycles(Setup Phase
and Access Phase).

8. Introduction:
The APB interfaces to any peripherals that are low-
bandwidth and do not require the high performance of a
pipelined bus interface.
It is connected to the system bus via a bridge, helps reduce
system power consumption.
It is also easy to interface.
The APB provides a low-cost interface that is optimized
for minimal power consumption and reduced interface
complexity.
The APB can interface with AHB ,AXI and etc..

9. APB Master
There is a single bus master on the APB, thus there is no
need for an arbiter.
The master drives the address and write buses and also
performs a combinatorial decode of the address to decide
which PSEL x signal to activate.
It is also responsible for driving the PENABLE signal to
time the transfer.
It drives APB data onto the system bus during a read
transfer.

10. APB Master

11. APB Slave
APB slaves have a very simple and flexible interface.
The exact implementation the interface will be
dependent on the design style employed and many
different options are possible.
In this two signals are main which mainly protect the
loss data while transfer of data is taking place they are
PSLVERR and PREADY.

13. Master to Slave Communication

14. Operating States

15.  IDLE - This is the default state of the APB.
 SETUP - When a transfer is required the bus moves
into the SETUP state, where the appropriate select
signal, PSELx, is asserted. The bus only remains in the
SETUP state for one clock cycle and always moves to
the ACCESS state on the next rising edge of the clock.

16.  ACCESS - The enable signal, PENABLE, is asserted in
the ACCESS state. The address, write, select, and write
data signals must remain stable during the transition
from the SETUP to ACCESS state. Exit from the
ACCESS state is controlled by the PREADY signal from
the slave:
 1 - If PREADY is held LOW by the slave then the
peripheral bus remains in the ACCESS state.
 2 - If PREADY is driven HIGH by the slave then the
ACCESS state is exited and the bus returns to the IDLE
state if no more transfers are required.
 Alternatively, the bus moves directly to the SETUP
state if another transfer follows.

17. Write With No Wait states
 The write transfer starts with the address, write data, write signal
and select signal all changing after the rising edge of the clock.
 The first clock cycle of the transfer is called the Setup phase.
 After the following clock edge the enable signal is asserted,
PENABLE, and this indicates that the Access phase is taking
place.
 The address, data and control signals all remain valid throughout
the Access phase. The transfer completes at the end of this cycle.
 The enable signal, PENABLE, is de-asserted at the end of the
transfer.
 The select signal, PSELx, also goes LOW unless the transfer is to
be followed immediately by another transfer to the same
peripheral.

18. With No Wait states

19. Write transfer with wait states
Figure shows how the PREADY signal from the slave can
extend the transfer. During an Access phase, when
PENABLE is HIGH, the transfer can be extended by
driving PREADY LOW.
The following signals remain unchanged for the additional
cycles:
● address, PADDR
● write signal, PWRITE
● select signal, PSEL
● enable signal, PENABLE
● write data, PWDATA.

21. Read With no wait states
The read transfer starts with the address, write signal and
select signal all changing after the rising edge of the clock.
The first clock cycle of the transfer is called the Setup
phase.
After the following clock edge the enable signal is
asserted, PENABLE, and this indicates that the Access
phase is taking place.
The address and control signals all remain valid
throughout the Access phase. The slave must provide the
data before the end of the read transfer.
The transfer completes at the end of this cycle.
The enable signal, PENABLE, is de-asserted at the end of
the transfer.

23. Read With wait states
 Access phase will extends up to PREADY is High. When
Pready is high slave provide PRDATA to the master.

24. Failing Write transfer
 Figure shows an example of a failing write transfer that
 completes with an error.

25. Read transfer
 A read transfer can also complete with an error
response, indicating that there is no valid read data
available.
 a read transfer completing with an error response.

26. Write Followed by Read

27. Error response
 You can use PSLVERR to indicate an error condition on
an APB transfer. Error conditions can occur on both
read and write transactions.
 PSLVERR is only considered valid during the last cycle
of an APB transfer, when PSEL, PENABLE, and
PREADY are all HIGH
 It is recommended, but not mandatory, that you drive
PSLVERR LOW when it is not being sampled. That is,
when any of PSEL, PENABLE, or PREADY are LOW.

28.  Transactions that receive an error, might or might not have
changed the state of the peripheral. This is peripheral-
specific and either is acceptable. When a write transaction
receives an error this does not mean that the register within
the peripheral has not been updated.
 Read transactions that receive an error can return invalid
data. There is no requirement for the peripheral to drive
the data bus to all 0s for a read error.
 APB peripherals are not required to support the PSLVERR
pin. This is true for both existing and new APB peripheral
designs. Where a peripheral does not include this pin then
the appropriate input to the APB bridge is tied LOW.

30. Advantages
 Low Power
 Latched address and control
 Simple Interface
 Suitable for many peripherals

31. Disadvantages
 Single Master –Limits parallelism
 Scalability_ performance suffers as bus is loaded
 Single Outstanding request :Poor throughput and
multi threading performance bottleneck