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Flip Flop 
Nugroho Adi Pramono 
nugnux@gmail.com,aravir@me.com 
http://aravir-rose.blogspot.com/p/digital
“But, before that…”
Real Gate
Interfacing 
It must work 
It must NOT damage other circuit
How fast? 
How much current? 
What voltage 
Things we may have overlooked
How Fast? 
As fast as slowest chip 
(chip to chip)
How Fast? 
Irrelevant 
(chip to something else)
How much current?
What voltage
Others Things
Switch Bounce
Switch Bounce
Smile or Smoke?
Smile or Smoke?
Smile or Smoke?
Power Supply
Sequential Logic
Combinational Logic 
some gates 
some inputs 
output (with certainty)
Sequential Logic 
inputs 
gates 
previous state
Sequential Logic 
tombol televisi 
saklar lampu 
bel pintu
Switches 
Latching 
non-Latching
Switches
RS bistable 
SR bistable 
RS Flip-Flop 
SR Flip-Flop 
RS Latch
RS bistable
RS bistable
NAND Latch
(1) = 1 
(3) = 0 atau 1 tergantung (2) 
(5) = 0 
(6) = 1 (sifat NAND) 
(6) — (2) 
gate A punya input 1 semua 
(3) = 0 
(4) = 0 
Q = 0 (reset) 
Q’ = 1 
S = 1, R = 0
(1) = 0 
(3) = 1 
gate B punya input 1 semua 
(3) — (4) = 1 
(5) = R = 1 
(6) = 0 
Q = 1 (set) 
Q’ = 0 
S = 0, R = 1
“nol untuk menyalakan” 
–Active Low Input 
Dan dia hidup bahagia selama-lamanya...
(1) = 0 
(3) = 1 
(5) = 0 
(6) = 1 
Q = 1 
Q’ = 1 
Forbidden 
S = 0, R = 0
S = 1, R = 1 
Tak ada yang terjadi
Switch Debouncer
Alternatif dari 
adalah
Tentukan tabel kebenarannya
Testing the Glitch 
Catcher
latch 
dapatkah mendeteksi perubahan logic state? 
pada durasi yang sangat pendek? 
50 ns
mudah 
gunakan switch 
tekan! 
pasti memantul
mudah lagi 
gunakan switch debouncer 
tekan! 
tak cukup cepat, 10 ms 
alt -> gunakan gerbang logika
Transition effects 
ubah input pada gerbang NOT 
NOT hanya akan membalik sinyal
Sepertinya baik-baik saja
Bagaimana jika intervalnya 10 ns?
Perubahan output ternyata tidak langsung 
memiliki waktu tunda 
waktu yang diperlukan tegangan untuk berjalan 
melalui gate 
transition/propagation time
untuk sesaat, sekitar 10 ns, input dan output 
memiliki logika yang sama (pada NOT)
Apakah bermasalah?
salah satu input dilewatkan ke inverter 
input XNOR selalu memiliki nilai yang berlawanan 
output XNOR selalu nol
Clocked Bistable
Asynchronous 
Go when you like 
Operate immediately when input applied 
All gates 
RS bistable
We don’t Always Want This 
alarm berbunyi sesegera setelah diset 
pesawat take-off segera setelah pilot datang 
koki langsung masak segera setelah bahan datang
Synchronous 
Wait until you told
Clocked RS Bistable
Clocked Input
Clocked Input
Clocked Input
“4 NAND gate, 1 chip 74xx00” 
–Johnny Appleseed
JK Latch
The Golden Rules of JKs 
If J and K different, the Q is always the same as J 
If J and K are 0, nothing happens 
If J and K are 1, the output toggles
Apa Gunanya Clock? 
menentukan respon terhadap input
When does the Clock Tick? 
input harus ada sebelum perubahan clock 
setup time 20 ns 
hold time 0 s (often)
Negative Edge Triggered 
(trailing edge triggered) 
the action occurs at the end of the clock pulse 
just as its logic level chages from 0 to 1 
symbol > o
J=1, K=1
Positive Edge triggering 
(rising/leading edge triggering) 
kebalikan dari trailing edge triggered
J=1, K=1
J=1, K=1
Pulse Triggering 
(master-slave design) 
mirip trailing edge JK
Pulse Triggering 
1. The JK inputs and the Q and NOT Q outputs are isolated. 
2. As soon as the leading edge of the clock pulse reaches 
logic 1, the data enters and is stored inside the JK. 
3. At the end of the clock pulse, when the falling edge 
leaves the logic 1 level, the J and K inputs are 
disconnected preventing any latecomers from getting in. 
4. The data is transferred to the Q and NOT Q output
Pulse Triggering
Pulse Triggering
D flip-flop
D flip-flop
D flip-flop
D flip-flop
D flip-flop
D flip-flop
T flip-flop
T flip-flop
T flip-flop
Selesai 
Dan dia hidup bahagia selama-lamanya...

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