sequential circuits

1. Sequential Circuits
Latches and Flip-Flops

2. Introduction
 A Sequential logic circuit is one
whose Output depends on current
inputs as well as past outputs
(Current state).
 Depends on the history
 Have “memory” property
 Sequential circuit consists of
» Combinational circuit
» Uses feedback (to feed the state
variables)
– Simple feedback
– Uses Latches and Flipflops.
– Ex:Registers,Counters, Sequence
Generators.

4. Latches and Flipflops:
• A latch a Sequential Circuit that Continuously take
the track of the inputs and can change its output at
any time.(Depends on propagation delay of the
internal Circuitry)
• Latch acts as a simple memory element and does
provide any control over the output.
• A flipflop is a Sequential Circuit that normally
samples its inputs and changes its output only
when a Clock Signal is applied.
• A flipflop acts a memory element and also
provides control over the output.

5. Types of Sequential Circuits
In Asynchronous sequential circuits the output of the logic circuit can change
state at any time, as soon as any input changes its state whereas in the case of
synchronous systems a signal namely clock signal is used to determine/control
the exact time at which any output can change its state. These are also called as
clocked sequential circuits.

6. Flip Flop
 A flip flop is a binary storage device. It can
store binary bit either 0 or 1. It has two stable
states HIGH and LOW i.e. 1 and 0.
 It has the property to remain in one state
indefinitely until it is directed by an input
signal to switch over to the other state.
 It is also called bistable multivibrator.
 The basic need of flip flop is to store data.

7. Flip Flop Types:
 SR ("set-reset")
 D ("data" or "delay")
 T ("toggle")
 JK
Flip-flops can be either simple (transparent or
asynchronous) or clocked (synchronous); the
transparent ones are commonly called latches.
The word latch is mainly used for storage
elements, while clocked devices are described
as flip-flops

8.  The SR (Set-Reset) LATCH is one of the
simplest sequential circuit in which the
output of each gate is connected to one of
the inputs of the other gate.
 The circuit has two active HIGH inputs
marked S and R, as well as two outputs, Q
and Q’.
 The output of the S-R latch depends on
current as well as previous inputs or state,
and its state (value stored) can change as
soon as its inputs change.
S-R LATCH

10. RS Latch
 RS latch have two inputs, S and R. S is called
set and R is called reset.
 The S input is used to produce HIGH on Q ( i.e.
store binary 1 in flip-flop).
 The R input is used to produce LOW on Q (i.e.
store binary 0 in flip-flop). Q' is Q
complementary output, so it always holds the
opposite value of Q.
 The output of the S-R latch depends on current
as well as previous inputs or state, and its state
(value stored) can change as soon as its inputs
change.

12. •When S = 0 and R = 0: If we assume Q = 1 and Q' = 0 as initial condition, then
output Q after input is applied would be Q = (R + Q')' = 1 and Q' = (S + Q)' = 0.
Assuming Q = 0 and Q' = 1 as initial condition, then output Q after the input applied
would be Q = (R + Q')' = 0 and Q' = (S + Q)' = 1. So it is clear that when both S and
R inputs are LOW, the output is retained as before the application of inputs. (i.e.
there is no state change).
•When S = 1 and R = 0: If we assume Q = 1 and Q' = 0 as initial condition, then
output Q after input is applied would be Q = (R + Q')' = 1 and Q' = (S + Q)' = 0.
Assuming Q = 0 and Q' = 1 as initial condition, then output Q after the input applied
would be Q = (R + Q')' = 1 and Q' = (S + Q)' = 0. So in simple words when S is
HIGH and R is LOW, output Q is HIGH.
•When S = 0 and R = 1: If we assume Q = 1 and Q' = 0 as initial condition, then
output Q after input is applied would be Q = (R + Q')' = 0 and Q' = (S + Q)' = 1.
Assuming Q = 0 and Q' = 1 as initial condition, then output Q after the input applied
would be Q = (R + Q')' = 0 and Q' = (S + Q)' = 1. So in simple words when S is
LOW and R is HIGH, output Q is LOW.
•When S = 1 and R =1 : No matter what state Q and Q' are in, application of 1 at
input of NOR gate always results in 0 at output of NOR gate, which results in both Q
and Q' set to LOW (i.e. Q = Q'). LOW in both the outputs basically is wrong, so this
case is invalid

13. Clocked RS Flip Flop
 The RS latch flip flop required the direct input but no
clock. It is very use full to add clock to control
precisely the time at which the flip flop changes the
state of its output.
 In the clocked RS flip flop the appropriate levels
applied to their inputs are blocked till the receipt of a
pulse from an other source called clock. The flip flop
changes state only when clock pulse is applied
depending upon the inputs.
 This circuit is formed by adding two AND gates at
inputs to the RS flip flop. In addition to control inputs
Set (S) and Reset (R), thereis a clock input (C) also.

14. The first five lines in the truth table give the static input and output
states.
The last four lines show the state of the outputs after a complete
clock pulse p.
The RS latch shown in the figure is NOR latch.

16. Clocked SR Flip Flop

17. Clocked SR Flip Flop

18. D - FLIP FLOP

19. D - FLIP FLOP

20. JK Flip Flop
 One of the most useful and versatile flip flop is
the JK flip flop the unique features of a JK flip
flop are:
◦ If the J and K input are both at 1 and the clock pulse is
applied, then the output will change state, regardless
of its previous condition.
◦ If both J and K inputs are at 0 and the clock pulse is
applied there will be no change in the output.
◦ There is no indeterminate condition, in the operation
of JK flip flop i.e. it has no ambiguous state.

21.  When J = 0 and K = 0,
These J and K inputs disable the NAND gates, therefore
clock pulse have no effect on the flip flop. In other
words, Q returns it last value.
 When J = 0 and K = 1,
The upper NAND gate is disabled the lower NAND gate
is enabled if Q is 1 therefore, flip flop will be reset (Q =
0 , Q’ =1)if not already in thatstate.
 When J = 1 and K = 0
The lower NAND gate is disabled and the upper NAND
gate is enabled if is at 1, As a result we will be able to
set the flip flop ( Q = 1, Q’ = 0) if not alreadyset.
 When J and K are both high, the clock pulses cause
the JK flip flop to toggle.

24. RACE AROUND CONDITON

25. RACE AROUND CONDITON

26. Master Slave JK Flip Flop

27.  A master slave flip flop contains two clocked
flip flops. The first is called master and the
second slave.
 When the clock is high the master is active.
The output of the master is set or reset
according to the state of the input.
 When clock becomes low the output of the
slave flip flop changes because it become
active during low clock period.
 The final output of master slave flip flop is
the output of the slave flip flop. So the
output of master slave flip flop is available at
the end of a clock pulse.

29. Toggle Flip Flop or T-Flip Flop
 The operation of the T type flip-flop is as
follows:
 A '0' input to 'T' will make the next state
the same as the present state (i.e. T = 0
present state = 0 therefore next state = 0).
 However a '1' input to 'T' will change the
next state to the inverse of the present
state (i.e. T = 1 present state = 0 therefore
next state = 1).

30. T Qn Qn+1
0 0 0
0 1 1
1 0 1
1 1 0

31. EXCITATION TABLE
CHARACTERISTIC TABLE EXCITATION TABLE
Q(n) S R Q(n+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 X
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 X
Q(n)
Q(n+1) S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
TRUTH TABLE
S R Q(n+1)
0 0 NO
CHANGE
0 1 RESET
1 0 SET
1 1 INVALID

32. EXCITATION TABLE
CHARACTERISTIC TABLE EXCITATION TABLE
Q(n) J K Q(n+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
Q(n)
Q(n+1) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
TRUTH TABLE
J K Q(n+1)
0 0 NO
CHANGE
0 1 RESET
1 0 SET
1 1 TOGGLE

33. EXCITATION TABLE
EXCITATION TABLE
Q(n)
Q(n+1) D
0 0 0
0 1 1
1 0 0
1 1 1
CHARACTERISTIC TABLE
D Q Q(n+1)
0 0 0
0 1 0
1 0 1
1 1 1

34. EXCITATION TABLE
EXCITATION TABLE
Q(n)
Q(n+1) T
0 0 0
0 1 1
1 0 0
1 1 1
CHARACTERISTIC TABLE
T Q Q(n+1)
0 0 0
0 1 1
1 0 1
1 1 0

35. FLIPFLOP CONVERSION

36. FLIPFLOP CONVERSION

37. FLIPFLOP CONVERSION

38. FLIPFLOP CONVERSION

39. Counters
 A counter is a register that goes through a
predetermined sequence of states upon the application
of clock pulses
Asynchronous counters
Synchronous counters
 Asynchronous Counters (or Ripple counters)
 the clock signal (CLK) is only used to clock the first FF.
Each FF (except the first FF) is clocked by the preceding
FF.
 Synchronous Counters
the clock signal (CLK) is applied to all FF, which means
that all FF shares the same clock signal
thus the output will change at the same time

40. Asynchronous Counters
 The Asynchronous Counter that counts 4 number
starts from 00 01 10 11 and back to 00 is called
MOD-4 Ripple (Asynchronous) Up-Counter.
 The external clock is connected to the clock input of
the first flip-flop (FF0) only. So, FF0 changes state at
the falling edge of each clock pulse, but FF1 changes
only when triggered by the falling edge of the Q
output of FF0.
 Because of the inherent propagation delay through a
flip-flop, the transition of the input clock pulse and a
transition of the Q output of FF0 can never occur at
exactly the same time.
 Therefore, the flip-flops cannot be triggered
simultaneously, producing an asynchronous operation.

41. The transitions of Q0, Q1 and CLK in the timing diagram below are shown as
simultaneous even though this is an asynchronous counter. Actually, there is
some small delay between the CLK, Q0 and Q1 transitions.
Usually, all the CLEAR inputs are connected together, so that a single pulse can
clear all the flip-flops before counting starts.
The clock pulse fed into FF0 is rippled through the other counters after
propagation delays, like a ripple on water, hence the name Ripple Counter.

42.  A counter with n flip-flops can have 2 to the power
n states. The number of states in a counter is known as
its mod (modulo) number. Thus a 2-bit counter is
a mod-4 counter.
 For a 4-bit counter, the range of the count is 0000 to
1111 (24-1). A counter may count up or count down or
count up and down depending on the input control.The
count sequence usually repeats itself.
 When counting up, the count sequence goes from 0000,
0001, 0010, ... 1110 , 1111 , 0000, 0001, ... etc.
 When counting down the count sequence goes in the
opposite manner: 1111, 1110, ... 0010, 0001, 0000, 1111,
1110, ... etc.

44. Synchronous counters
 A synchronous counter, is one whose outputbits
change state simultaneously, with no ripple.
 The external clock signal is connected to the
clock input of every individual flip-flop within
the counter so that all of the flip-flops are clocked
together simultaneously (in parallel) at the same
time giving a fixed time relationship.
 The result of this synchronization is that all the
individual output bits changing state at exactly the
same time in response to the common clock signal
with no ripple effect.

53. RING COUNTER

54. RING COUNTER

55. RING COUNTER