2. Gates and flip-flops
➢Gates are the building block of the logic
circuits. Their primary function is to perform
decision making operations.
➢Flip-flops are the building blocks of the digital
circuits. Their primary function is to store the
binary bits.
3. Logic circuits are classified into two groups:
Combinational logic circuits
Sequential logic circuits
Basic building
blocks include:
Basic building blocks
include FLIP-FLOPS:
LOGIC CIRCUITS
Logic gates make decisions
Flip Flops have memory
4. Synchronous and Asynchronous Sequential Logic:-
➢Synchronous
– the timing of all state transitions is controlled
by a common clock
– changes in all variables occur simultaneously
➢Asynchronous
–state transitions occur independently of any
clock and normally dependent on the timing of
transitions in the input variables
– changes in more than one output do not
necessarily occur simultaneously
5. Clock:-
➢A clock is a special device that whose
output continuously alternates between 0
and 1.
➢The time it takes the clock to change from 1
to 0 and back to 1 is called the clock period, or
clock cycle time.
➢The clock frequency is the inverse of the
clock period. The unit of measurement for
frequency is the hertz.
➢Clocks are often used to synchronize circuits.
clock period
6. Triggering
➢Sequential circuits are dependant on clock pulses
applies to their inputs.
➢The result of flip-flop responding to a clock input is
called clock pulse triggering, of which there are
four types. Each type responds to a clock pulse in
one of four ways :-
1. High level triggering
2. Low level triggering
3. Positive edge triggering
4. Negative edge triggering
7.
8.
9.
10.
11. Latch
Latch are the bi-stable devices which responds
to the change of input logic levels as they occur.
Latch
Inputs
Complementory output
Q
Q
Q is the primary output
Q is its complemetory
It is said to be in SET state if output Q is high
It is said to be in RESET state if output Q is low
12. R-S Latch using NOR gate
The two inputs, S and R
denote ``set'' and
``reset'' respectively.
The latch has memory,
and the present output
is dependent on the
state of the latch
R S Q Q comment
0 0 Qn Qn Previous
state
0 1 1 0 SET state
1 0 0 1 RESET state
1 1 Not Not Not
defined defined defined
13. R-S Latch using NAND gate
R S Q Q comment
1 1 Qn Qn Previous
state
0 1 1 0 SET state
1 0 0 1 RESET
state
0 0 Not Not Not
defined defined defined
R
Q
Q’
S
14. Level-Sensitive/ Gated RS-Latch
•
•
“Q” only changes when CLK is high (i.e. level-sensitive)
When CLK is high, behavior same as RS latch
E S R Q
0 X X No change
1 0 0 No change
1 0 1 0
1 1 0 1
1 1 1 Undefined Race condition
15. Level-Sensitive D-Latch
➢Make level-sensitive D-latch
from level-sensitive RS-latch
by connecting S = D and R =
not D
➢Due to NOT gate ,S and R will
always be the complements
of each other. hence S=R=0
or S=R=1, these inputs will
never appear. This will avoid
the problems associated
with SR=00 and SR=11
conditions
mal
Comple-
mentary
D Q
Nor
FF
Q
E
E D Q Q comments
0 X Q Q No change
1 0 0 1 Reset
1 1 1 0 Set
16. CLOCKED R-S FLIP-FLOP
S
R
et FF
S Q
eset
R
Q
ASYNCHRONOUS
Outputs of logic circuit can
change state anytime one
or more input changes
S
R
C
et FF
S Q
CLK
Q
R
lock
eset
SYNCHRONOUS
Clock signal determines
exact time at which any
output can change state
17. Flip-flops
❑A flip-flop is a bi-stable device, with inputs,
that remains in a given state as long as power
is applied and until input signals are applied to
cause its output to change.
❑There are four basic different types of flip-
flops:
➢
➢
➢
➢
SR
D
JK
T
18. CLOCKED R-S FLIP-FLOP
Symbols:
Truth Table:
Set
R
mal
Comple-
mentary
Clock
FF Nor
S Q
CLK
eset
R
Q
Clk S R
0 0
0 1
1 0
1 1
Qn Qn
No change
0 1
1 0
Race Race
