This document discusses latches and flip-flops. It describes the SR latch, gated SR latch, D latch, and gated D latch. It also covers edge-triggered flip-flops including the SR, D, and JK flip-flops. The edge-triggered flip-flops are synchronous, bistable devices that change state based on the rising or falling edge of a clock pulse. Common applications of flip-flops include data storage, data transfer, counting, and frequency division.

1. Latches And Flip Flops

2. Outline
a) Latches
b) Edge-Triggered Flip-Flops
c) Flip-Flop Applications

3. Latches
 Multivibrator
 Digital Circuit
 One bit of information
 Temporary Storage Device
 Bistable
 Similar to Flip-Flop
 outputs are constantly
 Output changes by inputs

4. The SR Latch
 Asynchronous device
 Works independently of control signals
 Two inputs S‘ and R' for set and reset respectively
 Two outputs Q and Q‘.
 A set state when Q = 1
 a reset state when Q = 0

6. The Gated S-R Latch
 Enable input(EN)
 sensitive to its inputs all the time
 disable the inputs
 When E =1, the circuit behaves like the normal NAND
implementation of the SR latch except that the S and R inputs are
active high rather than low.
 When E = 0, the latch remains in its previous state regardless of the
S and R inputs.

8. D Latch
 D for "data“
 Transparent Latch
 Simple extension of the gated SR latch
 Removes the possibility of invalid input states
 The D latch outputs the D input whenever the Enable line is high

9. Enable D Q Q’
0 0 Latch
0 1 Latch
1 0 0 1
1 1 1 0

10. Gated D Latch
 When the E input is asserted (E = 1), the Q output follows the D
input
 the latch is said to be “open” and the path from the input D to the
output Q is “transparent”.
 When E is de-asserted (E = 0), the latch is disabled or “closed”, and
the Q output retains its last value independent of the D input

11. The Edge-Triggered Flip-Flops
 Synchronous Bistable Devices
 Bistable Multivibrators
 Clock pulse
 Clock (CLK)
 Not available in IC Form

13. The Edge-Triggered S-R Flip-Flop
 sequential circuits
 two gates
 cross-coupling
 two active low inputs marked S and R

14. The Edge Triggered D Flip-Flop
 The Q output always takes on the state of the D input at the
moment of a rising clock edge
 The D flip-flop can be interpreted as a primitive memory cell, zero-
order hold, or delay line
 These flip flops are very useful, as they form the basis for shift
registers, which are an essential part of many electronic devices

15. Clock D Q Qprev
Rising edge 0 0 X
Rising edge 1 1 X
Non-Rising X Qprev

16. The Edge Triggered J-K Flip-Flop
 The JK flip-flop augments the behavior of the SR flip-flop (J=Set,
K=Reset) by interpreting the S = R = 1 condition as a "flip" or
toggle command
 The characteristic equation of the JK flip-flop is:

17. JK Flip Flop operation
Characteristic table Excitation table
J K Qnext
Comme
nt
Q Qnext J K
Comme
nt
0 0
hold
state
0 0 0 X
No
change
0 1 reset 0 1 1 X Set
1 0 set 1 0 X 1 Reset
1 1 toggle 1 1 X 0
No
change

18. Flip-Flop Applications
 Data Storage
 Data Transfer
 Counter
 Frequency division

19. ANY Questions ?