System View Inc. develops a visual system integration tool called Visual System Integrator (VSI) that allows users to rapidly develop embedded applications that span multiple chips such as CPUs, GPUs, and FPGAs. VSI provides a graphical workflow to describe the hardware platform, develop the application by connecting functional blocks, and automatically generate code for the complete system. It gives unprecedented runtime visibility into transactions for integrated systems with different processors and FPGAs.

1. System View Inc. Confidential
System View Inc.
System View Inc. Confidential
Visual System Integrator

2. System View Inc. Confidential
Problem
Embedded Systems
Getting Increasingly Complex
Designs Span Multiple Chips
(CPUs, GPUs, FPGAs, DSPs ….)
Difficult to Integrate, No Visibility
No Universal Tool Exists
for Integration

3. System View Inc. Confidential
Rapid, visual application development:
• Describe Hardware platform.
• Develop Application
(Import C/C++ blocks connect them)
• Automatic code generation for the
complete system
(Software/Hardware projects, drivers, DMAs)
Solution: Visual System Integrator
Get unprecedented Transaction
level visibility at runtime
Focus on your application, not the platform & firmware!

4. System View Inc. Confidential
Describe
Hardware
Platform
(Import Existing)
Visual System Integrator: Work Flow
Compile
Platform
Platform
Meta data
Software Projects
Eclipse, Qt, VC++ , …
Import
Platform
FPGA
Projects
Develop
Application
System
Compile
Generate
System

5. System View Inc. Confidential
• System Design Phase
• Canvas #1: Define high level platform
• Canvas #2: Connect high level functional blocks
• Implementation Phase
• Develop block details & run functional verification
• Optimize system performance by moving blocks to platform contexts
• SW – intra-block block communication: FIFO (Zero Copy)
• SW-SW shared memory or TCP
• SW-HW timed + driver/DMA
• SW-Simulation timed + BFM
• HW- HW : Aurora
• HW-HW blocks communication (CDC, Arbitration, FIFOs with Backpressure, Width matching)
• System IOs are defined but abstracted as “File I/O” for verification & implementation
• Debug functionality & profile performance with system level trace view
V S I : Design Life Cycle Support

6. System View Inc. Confidential
Applications Supported
Industrial Control
Timer controlled blocks
Accelerator Offload
Compute offloaded to FPGA
High Speed I/O Processing with Software
Network Packet Processing
High Speed Signal Processing

7. System View Inc. Confidential
Videos showing VSI in action
Click on Image
<space> to play
<space> to pause
: https://www.youtube.com/watch?v=39OQ3gSJUFw
Accelerator on Zynq platform
Inline Packet Processing – X86 connected to FPGA (PCI/e)
: https://www.youtube.com/watch?v=9m0GiBvkioE
X86 and Two Virtex-7 FPGAs
: https://www.youtube.com/watch?v=gd7PZYIcFl0

8. System View Inc. Confidential
Performance: PCI/e Data Transfer Rates
0
0.5
1
1.5
2
2.5
3
3.5
0 50 100 150 200 250 300
GBps
PCI/e GEN3 Transfer Rate . X86 <--> FPGA : 1 CDMA
1 Thread(s) 2 Threads(s) 3 Threads(s) 4 Threads(s)
0
0.5
1
1.5
2
2.5
3
3.5
0 50 100 150 200 250 300
GBps
PCI/e GEN3 Transfer Rate . X86 <--> FPGA : 2 CDMA
1 Thread(s) 2 Threads(s) 3 Threads(s) 4 Threads(s)
0
1
2
3
4
5
6
0 50 100 150 200 250 300
GBps
PCI/e GEN3 Transfer Rate . X86 <--> FPGA : 4 CDMA
1 Thread(s) 2 Threads(s) 3 Threads(s) 4 Threads(s)
0
1
2
3
4
5
6
0 50 100 150 200 250 300
GBps
PCI/e GEN3 Transfer Rate . X86 <--> FPGA : 3 CDMA
1 Thread(s) 2 Threads(s) 3 Threads(s) 4 Threads(s)

9. System View Inc. Confidential
Platform
Definition
Technology
Compile
Platform
Platform.plat
Hardware_platform.tclHardware_platform.tcl
System
Definition
Compile
System
System.cxx
Generate
System
Software_context.cxx
Software_System.cxx
Hardware_System.cxxHardware_System.tcl
User
SW Lib*
VSI
runtime
Compiler
(g++)
executables
Vivado
(IPI)
User
IP Lib*
Xilinx
IP Lib
Design/
bitstream
Import platform
* HLS Blocks Included* External
Tools

10. System View Inc. Confidential
System View Inc. Confidential
SW HW Transport
/dev/vsi_...1
/dev/vsi_...2
/dev/vsi_...N
IP..1
IP..2
IP..N
sv_driver
Kernel
Vsi_common_intf
FPGA
Transport
PCIe
AXI (Zynq)
Posix
open
close
read
write
lseek
ioctl
mmap

11. System View Inc. Confidential
SW Simulator Transport
Remote Procedure Call
RPC - FileIO
Vsi - runtime
RPC to DPI ( C )
DPI AXI (BFM)
(System Verilog)
VSI
Generated Design
• Remote Procedure Call (Transport)
• Direct Programming Interface (Simulator Interface)

12. System View Inc. Confidential
• MPSoC Support
• Driver
• Runtime
• Support added for Cortex-R5
• Ported Pthread library to work with FreeRTOS & rpmsg
• Created POSIX compliant “fileio” library for FreeRTOS
FreeRTOS
SW OpenAMP (shared Memory) Transport
RPMSG
Pthread Posix fileio
RPMSG
virtio virtio
RPMSG Driver
Vsi - runtime Vsi - runtime
Linux - StackR5 - Stack
Shared
memory
openAMP
openAMP

13. System View Inc. Confidential
SW TCP/IP Transport
TCP/IP
VSI Runtime
Interconnect
VSI Runtime
Interconnect
o N-depth Chainable
o Provides Automatic Routing for
Trace/Performance Data
o Simple configuration
o Dedicated pipeline for each interface

14. System View Inc. Confidential
FPGA - 2FPGA - 1
HW Serdes (Aurora) Transport
Serdes
Design
Aurora
Design
Aurora
• Tunnel multiple connections over single Aurora link
• Will load balance balance between multiple Aurora Links
• Links shared at a transaction level.

15. System View Inc. Confidential
AXI, S/MM [15]
AXI, S/MM [14]
AXI, S/MM [2]
AXI, S/MM [1]
AXI, S/MM [0]
Hardware Trace Module

16. System View Inc. Confidential
More Information
http://www.systemviewinc.com
info@systemviewinc.com