PPT ON VHDL subprogram,package,alias,use,generate and concurrent statments an...Khushboo Jain
this presentation includes information about - subprograms,packages,use clause, aliases,resolved signals,components,configuration,generate statements,concurrent statments and use of vhdl in simulation and synthesis.
Verilog Tutorial - Verilog HDL Tutorial with ExamplesE2MATRIX
E2MATRIX Research Lab
Opp Phagwara Bus Stand, Backside Axis Bank,
Parmar Complex, Phagwara Punjab (India).
Contact : +91 9041262727
web: www.e2matrix.com -- email: support@e2matrix.com
Simulation tools typically accept full set of Verilog language constructs
Some language constructs and their use in a Verilog description make simulation efficient and are ignored by synthesis tools
Synthesis tools typically accept only a subset of the full Verilog language constructs
In this presentation, Verilog language constructs not supported in Synopsys FPGA Express are in red italics
There are other restrictions not detailed here, see [2].
The Module Concept
Basic design unit
Modules are:
Declared
Instantiated
Modules declarations cannot be nested
PPT ON VHDL subprogram,package,alias,use,generate and concurrent statments an...Khushboo Jain
this presentation includes information about - subprograms,packages,use clause, aliases,resolved signals,components,configuration,generate statements,concurrent statments and use of vhdl in simulation and synthesis.
Verilog Tutorial - Verilog HDL Tutorial with ExamplesE2MATRIX
E2MATRIX Research Lab
Opp Phagwara Bus Stand, Backside Axis Bank,
Parmar Complex, Phagwara Punjab (India).
Contact : +91 9041262727
web: www.e2matrix.com -- email: support@e2matrix.com
Simulation tools typically accept full set of Verilog language constructs
Some language constructs and their use in a Verilog description make simulation efficient and are ignored by synthesis tools
Synthesis tools typically accept only a subset of the full Verilog language constructs
In this presentation, Verilog language constructs not supported in Synopsys FPGA Express are in red italics
There are other restrictions not detailed here, see [2].
The Module Concept
Basic design unit
Modules are:
Declared
Instantiated
Modules declarations cannot be nested
Those slides describe digital design using Verilog HDL,
starting with Design methodologies for any digital circuit then difference between s/w (C/C++) and H/w (Verilog) and the most important constructs that let us start hardware design using Verilog HDL.
This project will provides a detailed explanation about a smart traffic light controller using verilog code along with test bench and the working principle and simulation outputs are been attached.
I2C is a serial protocol for two-wire interface to connect low-speed devices like microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces and other similar peripherals in embedded systems.
The document explains about the concepts of sequential circuits in Digital electronics.
This will be helpful for the beginners in VLSI and electronics students.
This presentation discusses the Serial Communication features in 8051, the support for UART. It also discusses serial vs parallel communication, simplex, duplex and full-duplex modes, MAX232, RS232 standards
Digital signal processing is a specialized microprocessor with its architecture optimized for operational needs of digital signal processing
Application's of DSP like STFT and Wavelet transform has been explained in detail with images.
Those slides describe digital design using Verilog HDL,
starting with Design methodologies for any digital circuit then difference between s/w (C/C++) and H/w (Verilog) and the most important constructs that let us start hardware design using Verilog HDL.
This project will provides a detailed explanation about a smart traffic light controller using verilog code along with test bench and the working principle and simulation outputs are been attached.
I2C is a serial protocol for two-wire interface to connect low-speed devices like microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces and other similar peripherals in embedded systems.
The document explains about the concepts of sequential circuits in Digital electronics.
This will be helpful for the beginners in VLSI and electronics students.
This presentation discusses the Serial Communication features in 8051, the support for UART. It also discusses serial vs parallel communication, simplex, duplex and full-duplex modes, MAX232, RS232 standards
Digital signal processing is a specialized microprocessor with its architecture optimized for operational needs of digital signal processing
Application's of DSP like STFT and Wavelet transform has been explained in detail with images.
Los sistemas en tiempo discretos son sistemas en los cuales una o mas variables toman sus valores en valores del tiempo discreto, el intervalo de tiempo que existe entre dos valores de tiempo discreto es lo suficientemente pequeño como para poder obtener su valor mediante una interpolación.
Modeling more complicated logic using sequential statements
Skills gained:
1- Identify sequential environment in VHDL
2- Model simple sequential logic
This is part of VHDL 360 course
The presentation covers the following topics
The P-Only Algorithm
Controller Gain
Proportional Band
The function of the Proportional Term
The PI Algorithm
A function of the Integral Term
Integral Action Eliminates Offset
Challenges of PI Control
Proportional-Integral-Derivative (PID) controller
The Contribution of the Derivative Term
Understanding Derivative Action
sensor
These terms and definition are quite helpful while studying Instrumentation and Process Control and also in dealing with controllers.
The signal processing algorithms can be implemented on hardware using various strategies such as DSP processors and ASIC. This PPT compares and contrasts the two methods.
Keypad is a common interface with any microcontroller. This presentation gives details of keypad can be interfaced with 8051. The key pressed may be dispalyed on LCD/7 segment/LED displays.
This presentation is all about interfacing of a character LCD with 8051 micro-controller. It discusses various LCD commands, LCD pin description and a simple LCD working code in assembly for interfacing.
This presentation discusses the support for interrupts in 8051. The interrupt types, interrupts versus polling etc are discussed. The register formats of IE, IP register are discussed. The concept of priority among the interrupts is discussed.
This presentation discusses the details of the I2C protocol and interfacing of EEPROM with 8051 based on I2C protocol. It also discusses the other applications of I2C protocol
This presentation is about brief introduction to Timers/Counters in Intel 8051. It discusses the registers involved and modes of programming timers in 8051
This presentation gives the details about the data types available in Embedded C. It also discusses the pros and cons of writing codes in C for 8051. Different example codes are considered.
This presentation discusses the hardware details of 8051 microcontroller, viz. the pin description, reset circuit, port architectures, oscillator circuit and machine cycle etc in 8051
This presentation discusses the internal architecture of Intel 8051. It discusses basic families of 8051, the programmer view, register sets and memory organiszation of 8051
This presentation gives a brief over view of Embedded Systems. It describes the common characteristics of Embedded systems, the design metrics, processor technologies and also summarizes differences between Microcontrollers and Microprocessors.
This presentation discusses the basics about how to realize logic functions using Static CMOS logic. This presentation discusses about how to realize a Boolean expression by drawing a Pull-up network and a pull-down network. It also briefs about the pass transistor logic and the concepts of weak and strong outputs.
Interconnects occupy upto 90% of the area in Reconfigurable Architectures and affect the speed and noise of the chip. This presentations gives briefs about interconnects, particularly in context of Reconfigurable Architecture (eg FPGAs)
This presentation gives an overview of FPGA devices. An FPGA is a device that contains a matrix of re-configurable gate array logic circuitry. When a FPGA is configured, the internal circuitry is connected in a way that creates a hardware implementation of the software application.
FPGA devices can deliver the performance and reliability of dedicated hardware circuitry.
Design and Implementation of a GPS based Personal Tracking SystemSudhanshu Janwadkar
Design and Implementation of a GPS based Personal Tracking System
Tracking based applications have been quite popular in recent times. Most of them have been limited to commercial applications such as vehicular tracking (e.g tracking of a train etc). However, not much work has been done towards design of a personal tracking system. Our Research work is an attempt to design such personal tracking system. In this paper, we have shared glimpses of our research work.
The objective of our research project is to design & develop a system which is capable of tracking and monitoring a person, object or any other asset of importance (called as target). The system uses GPS to determine the exact position of the target. The target is aided with a compact handheld device which consists of a GPS receiver and GSM modem. GPS receiver obtains location coordinates (viz. Latitude & Longitude) from GPS satellites. The location information in NMEA format is decoded, formatted and sent to control station, through a GSM modem. Due to use of Open CPU development platform, no external Microcontroller is required, with additional advantage of compact size product, reduced design & development time and reduced cost.
Thus, the proposed system is able to track the accurate location of target. This system finds applications in tracking old-age people, tracking animals in forest, tracking delivery of goods etc. Our final designed system is a small-size compact l.S"X3.7S" Tracker system with position accuracy error <30m (100 feet).
With advancement in CMOS technology, a lot of research has been done to develop various logic styles to improve the performance of logic circuits. D flip-flops (DFF) are fundamental building blocks in almost every sequential logic circuit. Hence, in sequential logic circuits, the overall performance of the circuit is affected by the performance of constituent DFFs. In recent years, the focus has been towards incorporating higher clock rates in a processor for better performance. To achieve high clock rates, fine granularity pipelining techniques are used, which implies that there are relatively a fewer levels of logic in each pipeline stage. A major consequence of this design trend is that the pipeline overhead has becoming more significant. The primary cause of pipeline overhead is the latency of the flip-flop or latch used to design the processor and the clock skew of the system. This calls out for the need of incorporating the logic functionality within the architecture of flip-flop. The new family of flip-flops are called Embedded Logic Flip Flops. In this Paper, we have reviewed various Flip-flop architectures which have been proposed so far. Our attempt is to do a qualitative analysis and comparison of the proposed Embedded logic flip-flop designs.
This presentation discusses the basics of Pass Transistor Logic, its advantages, limitation and finally implementation of Boolean functions/Combinational Logic circuits using Pass Transistor Logic.
Unit 8 - Information and Communication Technology (Paper I).pdfThiyagu K
This slides describes the basic concepts of ICT, basics of Email, Emerging Technology and Digital Initiatives in Education. This presentations aligns with the UGC Paper I syllabus.
Francesca Gottschalk - How can education support child empowerment.pptxEduSkills OECD
Francesca Gottschalk from the OECD’s Centre for Educational Research and Innovation presents at the Ask an Expert Webinar: How can education support child empowerment?
2024.06.01 Introducing a competency framework for languag learning materials ...Sandy Millin
http://sandymillin.wordpress.com/iateflwebinar2024
Published classroom materials form the basis of syllabuses, drive teacher professional development, and have a potentially huge influence on learners, teachers and education systems. All teachers also create their own materials, whether a few sentences on a blackboard, a highly-structured fully-realised online course, or anything in between. Despite this, the knowledge and skills needed to create effective language learning materials are rarely part of teacher training, and are mostly learnt by trial and error.
Knowledge and skills frameworks, generally called competency frameworks, for ELT teachers, trainers and managers have existed for a few years now. However, until I created one for my MA dissertation, there wasn’t one drawing together what we need to know and do to be able to effectively produce language learning materials.
This webinar will introduce you to my framework, highlighting the key competencies I identified from my research. It will also show how anybody involved in language teaching (any language, not just English!), teacher training, managing schools or developing language learning materials can benefit from using the framework.
Normal Labour/ Stages of Labour/ Mechanism of LabourWasim Ak
Normal labor is also termed spontaneous labor, defined as the natural physiological process through which the fetus, placenta, and membranes are expelled from the uterus through the birth canal at term (37 to 42 weeks
Embracing GenAI - A Strategic ImperativePeter Windle
Artificial Intelligence (AI) technologies such as Generative AI, Image Generators and Large Language Models have had a dramatic impact on teaching, learning and assessment over the past 18 months. The most immediate threat AI posed was to Academic Integrity with Higher Education Institutes (HEIs) focusing their efforts on combating the use of GenAI in assessment. Guidelines were developed for staff and students, policies put in place too. Innovative educators have forged paths in the use of Generative AI for teaching, learning and assessments leading to pockets of transformation springing up across HEIs, often with little or no top-down guidance, support or direction.
This Gasta posits a strategic approach to integrating AI into HEIs to prepare staff, students and the curriculum for an evolving world and workplace. We will highlight the advantages of working with these technologies beyond the realm of teaching, learning and assessment by considering prompt engineering skills, industry impact, curriculum changes, and the need for staff upskilling. In contrast, not engaging strategically with Generative AI poses risks, including falling behind peers, missed opportunities and failing to ensure our graduates remain employable. The rapid evolution of AI technologies necessitates a proactive and strategic approach if we are to remain relevant.
Operation “Blue Star” is the only event in the history of Independent India where the state went into war with its own people. Even after about 40 years it is not clear if it was culmination of states anger over people of the region, a political game of power or start of dictatorial chapter in the democratic setup.
The people of Punjab felt alienated from main stream due to denial of their just demands during a long democratic struggle since independence. As it happen all over the word, it led to militant struggle with great loss of lives of military, police and civilian personnel. Killing of Indira Gandhi and massacre of innocent Sikhs in Delhi and other India cities was also associated with this movement.
Introduction to AI for Nonprofits with Tapp NetworkTechSoup
Dive into the world of AI! Experts Jon Hill and Tareq Monaur will guide you through AI's role in enhancing nonprofit websites and basic marketing strategies, making it easy to understand and apply.
2. Features of Behavioural Description
The behavioral description describes the system by
showing how the outputs behave according to changes in
the inputs.
In this description, we need not know the logic diagram
of the system or its components, what must be known is
how the outputs behaves in response to changes in input
In VHDL, the major behavioral description statement is
'process'. The statements inside the process statement
are sequential, however process statement itself is
concurrent.
3. Process statement
A process statement contains sequential statements that describe
the functionality of a portion of an entity in sequential terms
Syntax:
[ process-label: ] process [ ( sensitivity-list ) ]
[process-item-declarations]
begin
.
.
sequential-statements;
.
.
.
end process [ process-label];
variable-assignment-statement,
signal-assignment-statement,
wait-statement,
if-statement,
case-statement,
loop-statement,
null-statement,
exit-statement,
next-statement,
assertion-statement,
procedure-call-statement,
return-statement.
4. Process Statement
A set of signals that the process is sensitive to is defined
by the sensitivity list. In other words, each time an
event occurs on any of the signals in the sensitivity list,
the sequential statements within the process are
executed in a sequential order, that is, in the order in
which they appear.
The process then suspends after executing the last
sequential statement and waits for another event to
occur on a signal in the sensitivity list.
Items declared in the item declarations part are
available for use only within the process.
5. Process Statement
Summarising,
A process is activated when a signal in the
sensitivity list changes its value
Its statements will be executed sequentially
until the end of the process
6. Process Statement
Example:
P1: process(a,b,c)
begin
y1 <= a and b and c;
y2 <= a or b;
end process;
The process statement has a label P1(optional) and its sensitivity list has signals
a, b and c. As soon as there is an event on a, b or c, the process statement will be
executed. It must be noted that the two signal assignment statements inside
process will be executed sequentially.
7. Process Statement
For a combinational circuit, it is advisable that the all
inputs should be included in the sensitivity list.
Example:
P1: process(a)
begin
y1 <= a and b and c;
y2 <= a or b;
end process;
The process statement will be executed only when there is an event on Signal a. The
events on signals b and c will not be captured.
8. Process Statement
Write a VHDL process statement which counts the number of
transitions on a signal.
process (A)
variable count: INTEGER := 0;
begin
count := count+1;
end process;
This example is to count number of signal transition on signal ‘A’. At start of
simulation, the process is executed once. The variable count gets initialized
to 0 and then incremented by 1. After that, each time an event occurs on
signal A, the process is activated and the single variable assignment
statement is executed and the value of count is incremented.
Note the position of the
Variable declaration
statement.
Any variable that is created
in one process cannot be
used in another process
10. How are sequential statements
executed inside a Process statement?
All statements inside the body of the process are
executed sequentially
The execution of a signal-assignment statement has
two phases: calculation and assignment.
Sequential execution, here, refers to sequential
calculation
i. e The calculation of a subsequent statement will
not wait until the preceding statement is assigned, it
will wait only till the calculation of preceding
statement is completed.
11. How are sequential statements
executed inside a Process statement?
Example:
process (I1,I2)
begin
O1 <= I1 xor I2 after 10ns; -- Statement 1
O2 <= I1 and I2 after 10ns; -- Statement 2
end process;
To understand sequential execution, assume that at T = T0, I1 changes
from 0 to 1, while I2 stays at 1. This change constitutes an event on I1 and
it activates the process. Statement 1 is calculated as O1 =(I1 xor I2) = ( 1
xor 1)=0. This new value 0 is not assigned to O1 at T0, but rather at T0
+10ns. However, as soon as calculation of O1 = (I1 xor I2) is completed, at
same time instant T0, statement 2 is calculated by using values of I1 and
I2 at T0, so that O2 = (1 and 1) = 1. The value of 0 is assigned to O2 at T0
+ 10ns
13. How are sequential statements
executed inside a Process statement?
For the above example, both data-flow and
behavioural description result in the same output
for the signal assignments
Is this always true? No
This is not true when a signal appears on the right
side of a signal assignment statement and left side
of another signal assignment.
We prefer to use variable assignment statements
inside the process statement. -> Why?
14. Variable Assignment Statement
Variables can be declared and used inside a process statement.
Syntax for variable declaration:
variable [variable_Identifier] : [type] := [optional_initial_value]
Example: variable count : integer := 0;
Syntax for variable assignment:
variable-object := expression;
Example: Count := count + 1;
The expression is evaluated when the statement is executed and
the computed value is assigned to the variable object
instantaneously, that is, at the current simulation time
15. Signals versus Variable
-Differences in Syntax
Variables need to be defined after the keyword process but
before the keyword begin. Signals are defined in the
architecture before the begin statement.
Variables are assigned using the := assignment symbol.
Signals are assigned using the <= assignment symbol.
Variables can only be used inside processes, signals can be
used inside or outside processes.
Any variable that is created in one process cannot be used
in another process, signals can be used in multiple
processes though they can only be assigned in a single
process.
16. Why are variable assignments suited
inside process statement?
All statements inside the process statement are executed
sequentially.
To understand the trouble of using signal assignments inside
process statement, consider this example:
...
signal x,y,z : bit;
...
process (y)
begin
x<=y; -- st1
z<=not x; --st2
end process;
If the signal y changes then an event will be
scheduled on x to make it the same as y. Also, an
event is scheduled on z to make it the opposite of x.
It is now expected that the value of z must be
opposite to that of y.
The question is, will the value of z be the opposite of
y? NO!!
17. Why are variable assignments suited
inside process statement?
...
signal x,y,z : bit;
...
process (y)
begin
x<=y; -- st1
z<=not x; --st2
end process;
• If there is an event on y at T0, the value of x is
calculated as x=y at T0, but the value is assigned to
X at T0 + D.
• Next, at T0 itself, next statement is executed. At
this moment, x is not yet updated. This results in
calculation of z with previous value of x itself.
• Thus at T0+ D, the value of Z will be same as that
of y, instead being opposite of y.
19. Why are variable assignments suited
inside process statement?
Next, consider the example using variable assignment:
Example:
…
process (y)
variable x, z : bit;
begin
x:=y;
z:=not x;
end process;
........
The value of the variable z would be the opposite of
the value of y because the value of the variable x is
changed immediately.
21. Concurrent v/s sequential signal
assignment
Signal assignment statements which occur in the body
of a process statements are sequential signal
assignment statements,
while
Signal assignment statements that appear outside the
process are concurrent signal assignment statements.
1
22. Concurrent v/s sequential signal
assignment
Concurrent signal assignment statements are event-
triggered, that is they are executed whenever there is
an event on a signal that appears in its expression,
while
Sequential signal assignment statements are not event
triggered and are executed in sequence in relation to
other sequential statements that appear within the
process.
2
23. Concurrent v/s sequential signal
assignment
y1 <= not a; -- st1
y2 <= not b; -- st2
p1: process(b)
y1 <= not a; -- st1
y2 <= not b; -- st2
end process p1;
At time instant T1, lets say signal a undergoes a 0-> 1 transition, while b retains its value.
At some other time instant T2 (T2> T1), signal b undergoes 0->1 transition and signal a
undergoes 1-> 0 transition
How is this executed by Concurrent and sequential statements?
Example:
Concurrent Sequential I Sequential II
p1: process(a)
y1 <= not a; -- st1
y2 <= not b; -- st2
end process p1;
24. Concurrent v/s sequential signal
assignment
Concurrent Execution
At time instant T1, all
signal assignment
statements which have
signal a as their driver
will be executed
concurrently. No other
signal assignment
takes place.
25. Concurrent v/s sequential signal
assignment
Sequential Execution-I
In sequential
statements, whenever
there is an event on
sensitivity list, all the
statements in the
process are executed,
irrespective of the
events on their drivers.
29. Sequential Statements in VHDL
Wait statement- wait on, wait for, wait until
If statement – if, if-else, if-elsif-else
Case statement
Loop statement – for, while
Null statement
Exit statement
Next statement
Assert & report statement
Procedure and Return statement
30. Wait Statement
There are three basic forms of the wait statement:
wait on sensitivity-list;
wait until boolean-expression ;
wait for time-expression ;
31. Wait Statement
wait on (sensitivity-list) statement
The wait on statement suspends the execution of a process
till an event on the sensitivity list occurs.
Example:
wait on a, b, c;
In above statement, the execution of the wait statement
causes the process to suspend and then it waits for an
event to occur on signals a, b, or c. Once that happens, the
process resumes execution from the next statement
onwards.
32. Wait Statement
wait until (boolean_expression) statement
The wait until statement suspends the execution of a process
until the boolean express evaluates to be true.
Example:
wait until a= b;
In above statement, the process is suspended until the
specified condition becomes true. When an event occurs
on signal a or b, the condition a= b is evaluated and if it is
true, the process resumes execution from the next
statement onwards, otherwise, it suspends again
33. Wait Statement
wait for (time expression) statement
The wait until statement suspends the execution of a
process until the boolean express evaluates to be true.
Example:
wait for 10ns;
When the wait statement is executed, say at time T, the
process suspends for 10 ns and when simulation time
advances to T+10 ns, the process resumes execution
from the statement following the wait statement
34. Write a VHDL behavioural code to generate a
clock signal of period 20ns using wait statement
Note that it is
legitimate to use
signal inside the
process in this
example, as the
signal clock
appears only on
one side of the
signal assignment
statement
Also, note
that a
process
cannot have
both
sensitivity
list and wait
statement.
35. Write a VHDL behavioural code to generate a
clock signal of period 20ns using wait statement
• Using variable
assignment
statements.
• Note the
changes in
syntax
36. What if a process doesn’t have a
sensitivity list?
It is possible for a process not to have an explicit
sensitivity list. In such a case, the process may have one
or more wait statements.
It must have at least one wait statement, otherwise, the
process will never get suspended and would remain in
an infinite loop during the initialization phase of
simulation.
It is an error if both the sensitivity list and a wait
statement are present within a process.
The presence of a sensitivity list in a process implies the
presence of an implicit "wait on sensitivity-list"
statement as the last statement in the process.
37. Write the below process statement without
using sensitivity list
38. If statement
An if statement selects a sequence of statements for execution based on
the value of a condition. The condition can be any expression that
evaluates to a boolean value.
Syntax:
if boolean-expression then
--sequential-statements
elsif boolean-expression then
--sequential-statements
-- elsif clause; if stmt can have 0 or more elsif clauses
else
-- else clause.
-- sequential-statements
end if;
39. If statement
Semantics:
The if statement is executed by checking each
condition sequentially until the first true condition is
found; then, the set of sequential statements
associated with this condition is executed. The default
action is listed under else clause.
The if statement can have zero or more elsif clauses
and an optional else clause.
if statement is a sequential statement
nesting of if statements is allowed
41. case statement
case statement selects one of the branches for execution
based on the value of the expression.
The expression value must be of a discrete type or of a
one-dimensional array type.
Choices may be expressed as single values, as a range of
values, by using I (vertical bar: represents an "or"), or by
using the others clause.
All possible values of the expression must be covered in
the case statement. “
The others clause can be used as a choice to cover the
"catch-all" values and, if present, must be the last branch in
the case statement.
42. case statement
Syntax:
case expression is
when choices => sequential-statements -- branch #1
when choices => sequential-statements -- branch #2
-- Can have any number of branches.
[ when others => sequential-statements ] -- last branch
end case;
44. Null statement
The statement
null;
is a sequential statement that does not cause any
action to take place and execution continues
with the next statement.
47. Example: Leading Zeros
Refer Class notes for meaning of
code and alternate approach
If loop runs from 8
to 0, one can find
number of trailing
zeros
Instead of exit, if
next is used, it can
be used to find total
number of 0’s. This
can also be used to
check parity.
48. Example: Parity Detector
Refer Class notes for meaning of
code and alternate approach
How will you find
both odd parity
and even parity
from same code?
49. Example – 4-bit Ripple Carry Adder
This code is easy to understand, but is not very efficient when
comes to hardware implementation. Alternate versions of code
are available online. Can you try?
50. Example: Factorial of Positive Integers
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity factorial is
port(N : in natural; z : out natural); -- consider positive integers only
end factorial;
architecture behavioral of factorial is
begin
process (N)
variable y, i : natural;
begin
y := 1;
i := 0;
while (i < N) loop
i := i + 1;
y := y * i;
end loop;
z <= y;
end process;
end factorial;
Run the code in Xilinx and find the RTL
description of this circuit