digital system design using verilog Module 5 ppt.pptx

Module – v
Verilog Behavioral description

Syllabus:
Verilog Behavioral description: Structure, Variable Assignment Statement, Sequential
Statements, Loop Statements, Verilog Behavioral Description of Multiplexers (2:1, 4:1,
8:1). (Section 3.1 to 3.4 (only Verilog) of Text 3) Verilog Structural description:
Highlights of Structural description, Organization of structural description, Structural
description of ripple carry adder. (Section 4.1 to 4.2 of Text 3)
Text Book: HDL Programming VHDL and Verilog by Nazeih M Botros, 2009 reprint,
Dreamtech press

• Data-flow simulations were implemented to describe digital
systems with known digital structures such as adders,
multiplexers, and latches.
• The behavioral description is a powerful tool to describe systems
for which digital logic structures are not known or are hard to
generate.
• Examples of such systems are complex arithmetic units, computer
control units, and biological mechanisms that describe the
physiological action of certain organs such as the kidney or heart
Behavioral Description Highlights

• The behavioral description describes the system by
showing how outputs behave with the changes in inputs
• In this description, details of the logic diagram of the
system are not needed; what is needed is how the output
behaves in response to a change in the input.
• In VHDL, the major behavioral-description statement is
process.
• In Verilog, the major behavioral-description statements are
always and initial
Behavioral Description Facts

Listing 5.1 shows a simple example of HDL code describing a
system (half_add) using behavioral description.
Usually sequential statements such as IF or Case are used to
describe the change of the output; however, in this section,
Boolean functions are used to describe the change.
This is done here to explain how the HDL executes signal-
assignment statements written inside process (VHDL) or inside
always or initial (Verilog).
The code in Listing 5.1 mainly consists of signal-assignment
statements.
Structure of the HDL Behavioral Description

Referring to the VHDL code, the entity half_add has two input
ports, I1 and I2, and two output ports, O1 and O2.
The ports are of type bit; this type is recognized by the VHDL
package without the need to attach a library.
If the type is std_logic, for example, the IEEE library must be
attached.
The name of the architecture is behave_ex; it is bound to the
entity half_add by the predefined word of. Process is the
VHDL behavioral- description keyword.
.

Every VHDL behavioral description has to include a process.
The statement process (I1, I2) is a concurrent statement, so
its execution is determined by the occurrence of an event.
I1 and I2 constitute a sensitivity list of the process.
The process is executed (activated) only if an event occurs on
any element of the sensitivity list; otherwise, the process
remains inactive.
If the process has no sensitivity list, the process is executed
continuously. The process in Listing 5.1 includes two signal-
assignment statements: statement 1 and statement 2.

All statements inside the body of a process are executed
sequentially.
The execution of a signal-assignment statement has two
phases: calculation and assignment.
The sequential execution here means sequential calculation,
which means the calculation of a statement will not wait
until the preceding statement is assigned;
it will only wait until the calculation is done.

at T = T0, I1 changes from 0 to 1, while I2 stays at 1. This
change constitutes an event on I1, which in turn activates the
process. Statement 1 is calculated as O1 = (I1 XOR I2) = (1
XOR 0) =1.
Then, the value of O2 is calculated, still at T0, as (I1 and I2)= (1
and 0)= 0.
After calculation, the value of 1 is assigned to O1 after the
delay of 10 ns at T0 +10 ns; the value of 0 is assigned to O2
after the delay of 10ns at T0 + 10ns.

For the above example, both data-flow and behavioral
descriptions yield the same output for the two signal-
assignment statements.
This is not the case when a signal appears on both the right-
hand side of the statement and the left-hand side of another
statement, which will be seen later
.

Calculate: O1 (1 xor 0) = 1, assign 1 to O1 after 10 ns
Calculate: O2 (1 and 0) = 0, assign 0 to O2 after 10 ns
In contrast to VHDL, all Verilog statements inside always are
treated as concurrent, the same as in the data-flow
description.
Also, here any signal that is declared as an output or appears
at the left-hand side of a signal-assignment statement should
be declared as a register (reg) if it appears inside always. In
Listing 5.1, O1 and O2 are declared outputs, so they should
also be declared as reg.

Execution of signal-assignment statements inside always
(Verilog).
Calculate: O1 (1 xor 0) = 1, assign 1 to O1 after 10 ns
Calculate: O2 (1 and 0) = 0, assign 0 to O2 after 10 n
Execution of signal-assignment statements
Event on I1
activates
ALWAYS
I1
I2
10 ns
1
2

Verilog Description
module half_add (I1, I2, O1, O2);
input I1, I2;
output O1, O2;
reg O1, O2;
/* Since O1 and O2 are outputs and they are written inside “always,”
they should be declared as reg */
always @(I1, I2)
begin
#10 O1 = I1 ^ I2; // statement 1.
#10 O2 = I1 & I2; // statement 2
/*The above two statements are signal-assignment statements with 10 simulation
screen units delay*/
/*Other behavioral (sequential) statements can be added here*/
end
endmodule
Execution of signal-assignment statements

The use of variables inside processes is a common practice in VHDL
behavioral description.
Consider the following two signal-assignment statements inside a
process, where S1, S2, and t1 are signals:
Signl : process(t1) begin
st1 : S1 <= t1;
st2 : S2 <= not S1; end process;
The VHDL Variable-Assignment Statement

variable-assignment statements can be used instead of the above
signal- assignment statement as follows:
Varb : process(t1)
variable temp1, temp2 : bit; -- This is a variable
-- declaration statement
begin
st3 : temp1 := t1; -- This is a variable assignment
-- statement
st4 : temp2 := not temp1; -- This is a variable
-- assignment statement
st5 : S1 <= temp1;
st6 : S2 <= temp2;
end process;
Variable-Assignment Statement

Signl: process(t1) begin
st1: S1 <= t1;
st2: S2 <= not S1;
end process
Varb: process(t1)
variable temp1, temp2: bit; begin
st3: temp1: = t1;
st4: temp2: = not temp1; st5: S1 <= temp1;
st6: S2 <= temp2; end process;
cont…

• Variable-assignment statements, as in C language, are calculated
and assigned immediately with no delay time between calculation
and assignment.
• The assignment operator is :=. If t1 acquires a new value of 1 at T1,
then momentarily temp1 = 1 and temp2 = 0.
• For statements st5 and st6, S1 acquires the value of temp1 (1) at
T1 + D, and S2 acquires the value of temp2 (0) at T1 + D.
• Because D is infinitesimally small, S1 and S2 appear on the
simulation screen as if they acquire their new values at T1
Assignment operator

For statements st5 and st6, S1 acquires the value of temp1 (1) at T1
+ D, and S2 acquires the value of temp2 (0) at T1 + D. Because D is
infinitesimally small, S1 and S2 appear on the simulation screen as if
they acquire their new values at T1
Signal versus variable in VHDL

IF Statement
IF is a sequential statement that appears inside process in VHDL or
inside always or initial in Verilog. It has several formats, some of which
are as follows
Verilog IF-Else Formats if (Boolean Expression) begin
statement 1; /* if only one statement, begin and end
can be omitted */
statement 2;
statement 3;
.......
end
else begin
statement a; /* if only one statement, begin and end
can be omitted */
statement b; statement c;
.......
End
Sequential Statements

Execution of IF as ELSE-IF
Verilog
if (Boolean Expression1)
begin
statement1; statement 2;.....
end
else if (Boolean expression2)
begin
statementi; statementii;.....
end
else
begin
statementa; statement b;....
end
Execution of IF as ELSE-IF

Implementing ELSE-IF
if (signal1 == 1’b1)
temp = s1;
else if (signal2 == 1’b1)
temp = s2;
else
temp = s3;
Implementing ELSE-IF

Verilog Code for Behavioral Description of a D-Latch
module D_latch (d, E, Q, Qb);
input d, E;
output Q, Qb;
reg Q, Qb;
always @ (d, E) begin if (E == 1) begin Q = d;
Qb = ~ Q;
end
end
endmod
D-Latch

Verilog Description of a 2x1 Multiplexer Using IF-Else
module mux2x1 (A, B, SEL, Gbar, Y); input A, B, SEL, Gbar;
output Y; reg Y;
always @ (SEL, A, B, Gbar) begin
if (Gbar == 1) Y = 1’bz;
else begin
if (SEL)
Y = B;
else
Y = A;
End;
End;
endmodule
2x1 Multiplexer Using IF-Else

The case statement is a sequential control statement. It has the
following format:
Verilog Case Format
case (control-expression)
test value1 :
begin statements1;
end test value2 :
begin statements2;
end
test value3 :
begin statements3;
end default :
begin default statements
end
endcase
The case Statement

If, for example, test value1 is true (i.e., it is equal to the value of the
control expression), statements1 is executed.
The case statement must include all possible conditions (values) of the
control-expression.
The statement when others (VHDL) or default (Verilog) can be used to
guarantee that all conditions are covered.
The case resembles IF except the correct condition in case is
determined directly, not serially as in IF statements. The begin and end
are not needed in Verilog if only a single statement is specified for a
certain test value.
The case statement can be used to describe data listed into tables
The case Statement

module JK_FF (JK, clk, q, qb);
input [1:0] JK;
input clk;
output q, qb;
reg q, qb;
always @ (posedge clk)
begin
case (JK)
2’d0 : q = q;
2’d1 : q = 0;
2’d2 : q = 1;
2’d3 : q =~ q;
endcase
qb =~ q;
end
endmodule
Positive Edge-Triggered JK Flip-Flop Using the case
Statement

module waitstatement(a,b,c);
output a,b,c;
reg a,b,c;
initial begin
// Initialize Inputs a = 0;
b = 0;
c = 0;
end
always
begin
#10 ;
a = ~ a;
end
always
begin
#20 ;
b = ~ b;
end
always
begin
#40 ;
c = ~ c;
end
endmodule
The wait-for Statement

Loop is a sequential statement that has to appear inside process in
VHDL or inside always or initial in Verilog. Loop is used to repeat the
execution of statements written inside its body.
The number of repetitions is controlled by the range of an index
parameter.
The loop allows the code to be compressed; instead of writing a block of
code as individual statements, it can be written as one general statement
that, if repeated, reproduces all statements in the block.
There are several ways to construct a loop.
The wait-for Statement

Verilog For-Loop
for (i = 0; i <= 2; i = i + 1)
begin
if (temp[i] == 1’b1) begin
result = result + 2**i;
end
end
statement1; statement2; ....
The Loop Statement

Verilog While-Loop
while (i < x)
begin
i = i + 1;
z = i * z;
end
In the above example, the condition is (i < x). As long as i is less than x, i is
incremented, and the product i * z (i multiplied by z) is calculated and
assigned to z.
While-Loop

Verilog repeat
In Verilog, the sequential statement repeat causes the execution of
statements between its begin and end to be repeated a fixed number of
times; no condition is allowed in repeat.
repeat (32) begin
#100 i = i + 1;
end
In the above example, i is incremented 32 times with a delay of 100
screen time units. This describes a five-bit binary counter with a clock pe-
riod of 100 screen time units.
Verilog repeat

Verilog forever
The statement forever in Verilog repeats the loop endlessly. One common
use for forever is to generate clocks in code-oriented test benches. The
following code describes a clock with a period of 20 screen time units:
initial begin
Clk = 1’b0;
forever #20 clk = ~clk;
Verilog forever

module countr_direct (clk, Z); input clk;
output [3:0] Z;
reg [3:0] Z; initial
Z = 4’b0000;
/*This initialization is needed if we want to start counting from 0000*/
always @ (posedge clk) Z = Z + 1;
endmodule
Verilog code describes a four-bit binary counter

module mux2x1 (A, B, SEL, Gbar, Y);
input A, B, SEL, Gbar;
output Y;
reg Y;
always @ (SEL, A, B, Gbar)
begin
if (Gbar == 1) Y = 1’bz;
else
begin
if
(SEL) Y = B;
else
Y = A;
end
end
endmodule
2x1 Multiplexer Using IF-Else

module MUXBH (A, B, SEL, Gbar, Y);
input A, B, SEL, Gbar;
output Y;
reg Y; /* since Y is an output and appears inside always, Y has to be declared
as reg( register) */
always @ (SEL, A, B, Gbar)
begin
if (Gbar == 0 & SEL == 1)
begin
Y = B;
end
else if (Gbar == 0 & SEL == 0)
Y = A;
else
Y = 1’bz; //Y is assigned to high impedance
End
endmodule
2x1 Multiplexer Using Else-IF

• Structural description simulates the system by describing its logical
components. The components can be gate level (such as AND gates, OR
gates, or NOT gates), or components can be in a higher logical level, such
as register-transfer level (RTL) or processor level.
• It is more convenient to use structural description than behavioral
description for systems that require specific design constraints. Con-
sider, for example, a system performing the operation A + B = C. In
behavioral description, the addition can be written as C = A + B with no
choice in selecting the type of adders used to perform this addition. In
structural description, the type of adder, such as look-ahead adders, can
be selected.
• All statements in structural description are concurrent. At any simulation
time, all statements that have an event are executed concurrently.
Highlights of Structural Description

• A major difference between VHDL and Verilog structural description is the
availability of components (especially primitive gates) to the user.
• Verilog recognizes all the primitive gates such as AND, OR, XOR, NOT, and
XNOR gates. Basic VHDL packages do not recognize any gates un- less the
package is linked to one or more libraries, packages, or modules that have
the gate description. Usually, the user develops these links, as will be done
in this chapter.
• Although structural description is implemented in this chapter to simulate
digital systems, this does not mean that only one type of description
(structural) can be used in a module. In fact, in most descriptions of
complex systems, mixed-type descriptions (e.g., data flow, behavioral,
structural, or switch-level) are used in the same module
•
Highlights of Structural Description

HDL code that describes a half adder under the name of system using
structural description. The entity (VHDL) or module (Verilog) name is system;
there are two inputs, a and b, and two outputs, sum and cout.
The entity or module declaration is the same as in other description styles
previously covered (data flow and behavioral).
In the VHDL description, the structural code (inside the architecture) has two
parts: declaration and instantiation.
In declaration, all of the different types of components are declared. For
example, the statements
Organization of Structural Description

component xor2
port (I1, I2 : in std_logic; O1 : out std_logic); end component;
• Declare a generic component by the name of xor2; the component has
two inputs (I1, I2) and one output (O1). The name (identifier) xor2 is not a
reserved or predefined word in VHDL; it is a user-selected name.
• To specify the type of the component (e.g., AND, OR, XOR, etc.), additional
information should be given. If the system has two or more identical
components, only one declaration is needed.
• The instantiation part of the code maps the generic inputs/outputs to the
actual inputs/outputs of the system. For example, the statement

X1 : xor2 port map (a, b, sum);
maps input a to input I1 of xor2, input b to input I2 of xor2, and output sum
to output O1 of xor2.
This mapping means that the logic relationship between a, b, and sum is the
same as between I1, I2, and O1.
If xor2 is specified through additional statements to be a XOR gate, for
example, then sum = a xor b.
A particular order of mapping can be specified as:

X1 : xor2 port map (O1 => S, I1 => b , I2 => a);
S is mapped to O1, b is mapped to I1, and a is mapped to I2.
Note that the mapping of S is written before writing the mapping of the
inputs; we could have used any other order of mapping.
As previously mentioned, structural- description statements are concurrent
and are driven by events.
This means that their execution depends on events, not on the order in which
the statements are placed in the module.
So, placing statement A1 before statement X1 does not change the outcome
of the VHDL program

Verilog has a large number of built-in gates. For example, the statement:
xor X1 (sum, a, b);
describes a two-input XOR gate.
The inputs are a and b, and the output is sum. X1 is an optional identifier for
the gate; the identifier can be omitted as:
xor (sum, a, b);
outputs, sum and cout.
The entity or module declaration is the same as in other description styles
previously covered (data flow and behavioral).
Verilog has a complete list of built-in primitive gates

Verilog Description
module system (a, b, sum, cout); input a, b;
output sum, cout; xor X1 (sum, a, b);
/* X1 is an optional identifier; it can be omitted.*/
and a1 (cout, a, b);
/* a1 is optional identifier; it can be omitted.*/
Endmodule

• A Ripple Carry Adder is made of a number of full-adders cascaded
together. It is used to add together two binary numbers using only
simple logic gates.
• The figure below shows 4 full-adders connected together to produce a 4-
bit ripple carry adder.
Ripple Carry Adder

Verilog code for 4-bit ripple-carry adder
module rippe_adder(X, Y, S, Co);
input [3:0] X, Y;// Two 4-bit inputs
output [3:0] S;
output Co;
wire w1, w2, w3;
// instantiating 4 1-bit full adders in Verilog
fulladder u1(X[0], Y[0], 1'b0, S[0], w1);
fulladder u2(X[1], Y[1], w1, S[1], w2);
fulladder u3(X[2], Y[2], w2, S[2], w3);
fulladder u4(X[3], Y[3], w3, S[3], Co);
endmodule
Ripple Carry Adder code

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