SlideShare a Scribd company logo
MICROPROCESOR ARCHITECTURE-2
Register Organization
• The 8085 microprocessor has various types of registers as shown
below.
• It includes six , 8 – bit registers (B, C, D. E, H and L), one 8-bit
Accumulator ,One Flag register and two 16-bit registers (SP and PC).
• Also there are two 8-bit temporary registers
W and Z.
• These registers W and Z are not
accessible to the user, They are used by the
processor for internal, intermediate operations.
• These registers B, C, D. E, H and L are known
• as general purpose registers.
contd
• The registers Program Counter and Stack Pointer are known as the
speci purpose Registers.
• So, the total registers are classified into three groups .They are
(i).Temporary registers. (W and Z )
(ii).General purpose registers (B, C, D. E, H and L)
(iii).Special purpose registers. (SP and PC).
• The special purpose registers PC and SP are 16 bit registers.
• As you know 8085 is a 8-bit processor with 16 bit-address bus.So, the
address of the memory location is always16-bit .
• But a very interesting thing is there are no 16-bit general purpose
registers to hold the address of the memory location.
contd
• To overcome this limitation, Intel has provided the feature of Register
pairing.
• That is two 8-bitregisters are paired so that they can store a 16-bt
address.
• The admissible register pairs are B-C; D-E and H-L only. No other
pairs are allowed.
• These pair of register are mainly used only during the times of
address accessing .
• At all the other times they are only 8-bit data registers (B,C,D,E,H and
L).
• Let us see this with an example.
• LXI H 8509 ; It means, load immediately the register pair H-L with
the address 8509.
contd
• Here L-register is loaded with 09 and H-register is loaded with
address 85H. Here H indicates that the address is Hexadecimal.
• It is a three byte instruction.(Hex code = 21, 09, 85 (Three bytes)
21 = 0010 0001 8-bits = 1 byte
09 = 0000 1001 8-bits = 1 byte
85 = 1000 0110 8-bits = 1 byte
Total 3-bytes
Program Counter (PC)
• It is a 16-bit special purpose register, which stores the address of the
next instruction to be fetched or executed.
• The execution of a program is initiated by loading the PC by the address
of the first instruction of the program.
• Once the first instruction is executed, the PC is automatically
incremented to point to the next instruction unless a jump to some
specific address occurs.
• This process is repeated till the last instruction of the program is
executed.
•
contd
• Here the diagram shows the Operation of PC.
contd
• In case of JUMP or CALL instructions, current address is stored in the
Program Counter.
• The processor then fetches
the next instruction from the
new address specified by the
JUMP or CALL instruction.
Address HEX –
CODE
LABEL MNEMONIC COMMENTS
OPCODE OPERAND
8000 21,00,85 LXI H, 8500 INITIALISE H-L PAIR
8003 7E MOV C,M Count in the C register
8004 23 INX H First number in H-L pair
8005 4E MOV A,M Move first number in to Accumulator
8006 0D DCR C Decrement the count
8007 91 LOOP1 INX H Get the next number
8008 BE CMP M Compare the next number with previous
number
8009 D2 JNC LOOP2 Is next number >previous maximum?No,go
to the loop2
800A 0D
800B 80
800C 7E MOV A,M If,yes move the large number in to
Accumulator
800D 0D LOOP2 DCR C Decrement the count
800E C2 JNZ LOOP1 If count not equal to zero,repeat
800F 07
8011 80
8012 78
8013 32 STA 85XX Store the largest number in the location
85XX
8014 XX
8015 85
8016 76 HLT Stop the execution
Stack Pointer (SP)
• It is a 16-bit special purpose register which always stores the address of
top of the Stack. i.e. it always points to top of the Stack.
• Stack is a part of the memory location used to store the data
temporarily.
• A stack works on Last in First out (LIFO) basis. As the Stack pointer
always points to the top of the Stack, only top of the Stack of the
memory can be accessed.
• When a Write operation (PUSH) takes place, the contents of the stack
pointer is decremented by two so that the SP points to the new location.
Stack Pointer (SP)
• Similarly when the Read operation (POP) occurs, the Stack pointer is
incremented by two to point to the next data on top of the Stack.
• The Stack Pointer is initialized by load register pair immediate
instruction.
• Ex: LXI SP, 8530 H
Here 8530 H is the 16 bit address of the top of Stack location.
Stack Details
• Stack is a set of memory locations in the Read/Write memory(RAM),
which is used for temporary storage of binary information during the
execution of a program.
• It is implemented in the Last-in-first-out (LIFO) manner. i.e., the data
written first can be accessed last.
• The stack may also be used for storing local variables of subroutine and
for the transfer of parameter addresses to a subroutine.
• This facilitates the implementation of re-entrant subroutines which is a
very important software property.
Stack operation
• Operations on stack are performed using the two instructions namely PUSH and
POP.
• The contents of the stack are moved to certain memory locations on stack after
PUSH instruction. Similarly, the contents of the stack are transferred back to
registers by POP instruction.
• For example, let us consider a Stack whose
stack top is 4506 H. This is stored in the
16-bit Stack pointer register as shown below.
• Let us consider two registers (register pair) B &
C whose contents are 25 & 62.
Reg. B Reg. C
contd
• After PUSH operation the status of the Stack is as shown below.
contd
• Let us now consider POP operation: The Figs below explains before
and after the POP operation in detail.
• Ex: POP B
Temporary Registers
• The two temporary data registers are W register and Z register. These
are 8-bit registers.
• We have already seen in the earlier video that one temporary data
register is associated with the ALU operations.
• Similarly W and Z are also temporary registers used to hold 8-bit data
during execution of certain instructions.
• As these registers are internally used by the CPU, they are not
accessible to the user.
• For ex: the W and Z registers are used by the processor during CALL
instruction.
contd
• When a CALL instruction is encountered in any program, the current
Program counter (PC) contents are pushed on to the stack and the given
address is loaded on to PC.
• The given address is temporarily stored in W and Z registers and
placed on the bus for the fetch cycle.
• Thus the program control is transferred to the address given in the
instruction.
• Another example is, during the execution of XCHG instruction, the
contents of H-L pair are exchanged with D-E pair.
• At the time of exchange W and Z registers are used for temporary
storage of data.
Microprocessor architecture   II

More Related Content

What's hot

Pic16cxx instruction set
Pic16cxx instruction setPic16cxx instruction set
Pic16cxx instruction set
v Kalairajan
 
Programmable Logic Devices Plds
Programmable Logic Devices PldsProgrammable Logic Devices Plds
Programmable Logic Devices Plds
Gaditek
 
Field-programmable gate array
Field-programmable gate arrayField-programmable gate array
Field-programmable gate array
PrinceArjun1999
 
TMS320C5x
TMS320C5xTMS320C5x
Divide by N clock
Divide by N clockDivide by N clock
Divide by N clock
Mantra VLSI
 
Unit 1 MPMC
Unit 1 MPMCUnit 1 MPMC
Unit 1 MPMC
tamilnesaner
 
Vlsi design flow
Vlsi design flowVlsi design flow
Vlsi design flow
Rajendra Kumar
 
FPGA
FPGAFPGA
Introduction to VLSI
Introduction to VLSI Introduction to VLSI
Introduction to VLSI illpa
 
prom,pld problems
prom,pld problemsprom,pld problems
prom,pld problemsAnish Gupta
 
Trends in Embedded system Design
Trends in Embedded system DesignTrends in Embedded system Design
Trends in Embedded system DesignRaman Deep
 
Virtual instrumentation (LabVIEW)
Virtual instrumentation (LabVIEW)Virtual instrumentation (LabVIEW)
Virtual instrumentation (LabVIEW)
Manipal University Jaipur
 
Report on VLSI
Report on VLSIReport on VLSI
Report on VLSI
MAYANK KUMAR
 
PIC Microcontrollers.ppt
PIC Microcontrollers.pptPIC Microcontrollers.ppt
PIC Microcontrollers.ppt
Dr.YNM
 
Asic design flow
Asic design flowAsic design flow
Asic design flow
yogeshwaran k
 
Real Life Application of Digital Electronics
Real Life Application of Digital ElectronicsReal Life Application of Digital Electronics
Real Life Application of Digital Electronics
Taslima Yasmin Tarin
 
Tutorial on FPGA Routing
Tutorial on FPGA RoutingTutorial on FPGA Routing
Tutorial on FPGA Routing
Daniel Gomez-Prado
 
Adiabatic logic or clock powered logic
Adiabatic logic or clock powered logicAdiabatic logic or clock powered logic
Adiabatic logic or clock powered logic
Tuhinansu Pradhan
 
LOW POWER DESIGN VLSI
LOW POWER DESIGN VLSILOW POWER DESIGN VLSI
LOW POWER DESIGN VLSI
Duronto riyad
 
Question paper with solution the 8051 microcontroller based embedded systems...
Question paper with solution  the 8051 microcontroller based embedded systems...Question paper with solution  the 8051 microcontroller based embedded systems...
Question paper with solution the 8051 microcontroller based embedded systems...
manishpatel_79
 

What's hot (20)

Pic16cxx instruction set
Pic16cxx instruction setPic16cxx instruction set
Pic16cxx instruction set
 
Programmable Logic Devices Plds
Programmable Logic Devices PldsProgrammable Logic Devices Plds
Programmable Logic Devices Plds
 
Field-programmable gate array
Field-programmable gate arrayField-programmable gate array
Field-programmable gate array
 
TMS320C5x
TMS320C5xTMS320C5x
TMS320C5x
 
Divide by N clock
Divide by N clockDivide by N clock
Divide by N clock
 
Unit 1 MPMC
Unit 1 MPMCUnit 1 MPMC
Unit 1 MPMC
 
Vlsi design flow
Vlsi design flowVlsi design flow
Vlsi design flow
 
FPGA
FPGAFPGA
FPGA
 
Introduction to VLSI
Introduction to VLSI Introduction to VLSI
Introduction to VLSI
 
prom,pld problems
prom,pld problemsprom,pld problems
prom,pld problems
 
Trends in Embedded system Design
Trends in Embedded system DesignTrends in Embedded system Design
Trends in Embedded system Design
 
Virtual instrumentation (LabVIEW)
Virtual instrumentation (LabVIEW)Virtual instrumentation (LabVIEW)
Virtual instrumentation (LabVIEW)
 
Report on VLSI
Report on VLSIReport on VLSI
Report on VLSI
 
PIC Microcontrollers.ppt
PIC Microcontrollers.pptPIC Microcontrollers.ppt
PIC Microcontrollers.ppt
 
Asic design flow
Asic design flowAsic design flow
Asic design flow
 
Real Life Application of Digital Electronics
Real Life Application of Digital ElectronicsReal Life Application of Digital Electronics
Real Life Application of Digital Electronics
 
Tutorial on FPGA Routing
Tutorial on FPGA RoutingTutorial on FPGA Routing
Tutorial on FPGA Routing
 
Adiabatic logic or clock powered logic
Adiabatic logic or clock powered logicAdiabatic logic or clock powered logic
Adiabatic logic or clock powered logic
 
LOW POWER DESIGN VLSI
LOW POWER DESIGN VLSILOW POWER DESIGN VLSI
LOW POWER DESIGN VLSI
 
Question paper with solution the 8051 microcontroller based embedded systems...
Question paper with solution  the 8051 microcontroller based embedded systems...Question paper with solution  the 8051 microcontroller based embedded systems...
Question paper with solution the 8051 microcontroller based embedded systems...
 

Similar to Microprocessor architecture II

Lec04
Lec04Lec04
Lec04
Lec04Lec04
module-2.pptx
module-2.pptxmodule-2.pptx
module-2.pptx
Ambika Naik
 
Assemblylanguageprogrammingof8085 100523023329-phpapp02
Assemblylanguageprogrammingof8085 100523023329-phpapp02Assemblylanguageprogrammingof8085 100523023329-phpapp02
Assemblylanguageprogrammingof8085 100523023329-phpapp02Swati Watve-Phadke
 
Chapter 7 - Programming Techniques with Additional Instructions
Chapter 7 - Programming Techniques with Additional InstructionsChapter 7 - Programming Techniques with Additional Instructions
Chapter 7 - Programming Techniques with Additional Instructions
cmkandemir
 
8085 Architecture
8085 Architecture8085 Architecture
8085 Architecture
Kumar Anand Singh
 
8085_Microprocessor(simar).ppt
8085_Microprocessor(simar).ppt8085_Microprocessor(simar).ppt
8085_Microprocessor(simar).ppt
KanikaJindal9
 
Assembly Language Paper.docx
Assembly Language Paper.docxAssembly Language Paper.docx
Assembly Language Paper.docx
write22
 
B sc e5.2 mp unit 4 mc-8051
B sc e5.2 mp unit 4 mc-8051B sc e5.2 mp unit 4 mc-8051
B sc e5.2 mp unit 4 mc-8051
MahiboobAliMulla
 
UNIT II.pptx
UNIT II.pptxUNIT II.pptx
UNIT II.pptx
ssuser47c811
 
lec3-8051microcontrollerarchitecture-230130044236-5c11a082.pptx
lec3-8051microcontrollerarchitecture-230130044236-5c11a082.pptxlec3-8051microcontrollerarchitecture-230130044236-5c11a082.pptx
lec3-8051microcontrollerarchitecture-230130044236-5c11a082.pptx
MadavanR1
 
Lec03
Lec03Lec03
microp-8085 74 instructions for mct-A :P
microp-8085 74 instructions for mct-A :Pmicrop-8085 74 instructions for mct-A :P
microp-8085 74 instructions for mct-A :P
Jathin Kanumuri
 
8085 Paper Presentation slides,ppt,microprocessor 8085 ,guide, instruction set
8085 Paper Presentation slides,ppt,microprocessor 8085 ,guide, instruction set8085 Paper Presentation slides,ppt,microprocessor 8085 ,guide, instruction set
8085 Paper Presentation slides,ppt,microprocessor 8085 ,guide, instruction set
Saumitra Rukmangad
 
microp-8085 74 instructions for mct-A :P-2
microp-8085 74 instructions for mct-A :P-2microp-8085 74 instructions for mct-A :P-2
microp-8085 74 instructions for mct-A :P-2
Jathin Kanumuri
 
8085-paper-presentation.ppt
8085-paper-presentation.ppt8085-paper-presentation.ppt
8085-paper-presentation.ppt
KalaiSelvan911913
 
Unit 4.pptx
Unit 4.pptxUnit 4.pptx
Unit 4.pptx
BLACKSPAROW
 
8085 microprocessor(1)
8085 microprocessor(1)8085 microprocessor(1)
8085 microprocessor(1)Reevu Pal
 
Introduction to 8085 by adi ppt
Introduction to 8085 by adi pptIntroduction to 8085 by adi ppt
Introduction to 8085 by adi ppt
Prof. Dr. K. Adisesha
 

Similar to Microprocessor architecture II (20)

Lec04
Lec04Lec04
Lec04
 
Lec04
Lec04Lec04
Lec04
 
module-2.pptx
module-2.pptxmodule-2.pptx
module-2.pptx
 
Assemblylanguageprogrammingof8085 100523023329-phpapp02
Assemblylanguageprogrammingof8085 100523023329-phpapp02Assemblylanguageprogrammingof8085 100523023329-phpapp02
Assemblylanguageprogrammingof8085 100523023329-phpapp02
 
Chapter 7 - Programming Techniques with Additional Instructions
Chapter 7 - Programming Techniques with Additional InstructionsChapter 7 - Programming Techniques with Additional Instructions
Chapter 7 - Programming Techniques with Additional Instructions
 
8085 Architecture
8085 Architecture8085 Architecture
8085 Architecture
 
8085_Microprocessor(simar).ppt
8085_Microprocessor(simar).ppt8085_Microprocessor(simar).ppt
8085_Microprocessor(simar).ppt
 
MicroProcessors
MicroProcessors MicroProcessors
MicroProcessors
 
Assembly Language Paper.docx
Assembly Language Paper.docxAssembly Language Paper.docx
Assembly Language Paper.docx
 
B sc e5.2 mp unit 4 mc-8051
B sc e5.2 mp unit 4 mc-8051B sc e5.2 mp unit 4 mc-8051
B sc e5.2 mp unit 4 mc-8051
 
UNIT II.pptx
UNIT II.pptxUNIT II.pptx
UNIT II.pptx
 
lec3-8051microcontrollerarchitecture-230130044236-5c11a082.pptx
lec3-8051microcontrollerarchitecture-230130044236-5c11a082.pptxlec3-8051microcontrollerarchitecture-230130044236-5c11a082.pptx
lec3-8051microcontrollerarchitecture-230130044236-5c11a082.pptx
 
Lec03
Lec03Lec03
Lec03
 
microp-8085 74 instructions for mct-A :P
microp-8085 74 instructions for mct-A :Pmicrop-8085 74 instructions for mct-A :P
microp-8085 74 instructions for mct-A :P
 
8085 Paper Presentation slides,ppt,microprocessor 8085 ,guide, instruction set
8085 Paper Presentation slides,ppt,microprocessor 8085 ,guide, instruction set8085 Paper Presentation slides,ppt,microprocessor 8085 ,guide, instruction set
8085 Paper Presentation slides,ppt,microprocessor 8085 ,guide, instruction set
 
microp-8085 74 instructions for mct-A :P-2
microp-8085 74 instructions for mct-A :P-2microp-8085 74 instructions for mct-A :P-2
microp-8085 74 instructions for mct-A :P-2
 
8085-paper-presentation.ppt
8085-paper-presentation.ppt8085-paper-presentation.ppt
8085-paper-presentation.ppt
 
Unit 4.pptx
Unit 4.pptxUnit 4.pptx
Unit 4.pptx
 
8085 microprocessor(1)
8085 microprocessor(1)8085 microprocessor(1)
8085 microprocessor(1)
 
Introduction to 8085 by adi ppt
Introduction to 8085 by adi pptIntroduction to 8085 by adi ppt
Introduction to 8085 by adi ppt
 

More from Dr.YNM

Introduction to DSP.ppt
Introduction to DSP.pptIntroduction to DSP.ppt
Introduction to DSP.ppt
Dr.YNM
 
Atmel.ppt
Atmel.pptAtmel.ppt
Atmel.ppt
Dr.YNM
 
Crystalstructure-.ppt
Crystalstructure-.pptCrystalstructure-.ppt
Crystalstructure-.ppt
Dr.YNM
 
Basics of OS & RTOS.ppt
Basics of OS & RTOS.pptBasics of OS & RTOS.ppt
Basics of OS & RTOS.ppt
Dr.YNM
 
Introducion to MSP430 Microcontroller.pptx
Introducion to MSP430 Microcontroller.pptxIntroducion to MSP430 Microcontroller.pptx
Introducion to MSP430 Microcontroller.pptx
Dr.YNM
 
Microcontroller-8051.ppt
Microcontroller-8051.pptMicrocontroller-8051.ppt
Microcontroller-8051.ppt
Dr.YNM
 
Introduction to ASICs.pptx
Introduction to ASICs.pptxIntroduction to ASICs.pptx
Introduction to ASICs.pptx
Dr.YNM
 
VHDL-PRESENTATION.ppt
VHDL-PRESENTATION.pptVHDL-PRESENTATION.ppt
VHDL-PRESENTATION.ppt
Dr.YNM
 
Basics of data communications.pptx
Basics of data communications.pptxBasics of data communications.pptx
Basics of data communications.pptx
Dr.YNM
 
CPLD & FPGA Architectures and applictionsplications.pptx
CPLD & FPGA Architectures and applictionsplications.pptxCPLD & FPGA Architectures and applictionsplications.pptx
CPLD & FPGA Architectures and applictionsplications.pptx
Dr.YNM
 
Transient response of RC , RL circuits with step input
Transient response of RC , RL circuits  with step inputTransient response of RC , RL circuits  with step input
Transient response of RC , RL circuits with step input
Dr.YNM
 
CISC & RISC ARCHITECTURES
CISC & RISC ARCHITECTURESCISC & RISC ARCHITECTURES
CISC & RISC ARCHITECTURES
Dr.YNM
 
Lect 4 ARM PROCESSOR ARCHITECTURE
Lect 4 ARM PROCESSOR ARCHITECTURELect 4 ARM PROCESSOR ARCHITECTURE
Lect 4 ARM PROCESSOR ARCHITECTURE
Dr.YNM
 
Lect 3 ARM PROCESSOR ARCHITECTURE
Lect 3  ARM PROCESSOR ARCHITECTURE Lect 3  ARM PROCESSOR ARCHITECTURE
Lect 3 ARM PROCESSOR ARCHITECTURE
Dr.YNM
 
Microprocessor Architecture 4
Microprocessor Architecture  4Microprocessor Architecture  4
Microprocessor Architecture 4
Dr.YNM
 
Lect 2 ARM processor architecture
Lect 2 ARM processor architectureLect 2 ARM processor architecture
Lect 2 ARM processor architecture
Dr.YNM
 
Microprocessor Architecture-III
Microprocessor Architecture-IIIMicroprocessor Architecture-III
Microprocessor Architecture-III
Dr.YNM
 
LECT 1: ARM PROCESSORS
LECT 1: ARM PROCESSORSLECT 1: ARM PROCESSORS
LECT 1: ARM PROCESSORS
Dr.YNM
 
Verilog Test Bench
Verilog Test BenchVerilog Test Bench
Verilog Test Bench
Dr.YNM
 
Microprocessor architecture-I
Microprocessor architecture-IMicroprocessor architecture-I
Microprocessor architecture-I
Dr.YNM
 

More from Dr.YNM (20)

Introduction to DSP.ppt
Introduction to DSP.pptIntroduction to DSP.ppt
Introduction to DSP.ppt
 
Atmel.ppt
Atmel.pptAtmel.ppt
Atmel.ppt
 
Crystalstructure-.ppt
Crystalstructure-.pptCrystalstructure-.ppt
Crystalstructure-.ppt
 
Basics of OS & RTOS.ppt
Basics of OS & RTOS.pptBasics of OS & RTOS.ppt
Basics of OS & RTOS.ppt
 
Introducion to MSP430 Microcontroller.pptx
Introducion to MSP430 Microcontroller.pptxIntroducion to MSP430 Microcontroller.pptx
Introducion to MSP430 Microcontroller.pptx
 
Microcontroller-8051.ppt
Microcontroller-8051.pptMicrocontroller-8051.ppt
Microcontroller-8051.ppt
 
Introduction to ASICs.pptx
Introduction to ASICs.pptxIntroduction to ASICs.pptx
Introduction to ASICs.pptx
 
VHDL-PRESENTATION.ppt
VHDL-PRESENTATION.pptVHDL-PRESENTATION.ppt
VHDL-PRESENTATION.ppt
 
Basics of data communications.pptx
Basics of data communications.pptxBasics of data communications.pptx
Basics of data communications.pptx
 
CPLD & FPGA Architectures and applictionsplications.pptx
CPLD & FPGA Architectures and applictionsplications.pptxCPLD & FPGA Architectures and applictionsplications.pptx
CPLD & FPGA Architectures and applictionsplications.pptx
 
Transient response of RC , RL circuits with step input
Transient response of RC , RL circuits  with step inputTransient response of RC , RL circuits  with step input
Transient response of RC , RL circuits with step input
 
CISC & RISC ARCHITECTURES
CISC & RISC ARCHITECTURESCISC & RISC ARCHITECTURES
CISC & RISC ARCHITECTURES
 
Lect 4 ARM PROCESSOR ARCHITECTURE
Lect 4 ARM PROCESSOR ARCHITECTURELect 4 ARM PROCESSOR ARCHITECTURE
Lect 4 ARM PROCESSOR ARCHITECTURE
 
Lect 3 ARM PROCESSOR ARCHITECTURE
Lect 3  ARM PROCESSOR ARCHITECTURE Lect 3  ARM PROCESSOR ARCHITECTURE
Lect 3 ARM PROCESSOR ARCHITECTURE
 
Microprocessor Architecture 4
Microprocessor Architecture  4Microprocessor Architecture  4
Microprocessor Architecture 4
 
Lect 2 ARM processor architecture
Lect 2 ARM processor architectureLect 2 ARM processor architecture
Lect 2 ARM processor architecture
 
Microprocessor Architecture-III
Microprocessor Architecture-IIIMicroprocessor Architecture-III
Microprocessor Architecture-III
 
LECT 1: ARM PROCESSORS
LECT 1: ARM PROCESSORSLECT 1: ARM PROCESSORS
LECT 1: ARM PROCESSORS
 
Verilog Test Bench
Verilog Test BenchVerilog Test Bench
Verilog Test Bench
 
Microprocessor architecture-I
Microprocessor architecture-IMicroprocessor architecture-I
Microprocessor architecture-I
 

Recently uploaded

weather web application report.pdf
weather web application report.pdfweather web application report.pdf
weather web application report.pdf
Pratik Pawar
 
Immunizing Image Classifiers Against Localized Adversary Attacks
Immunizing Image Classifiers Against Localized Adversary AttacksImmunizing Image Classifiers Against Localized Adversary Attacks
Immunizing Image Classifiers Against Localized Adversary Attacks
gerogepatton
 
Standard Reomte Control Interface - Neometrix
Standard Reomte Control Interface - NeometrixStandard Reomte Control Interface - Neometrix
Standard Reomte Control Interface - Neometrix
Neometrix_Engineering_Pvt_Ltd
 
MCQ Soil mechanics questions (Soil shear strength).pdf
MCQ Soil mechanics questions (Soil shear strength).pdfMCQ Soil mechanics questions (Soil shear strength).pdf
MCQ Soil mechanics questions (Soil shear strength).pdf
Osamah Alsalih
 
WATER CRISIS and its solutions-pptx 1234
WATER CRISIS and its solutions-pptx 1234WATER CRISIS and its solutions-pptx 1234
WATER CRISIS and its solutions-pptx 1234
AafreenAbuthahir2
 
TECHNICAL TRAINING MANUAL GENERAL FAMILIARIZATION COURSE
TECHNICAL TRAINING MANUAL   GENERAL FAMILIARIZATION COURSETECHNICAL TRAINING MANUAL   GENERAL FAMILIARIZATION COURSE
TECHNICAL TRAINING MANUAL GENERAL FAMILIARIZATION COURSE
DuvanRamosGarzon1
 
Halogenation process of chemical process industries
Halogenation process of chemical process industriesHalogenation process of chemical process industries
Halogenation process of chemical process industries
MuhammadTufail242431
 
Final project report on grocery store management system..pdf
Final project report on grocery store management system..pdfFinal project report on grocery store management system..pdf
Final project report on grocery store management system..pdf
Kamal Acharya
 
在线办理(ANU毕业证书)澳洲国立大学毕业证录取通知书一模一样
在线办理(ANU毕业证书)澳洲国立大学毕业证录取通知书一模一样在线办理(ANU毕业证书)澳洲国立大学毕业证录取通知书一模一样
在线办理(ANU毕业证书)澳洲国立大学毕业证录取通知书一模一样
obonagu
 
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
bakpo1
 
H.Seo, ICLR 2024, MLILAB, KAIST AI.pdf
H.Seo,  ICLR 2024, MLILAB,  KAIST AI.pdfH.Seo,  ICLR 2024, MLILAB,  KAIST AI.pdf
H.Seo, ICLR 2024, MLILAB, KAIST AI.pdf
MLILAB
 
Event Management System Vb Net Project Report.pdf
Event Management System Vb Net  Project Report.pdfEvent Management System Vb Net  Project Report.pdf
Event Management System Vb Net Project Report.pdf
Kamal Acharya
 
The role of big data in decision making.
The role of big data in decision making.The role of big data in decision making.
The role of big data in decision making.
ankuprajapati0525
 
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptx
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxCFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptx
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptx
R&R Consult
 
block diagram and signal flow graph representation
block diagram and signal flow graph representationblock diagram and signal flow graph representation
block diagram and signal flow graph representation
Divya Somashekar
 
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdf
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdfHybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdf
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdf
fxintegritypublishin
 
Nuclear Power Economics and Structuring 2024
Nuclear Power Economics and Structuring 2024Nuclear Power Economics and Structuring 2024
Nuclear Power Economics and Structuring 2024
Massimo Talia
 
Cosmetic shop management system project report.pdf
Cosmetic shop management system project report.pdfCosmetic shop management system project report.pdf
Cosmetic shop management system project report.pdf
Kamal Acharya
 
J.Yang, ICLR 2024, MLILAB, KAIST AI.pdf
J.Yang,  ICLR 2024, MLILAB, KAIST AI.pdfJ.Yang,  ICLR 2024, MLILAB, KAIST AI.pdf
J.Yang, ICLR 2024, MLILAB, KAIST AI.pdf
MLILAB
 
Democratizing Fuzzing at Scale by Abhishek Arya
Democratizing Fuzzing at Scale by Abhishek AryaDemocratizing Fuzzing at Scale by Abhishek Arya
Democratizing Fuzzing at Scale by Abhishek Arya
abh.arya
 

Recently uploaded (20)

weather web application report.pdf
weather web application report.pdfweather web application report.pdf
weather web application report.pdf
 
Immunizing Image Classifiers Against Localized Adversary Attacks
Immunizing Image Classifiers Against Localized Adversary AttacksImmunizing Image Classifiers Against Localized Adversary Attacks
Immunizing Image Classifiers Against Localized Adversary Attacks
 
Standard Reomte Control Interface - Neometrix
Standard Reomte Control Interface - NeometrixStandard Reomte Control Interface - Neometrix
Standard Reomte Control Interface - Neometrix
 
MCQ Soil mechanics questions (Soil shear strength).pdf
MCQ Soil mechanics questions (Soil shear strength).pdfMCQ Soil mechanics questions (Soil shear strength).pdf
MCQ Soil mechanics questions (Soil shear strength).pdf
 
WATER CRISIS and its solutions-pptx 1234
WATER CRISIS and its solutions-pptx 1234WATER CRISIS and its solutions-pptx 1234
WATER CRISIS and its solutions-pptx 1234
 
TECHNICAL TRAINING MANUAL GENERAL FAMILIARIZATION COURSE
TECHNICAL TRAINING MANUAL   GENERAL FAMILIARIZATION COURSETECHNICAL TRAINING MANUAL   GENERAL FAMILIARIZATION COURSE
TECHNICAL TRAINING MANUAL GENERAL FAMILIARIZATION COURSE
 
Halogenation process of chemical process industries
Halogenation process of chemical process industriesHalogenation process of chemical process industries
Halogenation process of chemical process industries
 
Final project report on grocery store management system..pdf
Final project report on grocery store management system..pdfFinal project report on grocery store management system..pdf
Final project report on grocery store management system..pdf
 
在线办理(ANU毕业证书)澳洲国立大学毕业证录取通知书一模一样
在线办理(ANU毕业证书)澳洲国立大学毕业证录取通知书一模一样在线办理(ANU毕业证书)澳洲国立大学毕业证录取通知书一模一样
在线办理(ANU毕业证书)澳洲国立大学毕业证录取通知书一模一样
 
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
 
H.Seo, ICLR 2024, MLILAB, KAIST AI.pdf
H.Seo,  ICLR 2024, MLILAB,  KAIST AI.pdfH.Seo,  ICLR 2024, MLILAB,  KAIST AI.pdf
H.Seo, ICLR 2024, MLILAB, KAIST AI.pdf
 
Event Management System Vb Net Project Report.pdf
Event Management System Vb Net  Project Report.pdfEvent Management System Vb Net  Project Report.pdf
Event Management System Vb Net Project Report.pdf
 
The role of big data in decision making.
The role of big data in decision making.The role of big data in decision making.
The role of big data in decision making.
 
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptx
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxCFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptx
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptx
 
block diagram and signal flow graph representation
block diagram and signal flow graph representationblock diagram and signal flow graph representation
block diagram and signal flow graph representation
 
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdf
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdfHybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdf
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdf
 
Nuclear Power Economics and Structuring 2024
Nuclear Power Economics and Structuring 2024Nuclear Power Economics and Structuring 2024
Nuclear Power Economics and Structuring 2024
 
Cosmetic shop management system project report.pdf
Cosmetic shop management system project report.pdfCosmetic shop management system project report.pdf
Cosmetic shop management system project report.pdf
 
J.Yang, ICLR 2024, MLILAB, KAIST AI.pdf
J.Yang,  ICLR 2024, MLILAB, KAIST AI.pdfJ.Yang,  ICLR 2024, MLILAB, KAIST AI.pdf
J.Yang, ICLR 2024, MLILAB, KAIST AI.pdf
 
Democratizing Fuzzing at Scale by Abhishek Arya
Democratizing Fuzzing at Scale by Abhishek AryaDemocratizing Fuzzing at Scale by Abhishek Arya
Democratizing Fuzzing at Scale by Abhishek Arya
 

Microprocessor architecture II

  • 2. Register Organization • The 8085 microprocessor has various types of registers as shown below. • It includes six , 8 – bit registers (B, C, D. E, H and L), one 8-bit Accumulator ,One Flag register and two 16-bit registers (SP and PC). • Also there are two 8-bit temporary registers W and Z. • These registers W and Z are not accessible to the user, They are used by the processor for internal, intermediate operations. • These registers B, C, D. E, H and L are known • as general purpose registers.
  • 3. contd • The registers Program Counter and Stack Pointer are known as the speci purpose Registers. • So, the total registers are classified into three groups .They are (i).Temporary registers. (W and Z ) (ii).General purpose registers (B, C, D. E, H and L) (iii).Special purpose registers. (SP and PC). • The special purpose registers PC and SP are 16 bit registers. • As you know 8085 is a 8-bit processor with 16 bit-address bus.So, the address of the memory location is always16-bit . • But a very interesting thing is there are no 16-bit general purpose registers to hold the address of the memory location.
  • 4. contd • To overcome this limitation, Intel has provided the feature of Register pairing. • That is two 8-bitregisters are paired so that they can store a 16-bt address. • The admissible register pairs are B-C; D-E and H-L only. No other pairs are allowed. • These pair of register are mainly used only during the times of address accessing . • At all the other times they are only 8-bit data registers (B,C,D,E,H and L). • Let us see this with an example. • LXI H 8509 ; It means, load immediately the register pair H-L with the address 8509.
  • 5. contd • Here L-register is loaded with 09 and H-register is loaded with address 85H. Here H indicates that the address is Hexadecimal. • It is a three byte instruction.(Hex code = 21, 09, 85 (Three bytes) 21 = 0010 0001 8-bits = 1 byte 09 = 0000 1001 8-bits = 1 byte 85 = 1000 0110 8-bits = 1 byte Total 3-bytes
  • 6. Program Counter (PC) • It is a 16-bit special purpose register, which stores the address of the next instruction to be fetched or executed. • The execution of a program is initiated by loading the PC by the address of the first instruction of the program. • Once the first instruction is executed, the PC is automatically incremented to point to the next instruction unless a jump to some specific address occurs. • This process is repeated till the last instruction of the program is executed. •
  • 7. contd • Here the diagram shows the Operation of PC.
  • 8. contd • In case of JUMP or CALL instructions, current address is stored in the Program Counter. • The processor then fetches the next instruction from the new address specified by the JUMP or CALL instruction. Address HEX – CODE LABEL MNEMONIC COMMENTS OPCODE OPERAND 8000 21,00,85 LXI H, 8500 INITIALISE H-L PAIR 8003 7E MOV C,M Count in the C register 8004 23 INX H First number in H-L pair 8005 4E MOV A,M Move first number in to Accumulator 8006 0D DCR C Decrement the count 8007 91 LOOP1 INX H Get the next number 8008 BE CMP M Compare the next number with previous number 8009 D2 JNC LOOP2 Is next number >previous maximum?No,go to the loop2 800A 0D 800B 80 800C 7E MOV A,M If,yes move the large number in to Accumulator 800D 0D LOOP2 DCR C Decrement the count 800E C2 JNZ LOOP1 If count not equal to zero,repeat 800F 07 8011 80 8012 78 8013 32 STA 85XX Store the largest number in the location 85XX 8014 XX 8015 85 8016 76 HLT Stop the execution
  • 9. Stack Pointer (SP) • It is a 16-bit special purpose register which always stores the address of top of the Stack. i.e. it always points to top of the Stack. • Stack is a part of the memory location used to store the data temporarily. • A stack works on Last in First out (LIFO) basis. As the Stack pointer always points to the top of the Stack, only top of the Stack of the memory can be accessed. • When a Write operation (PUSH) takes place, the contents of the stack pointer is decremented by two so that the SP points to the new location.
  • 10. Stack Pointer (SP) • Similarly when the Read operation (POP) occurs, the Stack pointer is incremented by two to point to the next data on top of the Stack. • The Stack Pointer is initialized by load register pair immediate instruction. • Ex: LXI SP, 8530 H Here 8530 H is the 16 bit address of the top of Stack location.
  • 11. Stack Details • Stack is a set of memory locations in the Read/Write memory(RAM), which is used for temporary storage of binary information during the execution of a program. • It is implemented in the Last-in-first-out (LIFO) manner. i.e., the data written first can be accessed last. • The stack may also be used for storing local variables of subroutine and for the transfer of parameter addresses to a subroutine. • This facilitates the implementation of re-entrant subroutines which is a very important software property.
  • 12. Stack operation • Operations on stack are performed using the two instructions namely PUSH and POP. • The contents of the stack are moved to certain memory locations on stack after PUSH instruction. Similarly, the contents of the stack are transferred back to registers by POP instruction. • For example, let us consider a Stack whose stack top is 4506 H. This is stored in the 16-bit Stack pointer register as shown below. • Let us consider two registers (register pair) B & C whose contents are 25 & 62. Reg. B Reg. C
  • 13. contd • After PUSH operation the status of the Stack is as shown below.
  • 14. contd • Let us now consider POP operation: The Figs below explains before and after the POP operation in detail. • Ex: POP B
  • 15. Temporary Registers • The two temporary data registers are W register and Z register. These are 8-bit registers. • We have already seen in the earlier video that one temporary data register is associated with the ALU operations. • Similarly W and Z are also temporary registers used to hold 8-bit data during execution of certain instructions. • As these registers are internally used by the CPU, they are not accessible to the user. • For ex: the W and Z registers are used by the processor during CALL instruction.
  • 16. contd • When a CALL instruction is encountered in any program, the current Program counter (PC) contents are pushed on to the stack and the given address is loaded on to PC. • The given address is temporarily stored in W and Z registers and placed on the bus for the fetch cycle. • Thus the program control is transferred to the address given in the instruction. • Another example is, during the execution of XCHG instruction, the contents of H-L pair are exchanged with D-E pair. • At the time of exchange W and Z registers are used for temporary storage of data.