Verilog is a hardware description language used to model digital circuits. It was created in 1984 by Phil Moorby and Prabhu Goel. The language became an IEEE standard called Verilog-1995. Later revisions include Verilog-2001 and Verilog-2005. Verilog code uses modules to describe circuits and gates. It is commonly used with the Icarus Verilog compiler to simulate and synthesize designs. Examples show how to write Verilog code to implement logic gates like AND gates and multiplexers.

1. Digital Electronics

2. Presenter
Mohammad Yeasin Newaj

3. Definition and Details
History and Origin of Verilog
Basic Syntax of Verilog
01
Contents
Verilog
02 History
03 Syntax
04 Compiler
Software to run Verilog Log
05 Example of Verilog using gates
Example

4. Verilog
01
What is Verilog?

5. What is Verilog?
Verilog is a Hardware Description Language; a textual format for describing electronic circuits and
systems. Applied to electronic design, Verilog is intended to be used for verification through simulation,
for timing analysis, for test analysis (testability analysis and fault grading) and for logic synthesis.
The Verilog HDL is an IEEE standard - number 1364. The first version of the IEEE standard for Verilog
was published in 1995. A revised version was published in 2001; this is the version used by most
Verilog users. The IEEE Verilog standard document is known as the Language Reference Manual, or
LRM. This is the complete authoritative definition of the Verilog HDL.
A further revision of the Verilog standard was published in 2005, though it has little extra compared to
the 2001 standard. SystemVerilog is a huge set of extensions to Verilog, and was first published as an
IEEE standard in 2005. See the appropriate Knowhow section for more details about SystemVerilog.
IEEE Std 1364 also defines the Programming Language Interface, or PLI. This is a collection of software
routines which permit a bidirectional interface between Verilog and other languages (usually C).
Note that VHDL is not an abbreviation for Verilog HDL - Verilog and VHDL are two different HDLs. They
have more similarities than differences, however.

6. Short Definition of Verilog
Verilog, standardized as IEEE 1364, is a hardware
description language (HDL) which is used to
model electronic systems.
It is most commonly used in the design and
verification of digital circuits at the register-
transfer level of abstraction.
It is also used in the verification of analog
circuits and mixed-signal circuits, as well as in the
design of genetic circuits.[

7. History
02
History and Origin of Verilog

8. History of Verilog
In its original form, Verilog was intended to describe and simulate the automated synthesis of language subsets. After the
language created started spreading, it expanded to include structures such as gates which is how Verilog is used today.
One of the first hardware description languages to be created, Verilog was the brainchild of Prabhu Goel, Chi-Lai Huang,
Douglas Warmke, and Phil Moorby. Working over the winter of 1983 to 1984, the team created Verilog using their own
experience in similar systems. Chi-Lau Huang had helped to foster the LALDS hardware description.
The success of VDHL caused Cadence to make the move to expand Verilog for open standardization by transferring it to the
public domain. This move created the organization Accellera which was originally known as Open Verilog International. The
Verilog became IEEE Standard 1346 – 1995 or Verilog-95 as it was known.
Called the Automated Integrated Design Systems, the company that had been formed was purchased by Cadence Design
Systems in 1990. Today, Cadence retains all property rights to the Verilog and Verilog-XL design originated by the Gateway
Design Automation company. The success of the Verilog-95 led to numerous advances over the next several years. In
addition, the Verilog-A was created as a support to Spectre, an analog simulator, although it was never intended to be a
language that stood by itself.
The next major step occurred six years later when a new Verilog system was sent to the IEEE that offered improvements to
the system. Called the IEEE 1364-2001, it is better known as the Verilog-2001. Most of the upgrades included support for
variables and signed nets, a smoothing out of the signed operations process that helped to improve overall performance. In
addition, there was control over the statement instantiation which also improved the process significantly.
In 2005, another improvement was made to the Verilog system, although it was not as dramatic a leap from the Verilog-95 to
the Verilog-2001. The Verilog-2005 offered some new language features and clarified some spec and other aspects of the
design to make it run smoother. In addition, the Verilog-AMS was developed to bring together both mixed and analog sound
modeling and incorporate it into the traditional Verilog system.

9. Who invented Verilog?
Verilog HDL was invented by
Phil Moorby and Prabhu Goel
around 1984. It served as a
proprietary hardware
modeling language owned by
Gateway Design Automation
Inc. At that time, the language
was not standardized. It
modified itself in almost all
the revisions that came out
between 1984 to 1990.

10. Syntax
03
Basic Syntax of Verilog

11. Basic Syntax of a Verilog
An example for AND gate implementation using Verilog:
module and2 (c, b, a);
output c; // module outputs
input a,b; // module inputs
assign c = a&b; // continuous assignment
endmodule

12. Complex Verilog code for a specific design

13. Compiler
04
Compiler or Software to run Verilog Codes

14. Compiler or Software to use Verilog
Icarus Verilog
Icarus Verilog is the most common Verilog
simulation and synthesis tool.
It operates as a compiler, compiling source
code written in Verilog (IEEE-1364) into some
target format. For batch simulation, the
compiler can generate an intermediate form
called vvp assembly.

15. Interface of Icarus Verilog

16. Example
05
Example of Verilog Codes using Gates

17. Example of Verilog using gates - 1
The Logic Circuit for a Multiplexer
Verilog codes

18. Example of Verilog using gates - 2
module newaj (A,B,C,D,H);
Input A, B, C, D;
Output H;
and (z1, A, B, C);
and (z2, ~A, B, ~D);
Or (H, z1, z2);
endmodule

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