Prepare a Verilog HDL code for the following register: Positive Edge triggered gated latch D Flip Flop. Bring a soft copy of your Verilog HDL code with you to the lab. Solution Verilog tools Text editor: nedit is a graphical text editor that has syntax highlighting for Verilog. nedit & gedit & vi - Text based editor vi & Verilog simulator: verlogXL Event-based simulation - interpreted Verilog verilog myfile1.v myfile2.v myfile3.v ... & Other Verilog simulators you can use in the computers in ECSS 2.103 & 2.104 (Open Access Lab) : · Xilinx ISE · ModelSim For tutorials please google. Waveform viewer: WaveView CosmosScope 1. Introduction to Verilog These are just a few basic ideas of how verilog works. I would recommend you read “Verilog HDL A Guide Digital Design and Synthesis,” Palnitkar, Samir, SunSoft Press, A Prentice Hall Title, 1996. Verilog syntax and Structure In addition, A quick tutorial on Verilog and reference card are up. Verilog HDL - I : Combinational Logic Verilog HDL - II : Sequential Logic Verilog HDL quick reference card Verilog Learning website 2. Synthesizable Verilog code In VLSI design we are mostly concerned with synthesizable verilog. For synthesizing your finite state machine using a tool such as Synopsys Design Compiler certain rules have to be followed. (please read those rules carefully; if these rules are not followed it will cause big problems when using Synopsys). Verilog Restrictions for Synthesis ¨ Not all HDL constructs are synthesizable. ¨ Simulatable designs are not necessarily synthesizable. ¨ Synthesizable constructs are tool dependent ¨ Use only few HDL commands case if else concurrent and sequential statements ¨ Keep the intended circuit architecture in mind during design description. ¨ Using C-like programming style increases the silicon area dramatically. ¨ Type conversions and test stimuli definitions cannot be synthesized. ¨ Make extensive use of comments. ¨ Use headers for all modules, functions ¨ Explain the operating modes of the modules ¨ Explain all input and output signals ¨ Compiler directives reside within comments ¨ Smallest HDL code does not imply smallest silicon. ¨ Describe the architecture clearly. ¨ Cover all possible states within a if-else or case statement. ¨ Do not use nested loops for circuit description ¨ Do not define functions when instantiating parts within one entity. Here is an excellent link to a site which gives information about Verilog for synthesis: Synthesis flow Synthesizable Verilog Example with Test Bench Traffic Light Example NOTE: The library used in VLSI class only contains flip-flop. In order to only use flip-flop in the design, please only use \"posedge clock\" in the always block. Put other signals in the block, will cause the synthesizer pick LATCH or other sequential circuits for your design. Example: always @ (posedge clock) begin ... end 3. Behavior Verilog simulation You can simulate your file from the VLSI sever or Sun machine at the lab after set up your.

1. Prepare a Verilog HDL code for the following register: Positive Edge triggered gated latch D
Flip Flop. Bring a soft copy of your Verilog HDL code with you to the lab.
Solution
Verilog tools
Text editor:
nedit is a graphical text editor that has syntax highlighting for Verilog.
nedit &
gedit &
vi - Text based editor
vi &
Verilog simulator:
verlogXL Event-based simulation - interpreted Verilog
verilog myfile1.v myfile2.v myfile3.v ... &
Other Verilog simulators you can use in the computers in ECSS 2.103 & 2.104 (Open Access
Lab) :
· Xilinx ISE
· ModelSim
For tutorials please google.
Waveform viewer:
WaveView
CosmosScope
1. Introduction to Verilog
These are just a few basic ideas of how verilog works. I would recommend you read “Verilog
HDL A Guide Digital Design and Synthesis,” Palnitkar, Samir, SunSoft Press, A Prentice Hall
Title, 1996.
Verilog syntax and Structure
In addition, A quick tutorial on Verilog and reference card are up.
Verilog HDL - I : Combinational Logic
Verilog HDL - II : Sequential Logic
Verilog HDL quick reference card
Verilog Learning website
2. Synthesizable Verilog code
In VLSI design we are mostly concerned with synthesizable verilog. For synthesizing your finite
state machine using a tool such as Synopsys Design Compiler certain rules have to be followed.

2. (please read those rules carefully; if these rules are not followed it will cause big problems when
using Synopsys).
Verilog Restrictions for Synthesis
¨ Not all HDL constructs are synthesizable.
¨ Simulatable designs are not necessarily synthesizable.
¨ Synthesizable constructs are tool dependent
¨ Use only few HDL commands
case
if else
concurrent and sequential statements
¨ Keep the intended circuit architecture in mind during design description.
¨ Using C-like programming style increases the silicon area dramatically.
¨ Type conversions and test stimuli definitions cannot be synthesized.
¨ Make extensive use of comments.
¨ Use headers for all modules, functions
¨ Explain the operating modes of the modules
¨ Explain all input and output signals
¨ Compiler directives reside within comments
¨ Smallest HDL code does not imply smallest silicon.
¨ Describe the architecture clearly.
¨ Cover all possible states within a if-else or case statement.
¨ Do not use nested loops for circuit description
¨ Do not define functions when instantiating parts within one entity.
Here is an excellent link to a site which gives information about Verilog for synthesis:
Synthesis flow
Synthesizable Verilog Example with Test Bench
Traffic Light Example
NOTE: The library used in VLSI class only contains flip-flop. In order to only use flip-flop in
the design, please only use "posedge clock" in the always block. Put other signals in the block,
will cause the synthesizer pick LATCH or other sequential circuits for your design.
Example:
always @ (posedge clock)
begin
...
end

3. 3. Behavior Verilog simulation
You can simulate your file from the VLSI sever or Sun machine at the lab after set up your
environment by entering following command.
(you have to do this every time you open a new terminal session)
. /proj/cad/startup/profile.ic-5
You insert one of these verilog commands in your test bench module
Put it right after "initial begin"
initial
begin
(monitor command or dump command)
#(clockDelay) malfunction = 1'b0;
#(clockDelay) reset = 1'b0;
#(clockDelay) reset = 1'b0;
#(clockDelay) ready = 1'b1;
end
to check result by text
$monitor ("variable1 name in output text, variable2 name in output text ", variable1,
variable2);
to get a wave file.
initial
begin
$dumpfile("your_file.dump");
$dumpvars;
$finish;
end
and now, you can simulate your file with verilog XL by entering following command:
verilog your_verilog_file.v
After you finish compiling the simulation, you'll have a directory calledyour_file.dump.