Aldec is a leading EDA company founded in 1984 that provides RTL simulation, verification, and emulation solutions. It has over 200 employees and 30,000 licenses worldwide. Aldec's key products include Active-HDL for simulation, Riviera-PRO for verification, ALINTTM for linting, and HES for emulation. Aldec focuses on continuous innovation to provide better performance, more features, and lower prices than competitors.

1. Aldec – The Design
Verification Company
www.aldec.com

2. History - Background
• Founded 1984
• Privately Held, revenue funded
• Employees 200+
• Leading EDA Verification Technologies
• RTL Simulation
• HDL STARC Linting Software
• Hardware assisted
Acceleration/Emulation
• IP Cores
• Specialty Solutions
• DO-254 Verification Tools
Aldec holds an estimated • Actel® Prototyping
30% market share in non-OEM
simulator sales to FPGA designers. • Over 30,000 Licenses World-Wide
Aldec wins a majority of competitive • Several Key Technology Patents
engagements. Consistently winning in • Office Locations:
technology, flexibility and value. • Japan, China, France, India
• Distribution Channel
www.aldec.com

3. Product Portfolio
Active-HDL™
Graphical Design Entry + Simulator + Multi FPGA Vendor Flow Manager
HDL Language Support: VHDL, Verilog®, EDIF, SystemC and SystemVerilog
Operating System Support: Windows® XP and Vista 32/64 bit support
Riviera-PRO™
ASIC Simulator + Assertions+ OVM, ESL
HDL Language Support: VHDL, Verilog®, EDIF, SystemC, SystemVerilog, SVA and PSL
Operating System Support: Windows® XP and Vista 32/64 bit, Linux® 32/64 bit and Sun® Solaris
ALINT™
ALINT is a highly optimized design rule checker, which detects design errors in ASIC/FPGA designs.
HDL Language Support: VHDL and/or Verilog®
Operating System Support: Windows® XP and Vista 32/64 bit and Linux® 32/64 bit
HES™
HES (Hardware Emulation System) All-IN-One Hardware-Assisted Verification System providing
Emulation, Acceleration and Prototyping
HDL Language Support: VHDL, Verilog®, EDIF and SystemC
Operating System Support: Windows® XP and Vista 32/64 bit and Linux® 32/64 bit
www.aldec.com

4. Customers
www.aldec.com

5. A Few of our Industry
Partners
www.aldec.com

6. Active-HDL™
www.aldec.com

7. Better Performance, More
Features, Lower Price
Aldec Simulators Other RTL Simulators
 25 years in EDA Big Brand
 Comparable & Better Performance The Simulation Performance Standard
 More Features Included Feature OPTIONAL Upgrades
“Low/Minimal Upgrade Fees” Hidden Costs “Option Upgrade Fees”
 Lower License Prices
 Licensing Advantages
www.aldec.com

8. Aldec Cross-Platform
Language Support
www.aldec.com

9. Aldec Simulation Flow
www.aldec.com

10. Active-HDL
• Common-Kernel Mixed Language Simulator, support VHDL, Verilog®,
SystemVerilog (Design & Assertions), SystemC & EDIF
• HDL Design Tools: Design entry, Design Creation, Code2Graphics™, Block and
State Diagram, Waveform editor, stimulus generation, Language templates &
auto-complete, scripting, legacy design support.
• Design Flow Manager: use popular third-party tools throughout the design flow
within the same FPGA environment.
• Debugging: Code execution tracing, Waveform/Compare, Memory Viewer,
Xtrace, Advanced Dataflow and Profiler.
• Coverage: Code Coverage, Toggle & Functional Coverage.
• Additional Interfaces: DSP/HDL algorithm MATLAB® and Simulink® Interfaces
& Zuken CADSTAR PCB Design
• Assertion and Coverage(OPTION) SystemVerilog PSL & OVA support.
Dedicated Assertion viewer, coverage, breakpoint editor.
www.aldec.com

11. Active-HDL
Configurations
Features Desktop Designer Plus Expert
Master Edition Edition (PE) Edition (EE)
(DM)
VHDL IEEE 1076    
Verilog HDL IEEE 1364    
SystemVerilog IEEE 1800 (Design)    
Verilog PLI/VPI   
EDIF200  
Language Interface Wizard (PLI/VPI/VHPI/DPI)  
SystemVerilog IEEE DPI w/Wizard  
System 2.2 IEEE 1666/OSCI 2.2/TLM 2.0 Option 
MATLAB® Co-simulation Option 
Xilinx® SecureIP Support  VHDL 
Synopsys SmartModels®, SWIFT™ Interface Option 
SpringSoft® Verdi™ PSD mode Interface Option 
ALINT™ with Basic Rule Library Option 
Statement/Branch/Conditional/Toggle Coverage Option 
Waveform Viewer (AWF and ASDB)   
www.aldec.com
C++ Debugger  

12. Riviera-PROTM
www.aldec.com

13. Complete Verification Suite
• VHDL, Verilog, SystemVerilog and SystemC support.
• Assertion support (OVA, PSL, SVA, VTL).
• Transaction Level Modeling support.
• New, improved Graphical User Interface with Tcl scripting.
• Command line mode of operation.
• Advanced Debugging and Analysis (post-simulation debug, enhanced
waveform, code and functional coverage, dataflow)
• OS Platform independent library support
(Linux, including 64-bit, Windows)
• SLP-Verilog simulation provides significant performance gains
• Open IP Protection (simulation of encrypted sources)
www.aldec.com

14. Simulation Engine
Improvements
• SLP engine allowing dramatic reduction of simulation time
forVerilog RTL, gate-level and timing design descriptions.
• New VHDL Simulation Optimization algorithms.
• Improved support for SystemVerilog standard (classes, DPI,
functional coverage, etc.)
• Support for the most recent VHDL standard (IEEE Std 1076-
2008).
• Direct interface to compiled SystemC code (Native SystemC
interface), bypassing the cumbersome and slow PLI/VHPI
interfaces in mixed Verilog/VHDL/SystemC simulations.
• Riviera-PRO simulates IP encrypted with 256-bit key, such as
XILINX® Secure IP.
www.aldec.com

15. Assertion-Based
Verification
• Support of SVA, PSL and OVA assertions allows
implementation of new design verification methods:
 Easy access to all parts of design under verification (white box
verification),
 Self-checking Intellectual Property (IP),
 System protocol checkers,
 Functional coverage verifying quality of verification algorithm.
• Verification units can be specified in separate files, mixed
with HDL units in the same file, or placed in HDL file as
special comments.
www.aldec.com

16. Functional Coverage
• SystemVerilog assertions, PSL (Property Specification
Language) and OVA (Open Vera Assertion) are supported
allowing users to define sequences and properties for cover
directives for functional coverage.
• Functional Coverage results are saved to Aldec Coverage
Database (ACDB) format for easy management, restoring
and merging.
• Coverage results can be viewed directly waveform window,
as well as dedicated coverage viewer window for easy
debugging.
www.aldec.com

17. C/C++/SystemC Support
• C++ compilers, such as gcc or Microsoft® Visual C++® are
supported.
• ccomp command allows easy compilation of PLI, VHPI, DPI or
SystemC code.
• addsc command makes compiled SystemC code accessible in
Verilog or VHDL code.
• scgenmod command exports HDL module interface to a SystemC
file that allows instantiation of VHDL/Verilog in SystemC.
• Simultaneous debugging of C code and HDL code is supported in
one, common framework (no application switching required).
www.aldec.com

18. MATLAB® Co-simulation
• MATLAB® interface allows scalar and array data exchange with
MATLAB during HDL simulations in Riviera-PRO:
 To generate complicated stimulus in a testbench,
 To describe functionality of some design units at a high level of
abstraction,
 To post-process simulation data (e.g. compute Fast Fourier
Transform of the DSP block output),
 To visualize simulation data (statistical analysis, spectral analysis,
etc.)
• Extensive set of procedures and functions supporting this
interface is available in VHDL and Verilog.
www.aldec.com

19. Riviera-PRO
Configurations
Features AHDL-EE LV LVT LVT-SV
VHDL IEEE 1076    
Verilog HDL IEEE 1364    
SystemVerilog IEEE 1800 (Design)    
System 2.2 IEEE 1666/OSCI 2.2/TLM 2.0   
SystemVerilog IEEE 1800-2005 (Assertions)  
SystemVerilog IEEE 1800 (Verification) 
Verilog Programming Language Interfaces (PLI/VPI)    
MATLAB® Co-simulation    
Xilinx® SecureIP Support  VHDL  
Synopsys SmartModels®, SWIFT™ Interface   
SpringSoft® Verdi™ PSD mode Interface   
ALINT™ with Basic Rule Library   
Profiler (Performance Metrics)  
SFM (Server Farm Manager) Option 
Statement/Branch/Conditional/Toggle Coverage   
Integrated Source Level C/SystemC Debugger  
Linux x86/x86_64 x86  
www.aldec.com

20. ALINT™
www.aldec.com

21. Enhanced Plug-ins Rules
• Aldec (basic plug-in)
 ALDEC_VHDL
 ALDEC_VLOG
• STARC (best industry practices by Semiconductor Technology
Academic Research Center, Japan)
 STARC_VHDL
 STARC_VLOG
• DO-254/ED-80 (special for safety critical avionics designs)
 DO254_VHDL
 DO254_VLOG
www.aldec.com

22. ALINT™
• New rules in existing plug-ins (ALDEC, STARC, DO-254).
• New optional plug-in for RMM (Reuse Methodology Manual)
• Extended support for FPGA Vendor Primitives (Altera, Xilinx).
• Enhanced linting engine (CDC, TestBench features).
• New productivity tools in GUI (wizards, design quality reports).
• Number of corrections and bug fixes.
www.aldec.com

23. HES
Hardware Emulation System
www.aldec.com

24. HES Environment
www.aldec.com

25. HES Ecosystem
www.aldec.com

26. Hardware Supported
DINI
DN8000K10
• Off-the-shelf FPGA boards capacity up to:
24M ASIC gates
 High speed prototyping
 High capacity DINI
DN9000K10PCI
capacity up to:
• Immediate Advantages 10M ASIC
gates
 Reuse for acceleration
 Reuse for emulation ALDEC
 Better Return on Assets HES5XLX660E
X
 Reduces capital spending capacity up to:
4M ASIC gates
www.aldec.com

27. HES Interfaces
• Acceleration
 Direct link to Aldec simulators kernel
 PLI interfaces for 3rd party simulators
 SystemC/C++ bit-level, cycle accurate
• Emulation
 SCE-MI for transaction level testbenches
 SystemC/C/C++ for virtual modeling
 Vector based interface for bit level emulation
• Prototyping
 C/C++ to connect virtual models and high-level testbenches
www.aldec.com

28. Design Verification
Manager (DVM) Features
 Multi-HDL support (Verilog, SystemVerilog,
VHDL, SystemC, C/C++)
 Static and Dynamic debug options
 Supports excluding instances from hardware
by using Black-Box feature
 Incremental and block design synthesis
 Automatic ASIC clock conversion to
FPGA
 Automatic partitioning and multiplexing of
interconnections
 FPGA implementation flow management
 Console mode for scripting (TCL)
 Seamless integration with all HDL simulators
(PLI, VHPI, etc.);
 direct link with the Aldec simulator kernel
(performance!)
 HES-API available for C-testbench
 SDRAM, DDR and other external memories
www.aldec.com support

29. Transaction-Level
SCE-MI Emulation
UTC Model
Message Port
Proxy 1 Message Transactor 1 DUT
Port 1
UTC Model Message Port
Proxy 2
RTC Model Message Port Message
Proxy 3 Port 2 Transactor 2
UTC Model SCE-MI Infrastructure Message
Port 1
Clock/Reset
Generation
and Control
C/C++ kernel
such as SystemC
Software Side (host workstation) Hardware Side (emulator)
The picture is taken fromSCE-MI Reference Manual version 2.0
www.aldec.com

30. DVM Configurations
Features Pototyping Acceleration Emulation
(Proto) (Xcell) (Elite)
Design Verification Manger [DVM™]   
Automatic Design Partitioning w/ LVDS Signal Multiplexing  
Blackbox Functionality (Excludes modules)  
Static Debugging Probes   
Static Debugging Probes w/ Xilinx ChipScope™ Pro  
Static Debugging Probes w/ Aldec LA (ALA for SCE-MI) 
Dynamic Probes (for SCE-MI) 
Clock Conversion and Analysis  
Memory Model Mapping (maps to on-board memory)  
Prototyping API and function library (interface with C++)  
HDL Co-Simulator Interface (Aldec/CDNS/MG/SNPS)  
SCE-MI 2.0 HW/SW Infrastructure (SCE-MI C++ API) 
C/C++/SC Testbench Wrapper  
OVL Assertions Support 
Vector Based Emulation 
Multi-FPGA Boards Support Option Option 
www.aldec.com