The document discusses various HDL simulators including both commercial and open-source options. It provides details on the languages supported, features, and usage of simulators such as Xilinx ISE Simulator, ModelSim, QuestaSim, Quartus II Simulator, VCS, Icarus Verilog, and Verilator. It also provides commands for compiling, simulating, and viewing waveforms for some open-source simulators.

1. HDL SIMULATORS

2. • ISE Simulator-Xilinx
• Languages Supported:VHDL-93, V2001
• Xilinx ISE (Integrated Synthesis Environment) is a
software tool produced by Xilinx for synthesis and
analysis of HDLdesigns,to synthesize ("compile")
their designs, perform timing analysis,
examine RTL diagrams, simulate a design's
reaction to different stimuli, and configure the
target device with the programmer.

3. • Xilinx officially supports Microsoft
Windows, Red Hat Enterprise 4, 5, & 6
Workstations and SUSE Linux Enterprise
11.Certain other GNU/Linux distributions can
run Xilinx ISE WebPack with some modifica-
tions or configurations, including Gentoo
Linux, Arch Linux.

4. • System-level testing may be performed with
ISIM or the ModelSim logic simulator, and
such test programs must also be written in
HDL languages.Test bench programs may
include simulated input signal waveforms, or
monitors which observe and verify the
outputs of the device under test.

5. • ModelSim or ISIM may be used to perform the
following types of simulations:
• Logical verification, to ensure the module
produces expected results
• Behavioural verification, to verify logical and
timing issues
• Post-place & route simulation, to verify
behaviour after placement of the module
within the reconfigurable logic of the FPGA

6. • Active-HDL/Riviera-PRO-Aldec
• Languages Supported:VHDL-1987,-1993,-2002,-
2008,V1995,V2001,V2005,SV2009.
• Riviera-PRO enables the ultimate testbench
productivity, reusability, and automation by
combining the high-performance simulation
engine, advanced debugging capabilities at
different levels of abstraction, and support for
the latest Language and Verification Library
Standards.

7. • Incisive Enterprise Simulator -Cadence Design
Systems.
• Languages Supported:VHDL-2002, V2001,
SV2009.

8. • Incisive Enterprise Simulator supports all IEEE-
standard languages, the Open Verification
Methodology (OVM), Accellera’s Universal
Verification Methodology (UVM), and
the e Reuse Methodology (eRM), making it
quick and easy to integrate with your
established verification flows.

9. • We can extend the functionality of the Incisive
Enterprise Simulator with our Virtual System
Platform, which provides a high-throughput
channel between the testbench and the
device under test (DUT). This enables
automated metric-driven verification of
embedded software exactly as if it were
another part of the DUT.

10. • Code coverage – Supports Verilog,
SystemVerilog, VHDL, and mixed-language
designs – Automatic finite state machine
extraction – Coverage attributes supported
include blocks, paths, expressions, variables,
gates, FSM (states, sequences), and toggle.
• Tcl scripting for custom analysis.

11. • ModelSim and Questa- Mentor Graphics
• Languages Supported:VHDL-1987,-1993,-
2002,-2008, V2001, SV2005, SV2009, SV2012.
• ModelSim is a hardware simulation and debug
environment primarily targeted at smaller
ASIC and FPGA design.

12. • One of the main differences between QuestaSim
and Modelsim (besides performance/capacity) is
that QuestaSim is the simulation engine for the
Questa Platform which includes integration of
Verification Management, Formal based
technologies, Questa Verification IP, Low Power
Simulation and Accelerated Coverage Closure
technologies.
• QuestaSim natively supports SystemVerilog for
Testbench, UPF, UCIS, OVM/UVM where
ModelSim does not.

13. • MPSim-Axiom Design Automation
• Languages Supported:V2001, V2005, SV2005,
SV2009.
• PureSpeed-Frontline
• Languages Supportde:V1995

14. • It is the first Verilog simulator available on the
Windows OS. The simulator had a cycle-based
counterpart called 'CycleDrive'. FrontLine was
sold to Avant! in 1998, which was later
acquired by Synopsys in 2002. Synopsys
discontinued Purespeed after established VCS
simulator.

15. • Quartus II Simulator (Qsim)-Altera.
• Languages Supported:VHDL-1993, V2001,
SV2005.
• Altera Quartus II is programmable logic
device design software produced by Altera.
Quartus II enables analysis and synthesis
of HDL designs, which enables the developer
to compile their designs, perform timing
analysis, examine RTL diagrams.

16. • SOPC Builder, a tool in Quartus II software that
eliminates manual system integration tasks by
automatically generating interconnect logic and
creating a testbench to verify functionality.
• SOPC Builder (System on a Programmable Chip
Builder) is software made by Altera that
automates connecting soft-hardware
components to create a complete computer
system that runs on any of its various FPGA chips.

17. • Speedsim, Verilog-XL-Cadence Design System
• Languages Supported:V1995
• Verilog XL is the first verilog simulator to be
qualified for asic validation sign off.

18. • VCS –Synopsys
• Languages Supported:VHDL-1987,-1993,-
2002,-2008, V2001, SV2005, SV2009, SV2012
• It also supports UVM,OVM,VMM and system
C.
• VCS also uses VirSim, which is a graphical user
interface to VCS used for debugging and
viewing the waveforms.

19. • Vivado Simulator-Xilinx
• Languages Supported: VHDL-93, 2008,V2001
• Vivado Simulator is a hardware description language
(HDL) event-driven simulator that supports behavioral
and timing simulation for single language and mixed
language designs.
• Feature highlights:
• SystemVerilog
• Switching Activity Interchange Format (SAIF) for power
analysis
• Value Change Dump (VCD) support

20. • Other commercial simulators are
• CVC-Tachyon Design Automation:v95,
• SILOS-Silvaco:v95,
• SMASH-Dolphin Integration:V1995, V2001,
VHDL-1993.

21. Free and open-source simulators
• GPL Cver- it is a open-source simulator.This
simulator is not fully IEEE 1364-2001
compliant. It does not support generate and
constant functions.
• Icarus Verilog- V1995, V2001, limited
V2005/V2009.
• LIFTING , OSS CVC ,TkGate, Verilator, Verilog
Behavioral Simulator (VBS), VeriWell.

22. • LIFTING (LIRMM Fault Simulator), an open-
source simulator able to perform both logic
and fault simulations for single/multiple stuck-
at faults.
• VERILATOR- Verilator compiles Verilog into
C++.
• verilator –lint-only –f input.vc top.v

23. • Icarus Verilog is a Verilog simulation and
synthesis tool. It operates as a compiler,
compiling source code written in Verilog (IEEE-
1364) into some target format.
• Icarus Verilog is Supported OS such
as Linux, FreeBSD, OpenSolaris, AIX, Microsoft
Windows, and Mac OS X.

24. • Create a file using command- gvim filename.v
• Compile the file using-iverilog filename.v
• Execution can be done by- ./a.out
• Create the testbench-gvim filename.v
• Run the following command to include file.
• iverilog -o filename for run.vvp counter_tb.v
counter.v
• "-o" flag tells the compiler where to place the
compiled result.

25. • The vvp target generates code for the vvp
runtime. The output is a complete program that
simulates the design but must be run by
the vvp command.
• The "iverilog" command is the compiler, and the
"vvp" command is the simulation runtime engine.
• After creating new file for run.run the file by
using : vvp filename for run.vvp
• To generate waveform use command:
Gtkwave filename for run.vcd

26. • Initial
begin
$dumpfile("test.vcd");
$dumpvars(1,test);
end
$dumpfile directive to create a file that contains
the dumped waveforms. Use the $dumpvars
directive to define the scope of the dump.