Transport triggered architecture
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Transport triggered architecture uses function units, a control unit, and register files connected by transport buses and sockets. Each function unit implements operations like addition or user-defined computations. The control unit fetches and executes instructions from instruction memory. Register files store variables. Data and instructions are transferred between components through the transport buses and sockets.
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WHAT ARE THE SECURITY VIOLATION CATEGORIES?
1. Breach of confidentiality: unauthorized reading of data.
2. Breach of integrity: unauthorized modification of data.
3. Breach of availability: unauthorized destruction of data.
4. Theft of service: unauthorized use of resources.
5. Denial of Service(DOS): Prevention of legitimate use.
WHAT ARE THE SECURITY VIOLATION METHODS?
1. Masquerading (authentication breach): pretending to be an authorized user.
2. Replay Attack: Replaying the same message or adding a modification to it.
3. Man-in-the-middle attack: intruder sits in data flow, masquerading as sender to receiver and vice versa.
4. Session hijacking: intercepting a session which is already on going to by-pass authentication.
5. Privilege escalation: A really Common attack, access of resources that a user is not supposed to have.
WHAT ARE THE OTHER VARIATIONS OF HYPERVISORS?
1. Paravirtualization: guest OS is modified to work with VMM.
2. Programming-environment virtualization: VMMS do not virtualize hardware which creates optimized virtual system (Used by Oracle Java and Microsoft.Net).
3. Emulators: Allows applications written for one hardware to run on different hardware environments.
4. Application Containment: Not virtualization but, provides features like it by segregating application making them more secure and manageable.
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• Much variation is due to breadth, depth, and importance of virtualization.
WHAT ARE THE STEPS OF LIVE MIGRATION?
1. VMM start connection with the target VMM.
2. Target created a new guest (by creating a new VCPU).
3. VMM sends read-only files to target VMM.
4. VMM sends read-write files to target VMM.
5. Repeat 4 unit done as not all read-write data can be sent (could be a dirty read).
6. If step 4 and 5 becomes very short then, VMM freezes guest, send remaining stuff.
7. Target starts running the freezed guest.
WHAT ARE THE REASONS FOR DISTRIBUTED SYSTEMS?
1. Resource sharing
Sharing files, information, printing.
Using remote GPUs.
2. Computation speedup
dsitribute processing needed to multicomputers.
Load balancing: moving jobs to more lightly-laoded sites.
3. Reliability: detect and recover failurs.
WHAT ARE THE WIDELY USED ARCHITECTURES?
1. Client-server model.
2. Cluster-based model.
WHAT ARE THE CHALLENGES?
1. Naming and transparency.
2. Remote file access.
3. Caching and caching consistency.
WHAT WAS GFS WAS INFLUNECNED BY?
1. Hardware failure should be expected routinely.
2. Most files are changed by appending new data (rather than overwriting existing data).
3. Modularized software layer MapReduce sit on top of GFS to carry out large-scale parallel computations.
WHAT ARE THE ADVANTAGES OF DISK CACHES?
1. Reliable
2. Cached data kept on disk do not need to be fetched again while recovery.
ADVANTAGES OF MAIN MEMORY CACHES?
1. Can make workstations diskless.
2. Quicker data access.
3. Performance speed up in bigger memories.
4. Server c
Understanding open max il
The document provides an overview of OpenMAX-IL (OpenMAX Integrated Layer), which is a royalty-free, cross-platform API for accelerated multimedia components. It defines OpenMAX-IL entities like components, ports, and the core. Components have input/output ports and support non-tunneled or tunneled communication. The document describes component states, buffer handling, simple usage including tunnel setup, and state transitions for OpenMAX-IL.
Processor Organization and Architecture
This document discusses processor organization and architecture. It covers the stored program concept where both instructions and data are stored in memory. It describes the Von Neumann architecture, which includes a main memory, ALU, control unit, and I/O. It discusses the registers used in processor control and execution like the program counter, accumulator, and instruction register. Finally, it examines addressing modes like immediate, direct, indirect, register, displacement, and stack addressing.
I/o management and disk scheduling .pptx
This document provides an overview of I/O management and disk scheduling in operating systems. It begins with an introduction to different categories of I/O devices and how they vary. It then covers techniques for performing I/O like programmed I/O, interrupt-driven I/O, and direct memory access. The document discusses the evolution of the I/O function and a hierarchical model for organizing I/O. It also outlines concepts like I/O buffering, disk scheduling parameters, RAID levels, and disk caching.
SUDHARSAN.V.pptx
The document summarizes the key components of a processor's organization:
- The control unit directs input/output flow and instruction execution.
- The arithmetic logic unit (ALU) performs calculations and logical operations.
- Main memory units include registers like the accumulator, program counter, and memory address/data registers that store instructions and data.
- Buses transmit data between components like the data bus and address bus.
- The datapath performs microoperations by transferring data between registers through the ALU and includes additional components like multiplexers and a barrel shifter.
Ch 7 io_management & disk scheduling
This document discusses input/output (I/O) management and disk scheduling. It begins by categorizing I/O devices as those for communicating with users, electronic equipment, and remote devices. It then describes how I/O devices differ in data rates, applications, control complexity, data transfer units, data representation, and error handling. The document outlines three I/O techniques - programmed I/O, interrupt-driven I/O, and direct memory access (DMA). It also discusses the evolution of I/O architectures and covers I/O buffering, disk organization, and disk terminology.
ch1.pptx
The document provides an overview of computer organization and architecture. It discusses that computer architecture focuses on the logical structure and behavior of a computer system, while computer organization deals with the physical implementation and operational attributes. The document also outlines the evolution of computers from early vacuum tube-based systems to modern multicore processors, noting increased processing speed, smaller component sizes, and larger memory capacities over time. It describes the classic Von Neumann architecture with separate memory and processing units, and how this basic structure is still prevalent in modern systems.
06_1_design_flow.ppt
The document discusses computation flow for reconfigurable systems at both run-time and compile-time. It may be necessary to iterate some steps for certain applications. Synchronization is usually used between the processor and reconfigurable device (RD), and blocking access is used for memory access. Devices like Xilinx FPGAs feature soft or hard processors that allow complete system integration. Reconfiguration can be full, reconfiguring the entire device, or partial, reconfiguring only a part of the device. The document also discusses design flows, placement and routing challenges, and references reconfigurable computing architectures.
Tsfpga
This document discusses the Matrix, TSFPGA, and DPGA architectures. Matrix is based on an array of identical primitive elements with a configurable interconnect network. It operates in a pipelined fashion. TSFPGA moves the value registers to the inputs of computational elements, allowing values to move between producer and consumer with minimum transit time independent of when the consumer will use the data. It uses input registers and broadcasts the current timestep so inputs can load values when their programmed load time matches. The basic building block of TSFPGA is the subarray tile containing LUTs and a central crossbar for switching.
UNIT 2.pptx
The document discusses the features and architecture of the Pentium processor, including that it is a 32-bit superscalar microprocessor introduced in 1993 containing over 3 million transistors. It has separate 8KB caches for instructions and data and executes instructions through five pipeline stages, allowing for simultaneous execution of multiple instructions. The Pentium uses a superscalar architecture with two integer pipelines (U-pipe and V-pipe) that can concurrently execute independent instructions to improve performance.
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The document summarizes the basic design of Kerberos, an authentication system used to verify users on a network. It describes the key components - the Authentication Server (AS), Ticket Granting Server (TGS), File Server (FS), and client. It outlines the basic process where the AS verifies the client's identity and issues tickets allowing access to other services like the TGS and FS. The TGS and FS then use the tickets and session keys to further authenticate the client before granting access to resources.
Network security
1. Formulate a testing plan with the client to identify systems to evaluate and the scope of testing allowed.
2. Remotely or locally access the target systems to find vulnerabilities by simulating common attacks.
3. Report any found vulnerabilities to the client along with recommendations on how to remedy security issues.
Os module 2 d
The document discusses deadlocks in computer systems and various approaches to handling them. It defines deadlock as when a set of processes are blocked waiting for resources held by each other in a cyclic manner. There are four conditions required for deadlock: mutual exclusion, hold and wait, no preemption, and circular wait. Methods to handle deadlocks include ignoring the problem, preventing deadlocks through design restrictions, avoiding deadlocks by dynamically checking for safety, and detecting and recovering from deadlocks after the fact. The banker's algorithm is presented as an avoidance technique using a resource allocation graph and safety checks.
Os module 2 c
This document discusses mechanisms for ensuring orderly execution of concurrent processes that share resources. It describes the concept of concurrency with multiple simultaneous processes and the need for synchronization. Atomic operations are introduced to prevent race conditions when processes update shared variables concurrently. The critical section problem is defined, where processes need exclusive access to shared resources. Three requirements for the solution are given: mutual exclusion, progress, and bounded waiting. Several solutions for synchronization between two processes using shared variables are presented and evaluated against the requirements.
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Vector processing involves executing the same operation on multiple data elements simultaneously using a single instruction. Early implementations like the CDC Cyber 100 had limitations. The Cray-1 was the first successful vector processing supercomputer, using vector registers to perform calculations faster than requiring memory access. Seymour Cray led the development of vector processing machines that dominated the field for many years. While vector processing is no longer a focus, its principles are still used today in multimedia SIMD instructions.
Lec 3
This document discusses caching techniques used in computer architecture to reduce the latency gap between processors and memory. It covers cache organization, operation, write policies, replacement policies, multi-level caches, prefetching, and multi-ported caches. The goal of caching is to exploit locality in memory access patterns to keep frequently used data closer to the processor.
Lec2 final
Systolic arrays are arrangements of processors where data flows synchronously between neighboring processors. Each processor receives data from neighbors, processes it, and outputs results to opposite neighbors. This allows certain problems to be solved much more efficiently, such as reducing the n-body problem from n^2 to n time. Matrix multiplication can also be performed in linear rather than cubic time using a systolic array. While powerful for specific applications, systolic arrays are also expensive and specialized, and not needed for most problems.
Lec1 final
Superscalar and VLIW architectures can exploit instruction-level parallelism (ILP) by processing multiple instructions simultaneously. There are two main approaches: superscalar processors fetch and execute independent instructions in parallel using dependency checking, while very long instruction word (VLIW) architectures rely on compilers to group independent instructions into single long instructions. List scheduling and trace scheduling are algorithms used to schedule instructions for ILP. Trace scheduling works by identifying common code traces and scheduling basic blocks within the trace together.
Module 3 law of contracts
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1. The four essential requisites of an obligation are a passive subject, active subject, object or presentation, and a juridical tie.
2. Obligations can arise from law, contracts, quasi-contracts, delicts or crimes. Contracts require consent, a certain object, and cause or consideration.
3. A contract is a meeting of minds where one party binds themselves to give something or render a service to the other party. Contracts must not be unlawful or violate public policy.
Subnetting
Subnets divide a network into smaller sub-networks or subnets. Each subnet is treated as a separate network and can be further divided. When a packet enters a network with subnets, routers will route based on the subnet ID which is a combination of the network ID and subnet portion of the IP address. Subnets are only relevant for routing within an organization and are transparent outside the organization.
Os module 2 c
The document discusses mechanisms for ensuring orderly execution of concurrent processes that share a logical address space. It describes concepts like concurrency, atomic operations, race conditions, and the critical section problem. It presents solutions to the critical section problem like mutual exclusion, progress, and bounded waiting. Algorithms like Peterson's and Dekker's are discussed for solving mutual exclusion between two processes. The use of semaphores as a synchronization tool that avoids busy waiting is also covered.
Os module 2 ba
The document discusses different scheduling algorithms used by operating systems. It begins by explaining that the scheduler decides which process to activate from the ready queue when multiple processes are runnable. There are long-term, medium-term, and short-term schedulers that control admission of jobs, memory allocation, and CPU sharing respectively. The goal of scheduling is to optimize system performance and resource utilization while providing responsive service. Common algorithms include first-come first-served (FCFS), shortest job first (SJF), priority scheduling, and round-robin. FCFS schedules processes in the order of arrival while SJF selects the shortest job first. Priority scheduling preempts lower priority jobs.
Lec5
This chapter describes data storage technologies used in computer systems. It discusses the characteristics of primary storage, such as RAM and ROM, and secondary storage devices, including magnetic tapes, disks, and optical discs. The key aspects covered are the memory hierarchy from fastest and most expensive to slower and cheaper, as well as the technologies behind magnetic and optical storage and how they encode data through magnetic charges or light reflection respectively.
Delivery
There are four categories of messaging: unicast, multicast, broadcast, and anycast. Unicast messages are sent to a single recipient, multicast messages are sent to a group of recipients, broadcast messages are sent to all recipients on a network, and anycast messages are sent to any member of a group. LANs often use broadcast technology to implement multicast and broadcast messaging efficiently, while WAN multicast requires tunneling through networks that do not support multicast natively.
Addressing
Addressing deals with uniquely identifying the location of an entity for communication purposes. It involves a name/identifier, address, and route. Addresses allow messages to be delivered to the intended destination. IP addresses in IPv4 are 32-bit numbers that identify devices on the network. IPv6 was developed to replace IPv4 and uses 128-bit addresses to overcome the address space limitations of IPv4. A transition approach is needed to integrate IPv6 since the internet cannot be abruptly changed over.
6 spatial filtering p2
This document discusses techniques for image enhancement through spatial filtering. It begins with a refresher on spatial filtering, then discusses sharpening filters including 1st and 2nd derivative filters. The Laplacian filter is presented as a simple sharpening filter based on the 2nd derivative that highlights edges. Applying the Laplacian filter alone does not produce an enhanced image. To generate a sharpened image, the result of the Laplacian filter must be subtracted from the original image.
5 spatial filtering p1
This document discusses digital image processing and spatial filtering. It begins by explaining that spatial filtering operates on neighborhoods of pixels rather than individual pixels. It then provides examples of simple neighborhood operations like minimum, maximum, and median filters. It also shows how spatial filtering can be expressed as an equation. The document goes on to explain smoothing spatial filters, which average pixel values in a neighborhood. It provides an example of a 3x3 averaging filter and shows how it is applied to each pixel. Finally, it discusses weighted smoothing filters that give more importance to pixels closer to the center.
Medical image analysis
This document discusses various types of medical imaging technologies. It describes radiologic/x-ray technology, ultrasound technology, CT scans, MRI scans, and nuclear imaging including PET and SPECT. The goal of medical imaging is to non-invasively examine the inside of the body to diagnose health problems and guide treatment. Each technology has advantages for certain applications based on the type of information and depth of imaging it provides. Together these modalities provide physicians a variety of tools to accurately diagnose and monitor patient health issues.
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Transport triggered architecture
- 4. Structure • Function unit • Each function unit implements one or more operations, which implement functionality ranging from a simple addition of integers to a complex and arbitrary user-defined application-specific computation. Operands for operations are transferred through function unit ports. • Each function unit may have an independent pipeline. In case a function unit is fully pipelined, a new operation that takes multiple clock cycles to finish can be started in every clock cycle. On the other hand, a pipeline can be such that it does not always accept new operation start requests while an old one is still executing. • Data memory access and communication to outside of the processor is handled by using special function units. Function units that implement memory accessing operations and connect to a memory module are often called load/store units
- 6. Structure • Control unit • Control unit is a special case of function units which controls execution of programs. Control unit has access to the instruction memory in order to fetch the instructions to be executed. In order to allow the executed programs to transfer the execution (jump) to an arbitrary position in the executed program, control unit provides control flow operations. A control unit usually has an instruction pipeline, which consists of stages for fetching, decoding and executing program instructions
- 7. Control Unit
- 8. Structure • Register files • Register files contain general purpose registers, which are used to store variables in programs. Like function units, also register files have input and output ports. The number of read and write ports, that is, the capability of being able to read and write multiple registers in a same clock cycle, can vary in each register file
- 10. Structure • Transport buses and sockets • Interconnect architecture consists of transport buses which are connected to function unit ports by means of sockets. Due to expense of connectivity, it is usual to reduce the number of connections between units (function units and register files). A TTA is said to be fully connected in case there is a path from each unit output port to every unit's input ports. • Conditional execution is implemented with the aid of guards. Each data transport can be conditionalized by a guard, which is connected to a register (often a 1-bit conditional register) and to a bus. In case the value of the guarded register evaluates to false (zero), the data transport programmed for the bus the guard is connected to is squashed, that is, not written to its destination
- 11. Transport buses and sockets