central processing unit

1. CENTRAL PROCESSING UNIT
Instruction Set Architecture(ISA)
Mr. SUBHASIS DASH
SCHOLE OF COMPUTER ENGINEERING.
KIIT UNIVERSITY, BHUBANESWAR , ORISSA

2. CENTRAL PROCESSING UNIT
• Introduction
• Types of computer Organization
• Instruction Formats
• Addressing Modes
• Data Transfer and Manipulation
• Program Control

3. MAJOR COMPONENTS OF CPU
Introduction
• Storage Components
Registers
Flags
• Execution (Processing) Components
Arithmetic Logic Unit(ALU)
Arithmetic calculations, Logical computations, Shifts/Rotates
• Transfer Components
Bus
• Control Components
Control Unit Register
File ALU
Control Unit

4. PROCESSOR (COMPUTER) ORGANIZATION
• In general, most processors are organized in one of 3 ways
– Single register (Accumulator) organization
» Basic Computer is a good example
» Accumulator is the only general purpose register
– General register organization
» Used by most modern computer processors
» Any of the registers can be used as the source or destination for
computer operations
– Stack organization
» All operations are done using the hardware stack
» Example: An OR instruction will POP two top elements from stack,
do a logical OR on them, & PUSH result on stack (TOS).
COMPUTER ORGANIZATION

5. SINGLE REGISTER (ACCUMULATOR)
ORGANIZATION
• All operations are performed with an implied mode of operations.
• The instruction format in this type of computer uses one address
field.
• Ex:- ADD X
– Where X is the address of the operand.
• AC AC + M[XX]
– AC is the accumulator register.
– M[X] is the memory word located at address X.
COMPUTER ORGANIZATION

6. GENERAL REGISTER ORGANIZATION
MUXSELA
{ MUX }SELB
ALUOPR
R1
R2
R3
R4
R5
R6
R7
Input
3 x 8
decoder
SELD
Load
(7 lines)
Output
A bus B bus
Clock
COMPUTER ORGANIZATION

7. GENERAL REGISTER ORGANIZATION
OPERATION OF CONTROL UNIT
The control unit
Directs the information flow through ALU by
- Selecting various Components in the system
- Selecting the Function of ALU
Example: R1 ← R2 + R3
[1] MUX A selector (SELA): BUS A ← R2
[2] MUX B selector (SELB): BUS B ← R3
[3] ALU operation selector (OPR): ALU to ADD
[4] Decoder destination selector (SELD): R1 ← Out Bus
Control Word
Encoding of register selection fields
Control
Binary
Code SELA SELB SELD
000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7
SELA SELB SELD OPR
3 3 3 5

8. STACK (REGISTER) ORGANIZATION
Register Stack
Push, Pop operations
/* Initially, SP = 0, EMPTY = 1, FULL = 0 */
PUSH POP
Stack Organization
SP ← SP + 1 DR ← M[SP]
M[SP] ← DR SP ← SP − 1
If (SP = 0) then (FULL ← 1) If (SP = 0) then (EMPTY ← 1)
EMPTY ← 0 FULL ← 0
Stack
- Very useful feature for nested subroutines, nested interrupt services
- Also efficient for arithmetic expression evaluation
- Storage which can be accessed in LIFO
- Pointer: SP
- Only PUSH and POP operations are applicable
A
B
C
0
1
2
3
4
63
Address
FULL EMPTY
SP
DR
Flags
Stack pointer
stack
6 bits

9. STACK (MEMORY) ORGANIZATION
Stack Organization
- A portion of memory is used as a stack with a
processor register as a stack pointer
- PUSH: SP ← SP - 1
M[SP] ← DR
- POP: DR ← M[SP]
SP ← SP + 1
Memory with Program, Data,
and Stack Segments
4001
4000
3999
3998
3997
3000
Data
(operands)
Program
(instructions)
1000
PC
AR
SP
stack
Stack grows
In this direction
- Most computers do not provide hardware to check stack overflow (full
stack) or underflow (empty stack)  must be done in software

10. INSTRUCTION FORMAT
OP-code field - specifies the operation to be performed
Address field - designates memory address(es) or a processor register(s)
Mode field - determines how the address field is to be interpreted (to
get effective address or the operand)
• The number of address fields in the instruction format depends
on the internal organization of CPU.
• The three most common CPU organizations:
Instruction Format
Single accumulator organization:
ADD X /* AC ← AC + M[X] */
General register organization:
ADD R1, R2, R3 /* R1 ← R2 + R3 */
ADD R1, R2 /* R1 ← R1 + R2 */
MOV R1, R2 /* R1 ← R2 */
ADD R1, X /* R1 ← R1 + M[X] */
Stack organization:
PUSH X /* TOS ← M[X] */
ADD
• Instruction Fields

11. INSTRUCTION FORMAT
• Three-Address Instructions
• Two-Address Instructions
• One-Address Instructions
• Zero-Address Instructions
Instruction Format
MODE
Execution
OPCODE OPERAND 3 OPERAND 2 OPERAND 1
MODE
Execution
OPCODE OPERAND 2 OPERAND 1
MODE
Execution
OPCODE OPERAND 1
MODE
Execution
OPCODE

12. • Three-Address Instructions
Program to evaluate X = (A + B) * (C + D) :-
ADD R1, A, B /* R1 ← M[A] + M[B] */
ADD R2, C, D /* R2 ← M[C] + M[D] */
MUL X, R1, R2 /* M[X] ← R1 * R2 */
- Results in short programs
- Instruction becomes long (many bits)
• Two-Address Instructions
Program to evaluate X = (A + B) * (C + D) :
MOV R1, A /* R1 ← M[A] */
ADD R1, B /* R1 ← R1 + M[B] */
MOV R2, C /* R2 ← M[C] */
ADD R2, D /* R2 ← R2 + M[D] */
MUL R1, R2 /* R1 ← R1 * R2 */
MOV X, R1 /* M[X] ← R1 */
Instruction Format
THREE, AND TWO-ADDRESS INSTRUCTIONS

13. ONE, AND ZERO-ADDRESS INSTRUCTIONS
• One-Address Instructions
- Use an implied AC register for all data manipulation
- Program to evaluate X = (A + B) * (C + D) :
Instruction Format
LOAD A /* AC ← M[A] */
ADD B /* AC ← AC + M[B] */
STORE T /* M[T] ← AC */
LOAD C /* AC ← M[C] */
ADD D /* AC ← AC + M[D] */
MUL T /* AC ← AC * M[T] */
STORE X /* M[X] ← AC */
• Zero-Address Instructions
- Can be found in a stack-organized computer
- Program to evaluate X = (A + B) * (C + D) :
PUSH A /* TOS ← A */
PUSH B /* TOS ← B */
ADD /* TOS ← (A + B) */
PUSH C /* TOS ← C */
PUSH D /* TOS ← D */
ADD /* TOS ← (C + D) */
MUL /* TOS ← (C + D) * (A + B) */
POP X /* M[X] ← TOS */

14. RISC INSTRUCTION FORMAT
• RISC (Reduce instruction Set Computer) Format :-
– Instruction set of a typical RISC processor is restricted to use load
& store instruction, when communicating between memory & CPU.
– All other instructions are executed within processor register (AC)
without reference to memory.
– LOAD & STORE  have 1 memory & 1 register address.
– ALL other instructions  3 address instruction format.
– Program to evaluate X = (A + B) * (C + D)
LOAD R1, A */ R1  M[A] */
LOAD R2, B */ R2  M[B] */
LOAD R3, C */ R3  M[C] */
LOAD R4, D */ R4  M[D] */
ADD R1, R1, R2 */ R1  [R1] + [R2] */
ADD R3, R3, R4 */ R3  [R3] + [R4] */
MUL R1, R1, R3 */ R1  [R1] * [R3] */
STORE XX, R1 */ M[XX]  [R1] */
Instruction Format

15. ADDRESSING MODES
Addressing Modes
• Addressing Mode
1. Where to find operand on which operation is to be performed ???
2. Operand may be in accumulator or in memory or in registers (GPR) .
3. Now the way the operands are determine during program execution
is determine from ADDRESSING MODE of the instruction.
4. During fetch cycle addressing mode must be confirmed.
5. Addressing mode Specifies rules for interpreting or modifying the
address field of the instruction (before operand is actually
referenced).
6. Variety of addressing modes
- to give programming flexibility to the user
- to use the bits in the address field of the instruction efficiently

16. TYPES OF ADDRESSING MODES
• Implied Mode
Address of the operands are specified implicitly in the definition of the
instruction.
- No need to specify address in the instruction
- By default is use accumulator(AC) or stack pointer(SP).
- Single register (AC) {1 address} & stack organization (SP) {0 address}
- Effective Address (EA) = AC, or EA = Stack[SP]
- Examples from Basic Computer
CLA, CME, RAR, RAL, RRC,
• Immediate Mode
Instead of specifying the address of the operand, operand itself is
specified.
- No need to specify address in the instruction
- However, operand itself needs to be specified in the operand field.
- Sometimes, require more bits than the address
- Fast to acquire an operand
- Examples from Basic Computer  8085 CPU use this type
MVI A,8bit data // A  A + 8 bit data
ADI 8bit data // AC  AC + 8 bit data
Addressing Modes

17. TYPES OF ADDRESSING MODES
• Register Mode
Address specified in the instruction is the register address
- Designated operand need to be in a register which resides in CPU
- Shorter address than the memory address
- Saving address field in the instruction
- Faster to acquire an operand than the memory addressing
- EA = IR(REG) ([IR (REG)]: - Register field of IR)
- Example :- 8085 CPU use this type
MOVE A, B // A  [B]
ADD C // AC  [AC] + [C]
• Register Indirect Mode
Instruction specifies a register which contains the memory address of the
operand
- Saving instruction bits since register address is shorter than the memory
address
- Slower to acquire an operand than both the register addressing or memory
addressing
- EA = [IR(REG)] ([x]: Content of x means address of operand)
- Example :- 8085 CPU use this type
MOVE A, M[XX] // A  M[XX]
ADD M[XX] // AC  [AC] + M[XX]
LXI HL, 16 bit address // HL  16 bit address
Addressing Modes

18. TYPES OF ADDRESSING MODES
Addressing Modes
•Auto-increment or Auto-decrement Mode
When the address in the register is used to access memory, the value in
the register is incremented or decremented after or before its value use to access
memory by 1 automatically.
• Direct Address Mode
Instruction specifies the memory address which can be used directly to
access the memory.
- Faster than the other memory addressing modes
- Too many bits are needed to specify address for large physical memory space.
- EA = IR(address) // [(IR(address):- address field of IR)]
- Examples :- LDA 16 bit address // [AC]  [content of address]
STA 16 bit address // [Memory of address]  [AC]
• Indirect Addressing Mode
The address field of an instruction specifies the address of a memory location
that contains the address of the operand.
- Slow to acquire an operand because of an additional memory access
- EA = M[IREG(address)] // (IR(address):- M[IREG(address)]
- Example :- ADD M[300] // AC  [AC] + M[300[1350]]

19. TYPES OF ADDRESSING MODES
Addressing Modes
• Displacement (offset) Addressing Modes
The Address fields of an instruction specifies the part of the address
(address part + register content) which can be used along with a
designated registers like PC, index or base to calculate the address of
the operand.
- Address field of the instruction is short
- Large physical memory can be accessed with a small number of
address bits
- EA = f(IR(address), R), R is sometimes implied
3 different Relative Addressing Modes depending on R;
* PC Relative Addressing Mode ( Relative Register is = PC)
- EA = PC + IR(address)
* Indexed Addressing Mode (Reg. = IX, where IX: Index Register)
- EA = IX + IR(address)
* Base Register Addressing Mode
(Reg. = BAR, where BAR: Base Address Register)
- EA = BAR + IR(address)

20. ADDRESSING MODES - EXAMPLES -
Addressing Modes
Direct address 500 /* AC ← (500) */ 800
Immediate - /* AC ← 500 */ 500
Indirect address 800 /* AC ← ((500)) */ 300
Relative address 702 /* AC ← (PC+500) */ 325
Indexed address 600 /* AC ← (IX+500) */ 900
Register - /* AC ← R1 */ 400
Register indirect 400 /* AC ← (R1) */ 700
Autoincrement 400 /* AC ← (R1)+ */ 700
Autodecrement 399 /* AC ← -(R) */ 450
Load to AC Mode
Address = 500
Next instruction
200
201
202
399
400
450
700
500 800
600 900
702 325
800 300
MemoryAddress
PC = 200
R1 = 400
IX = 100
AC
Addressing
Mode
Effective
Address
Content
of AC

21. INSTRUCTION COMPLETENESS
• Most of the computer instructions can be classified
into 3 category:-
1. Data transfer instructions
2. Data manipulation instructions
3. Program Control instructions
• Data transfer instructions
– It moves data from one place in the computer to another without
changing the data content.
– Transfer happens between memory & processor register
processor register & I/O register
processor register & GPR

22. DATA TRANSFER INSTRUCTIONS
Load LD Transfer from memory to processor register.
Store ST Transfer from processor register to memory.
Move MOV Transfer from processor register to memory.
Transfer from memory to memory.
Transfer from processor register to GPR.
Exchange XCH Swap data between two registers.
Swap data between two registers.
Input IN Transfer data between processor register &
input terminal.
Output OUT Transfer data between processor register &
output terminal.
Push PUSH Transfer data between processor register &
memory stack.
Pop POP
Name Mnemonic
• Typical Data Transfer Instructions
Data Transfer and Manipulation
Function

23. DATA MANIPULATION INSTRUCTIONS
• Three Basic Types: Arithmetic instructions
Logical and bit manipulation instructions
Shift instructions
• Arithmetic Instructions
Data Transfer and Manipulation
Name Mnemonic Function
Increment INC Increment register value by 1.
Decrement DEC Decrement register value by 1.
Add ADD Operation will be performed
Subtract SUB over operand.
Multiply MUL
Divide DIV
Add with Carry ADDC Add both operands & value of
carry bit from previous
computation.
Subtract with Borrow SUBB Subtract two operands &
borrow which may be resulted
from previous computation.
Negate(2’s Complement) NEG 2’s complement of the operand.

24. DATA MANIPULATION INSTRUCTIONS
Clear CLR Specified operand to be replaced by 0’
Complement COM Produce 1’s complement of the operand.
AND AND X * 1 = X & X* 0 = 0 [Mask] [used for clear bits]
OR OR X + 1 = 1 & X + 0 = X [used for set bits]
Exclusive-OR XOR X + 1 = X’ & X + 0 = X [Complement the bits]
Clear carry CLRC Clear the carry bit.
Set carry SETC Set the carry bit.
Complement carry COMC Complement the carry bit.
Enable interrupt EI Enable the interrupt bit.
Disable interrupt DI Disable the interrupt bit.
Name Mnemonic
• Logical and Bit Manipulation Instructions
Data Transfer and Manipulation
Function

25. Logic Operations
• AND, OR, XOR
• Masking, Selective set bits & complement
the bits.
11111010
10101010OR
11110000
01010101
10101010XOR
11111111
00001010
10101010AND
00001111
10001010
10101010AND
11011111
Data Transfer and Manipulation

26. DATA MANIPULATION INSTRUCTIONS
• Logical Shift Operation
Data Transfer and Manipulation
Logical shift right SHR
Logical shift left SHL
Arithmetic shift right SHRA
Arithmetic shift left SHLA
Rotate right ROR
Rotate left ROL
Rotate right thru carry RORC
Rotate left thru carry ROLC
Name Mnemonic
 Shifts are operations which the bits of a operand are moved to the left
or right.
LOGICAL SHIFT OPERATION
 Insert 0 to the end bit position,
if the end bit position is left most
then it is a right shift operation &
if the end bit position is right most
then it is a left shift operation.
Example:-
 0 inserted to right
0 inserted to left

27. LOGICAL SHIFT
Shift Microoperations
• In a logical shift the serial input to the shift is a 0.
• A right logical shift operation:
• A left logical shift operation:
• In a Register Transfer Language, the following notation is used
– shl for a logical shift left
– shr for a logical shift right
– Examples:
» R2 ← shr R2
» R3 ← shl R3
0
0

28. ARITHMETIC SHIFT Shift Microoperations
• An arithmetic shift is meant for signed binary numbers (integer).
• An arithmetic left shift
– This instruction is just a synonym for SHL.
– multiplies a signed number by two
– Insert a o to the right most bit & shift each bit to left.
– If the Rn-1 & Rn-2 bits are differs then overflow occurred and stored in flag bit Vs
• An arithmetic right shift
– Preserved the sign bit in left most position.
– Sign bit is shifted to the right together with the rest of the bits but the sign bit
remains unchanged.
– divides a signed number by two
0
sign
bit
sign
bit

29. ARITHMETIC SHIFT
Shift Microoperations
• An left arithmetic shift operation must be checked for the
overflow
0
V
Before the shift, if the leftmost two
bits differ, the shift will result in an
overflow
• In a RTL, the following notation is used
– SHLA for an arithmetic shift left
– SHRA for an arithmetic shift right
– Examples:
» R2 ← SHRA R2
» R3 ← SHLA R3
sign
bit
Rn-1
Rn-2

30. ARITHMETIC SHIFT EXAMPLE
Shift Microoperations
• An arithmetic left shift
+5  0 0101
0 1010  IN ‘0’
0
sign
bit
+10  0 1010
1 0100  IN
‘0’
Here Rn-1 & Rn-2 differs
0 + 1 = 1  VS
-5  1 0101
1010  1’s complement
+ 1
11011  2’s complement
10110  in ‘0’
1001  1’s complement
+ 1
1010  2’s complement
Here Rn-1 & Rn-2 not differs
1 + 1 = 0  VS

31. ARITHMETIC SHIFT EXAMPLE Shift Microoperations
• An arithmetic right shift
sign
bit
+10 0 1010  last bit discarded
0 0101
-10 1 1010
0101  1’s complement
+ 1
1 0110  2’s complement & discarded the last bit
1 1011
0100  1’s complement
+ 1
1 0101

32. CIRCULAR (ROTATE) SHIFT
Shift Microoperations
• In a circular shift the serial input is the bit that is shifted out
of the other end of the register. (No loss of bits.)
• A right circular shift operation:
• A left circular shift operation:
• In a RTL, the following notation is used
– ROL for a circular/rotate shift left
– ROR for a circular/rotate shift right
– Examples:
» R2 ← ROR R2
» R3 ← ROL R3
Serial input
Serial outputserial input
Serial output
Example:-
1001
ROR 1100
0011 ROL

33. ROTATE THROUGH CARRY Shift Microoperations
• In a rotate through carry, the carry bit as an extension of the register
whose word is being rotated.
• A rotate right through carry operation:
– Instruction transfers the carry bit in to left most bit position of the register,
transfer the right most bit position to carry bit & at the same time shift the
entire register to right.
• A rotate left through carry operation:
– Instruction transfers the carry bit in to right most bit position of the register,
transfer the left most bit position to carry bit & at the same time shift the
entire register to left.
• In a RTL, the following notation is used
– ROLC for a circular/rotate left through carry
– RORC for a circular/rotate right through carry.
– Examples:
» R2 ← RORC R2
» R3 ← ROLC R3
carry
carry
EXAMPLE:-
C=1 1010
RORC  C=0 1101
C=1 0101  ROLC

34. FLAG, PROCESSOR STATUS WORD
• In Basic Computer, the processor had several (status) flags – 1 bit
value that indicated various information about the processor’s
state – E, FGI, FGO, I, IEN, R
• In some processors, flags like these are often combined into a
register – the processor status register (PSR); sometimes called a
processor status word (PSW)
• Common flags in PSW are
– C (Carry): Set to 1 if the carry out of the ALU is 1
– S (Sign): The MSB bit of the ALU’s output
– Z (Zero): Set to 1 if the ALU’s output is all 0’s
– V (Overflow): Set to 1 if there is an overflow
Status Flag Circuit
c7
c8
A B
8 8
8-bit ALU
V Z S C
F7
F7 - F0
8
F
Check for
zero output

35. PROGRAM CONTROL INSTRUCTIONS
Program Control
PC
+1
In-Line Sequencing (Next instruction is fetched
from the next adjacent location in the memory)
Address from other source; Current Instruction,
Stack, etc; Branch, Conditional Branch,
Subroutine, etc
• Program Control Instructions
Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Call CALL
Return RTN
Compare(by − ) CMP
Test(by AND) TST

36. CONDITIONAL BRANCH INSTRUCTIONS
BZ Branch if zero Z = 1
BNZ Branch if not zero Z = 0
BC Branch if carry C = 1
BNC Branch if no carry C = 0
BP Branch if plus S = 0
BM Branch if minus S = 1
BV Branch if overflow V = 1
BNV Branch if no overflow V = 0
BHI Branch if higher A > B
BHE Branch if higher or equal A ≥ B
BLO Branch if lower A < B
BLOE Branch if lower or equal A ≤ B
BE Branch if equal A = B
BNE Branch if not equal A ≠ B
BGT Branch if greater than A > B
BGE Branch if greater or equal A ≥ B
BLT Branch if less than A < B
BLE Branch if less or equal A ≤ B
BE Branch if equal A = B
BNE Branch if not equal A ≠ B
Unsigned compare conditions (A - B)
Signed compare conditions (A - B)
Mnemonic Branch condition Tested condition
Program Control

37. SUBROUTINE CALL AND RETURN
Call subroutine
Jump to subroutine
Branch to subroutine
Branch and save return address
Program Control
• Subroutine Call
 Two Most Important Operations Subroutine Call:-
* Branch to the beginning of the Subroutine
- Same as the Branch or Conditional Branch
* Save the Return Address (Address of next instruction available in PC
stored in temporary location, so subroutine knows where to return)
 Return from Subroutine
 Locations for storing Return Address
Fixed Location in the subroutine (Memory)
Fixed Location in memory
In a processor Register
In memory stack
Most efficient way
CALL
SP ← SP - 1
M[SP] ← PC
PC ← EA
RTN
PC ← M[SP]
SP ← SP +
1

38. Program-Controlled I/O Example
- Registers
- Flags
- Device interface
DATAIN DATAOUT
SIN SOUT
Ke yboard Display
Bus
Bus connection for processor keyboard, and display.
Processor

39. PROGRAM INTERRUPT
Types of Interrupts
External interrupts
External Interrupts initiated from the outside of CPU and Memory
- I/O Device → Data transfer request or Data transfer complete
- Timing Device → Timeout
- Power Failure
- Operator
Internal interrupts (TRAP)
Internal Interrupts are caused by the currently running program
- Register, Stack Overflow
- Divide by zero
- OP-code Violation
- Protection Violation
Software Interrupts
Both External and Internal Interrupts are initiated by the computer HW.
Software Interrupts are initiated by the executing an instruction.
- Supervisor Call → Switching from a user mode to the supervisor mode
→ Allows to execute a certain class of operations
which are not allowed in the user mode
Program Control

40. INTERRUPT PROCEDURE
- The interrupt is usually initiated by an internal or an external signal
rather than from the execution of an instruction (except for the
software interrupt).
- The address of the interrupt service program is determined by the
hardware rather than from the address field of an instruction.
- An interrupt procedure usually stores all the information necessary
to define the state of CPU rather than storing only the PC.
The state of the CPU is determined from;
Content of the PC
Content of all processor registers
Content of status bits
Many ways of saving the CPU state
depending on the CPU architectures
Program Control
Interrupt Procedure and Subroutine Call