SlideShare a Scribd company logo
COMPUTER
ORGANIZATION
MODULE-1
BASIC STRUCTURE OF
COMPUTERS
Basic Operational Concepts:
•A typical instruction may be like
Add LOCA, R0
This instruction adds the operand at the memory
location LOCA to the operand in a register R0 and
places the result in the register.
Similarly:
Load LOCA, R1
Add R1,R0
• Figure below shows the connection between the
memory and the processor
Figure 1.2. Connections between the processor and the memory.
Processor
Memory
PC
IR
MDR
Control
ALU
Rn 1-
R1
R0
MAR
n general purpose
registers
• The processor contains a number of registers used for
different purposes.
• The Instruction Register (IR) holds the instruction that is
currently being executed.
• The Program Counter(PC) is a specialized register which
keeps track of the address of the next instruction to be
fetched and executed.
• The Memory Address Register(MAR) holds the address of the
location to be accessed.
• The Memory Data Register(MDR) contains the data to be
written into or read out of the addressed location.
• The n general purpose registers which stores the contents
Interrupt:
• Normal execution of the program may be preempted if some
device requires urgent servicing
• In order to deal with the request, the normal execution is
interrupted and the device raises the interrupt signal.
• ISR (Interrupt Service Routine)
• ISR saves the internal state of the processor, PC, the general
registers and some control information.
• When ISR is completed the state of the processor is restored and
interrupted program may continue its execution.
Bus Structures
• A group of lines that serve as a connecting path
for several devices is called a bus.
• The system bus has three parts:
• Data bus
• Address bus
• Control bus
• There are two types of bus:
• Single bus structure
• Multi bus structure
Single Bus Structure
• All units are connected to a
single bus.
• Only two devices can connect
at a time.
• Single bus structure is vastly
used because of its low cost
and flexibility.
• The device connected to the
bus widely vary with their
speed of operation.
• Consider the transfer of an
encoded character from the
processor to the printer.
Figure 1.3. Single-bus structure.
MemoryInput Output Processor
• Drawback of Single Bus Structure:
• The performance of the computer system suffers when large
number of device is connected to the bus.
• Propagation Delay
• Bus- Bottleneck
Multiple Bus Structure:
• Achieve more concurrency
• Leads to better performance
• Increased cost
PERFORMANCE
• Performance is the time taken by the system to
execute a program.
• The parameters that effect the performance are
processor clock speed, type of instruction, memory
access time, type of I/O devices connected, and
data transfer capacity.
• Elapsed time: The total time required to execute the
program.
• Processor Time: The period in which the processor is
active.
• The processor cache
Processor Clock
• Processor circuits are controlled by a timing signal
called Clock.
• The clock defines a regular time interval called clock
cycles.
• The length P of one clock cycle is an important
parameter that effects the processor performance.
Clock rate R=1/P
• Where P- Length of one clock cycle.
Clock Cycle P=I*CPI
• Where I is number of instructions
• CPI –Average clock cycle per instruction
Basic Performance Equation
• Let T be the processor time required to execute a
program.
• Assume that complete execution of the program
requires the execution of N machine language
Instructions.
• Suppose that average number of basic step needed
to execute one machine instruction is S.
• If the clock rate is R cycles per sec then the program
execution time is given by
T= N* S/ R
(Basic performance Equation)
Clock Rate
• There are two possibilities of increasing the clock rate R,
• First, Improving the IC technology makes the logical
circuit faster, which reduces the time of execution of
basic steps, This allows the clock period P, to be
reduced and the clock rate to be increased.
• Second, Reducing the amount of processing done in
one basic step.
Performance Measurement
• Let us consider two programs P1 and P2 with first
one having all operands in memory and second
having all operands in CPU. Consider two computers
C1 and C2. The clock speed of C1 is greater than
that of C2. However memory access time in C1 is
faster than C2. With these conditions which
program gets executed faster??? Which computer is
faster??
• Measure of instruction execution performance are based on
average figures which are usually determined by measuring the
runtimes of representative called benchmark program.
• SPEC (System Performance Evaluation Corporation).
• SPEC rating = Running time on the reference computer
Running time on the computer under test
Let SPEC I be the rating for the program I in the suite
SPEC rating =
Where n is the number of programs in the suite.

More Related Content

What's hot

Computer Organisation and Architecture
Computer Organisation and ArchitectureComputer Organisation and Architecture
Computer Organisation and Architecture
Subhasis Dash
 
Central Processing Unit (Instruction Circle)
Central Processing Unit (Instruction Circle)Central Processing Unit (Instruction Circle)
Central Processing Unit (Instruction Circle)
muhd afiq
 
1353142173system unit
1353142173system unit1353142173system unit
1353142173system unit
Najmul Hassan
 
Program execution
Program executionProgram execution
Program execution
peoplesmagnet
 
Computer organization basics
Computer organization  basicsComputer organization  basics
Computer organization basics
Deepak John
 
Algorithm and flowchart
Algorithm and flowchartAlgorithm and flowchart
Algorithm and flowchart
BaliThorat1
 
Coal 10 instruction cycle and interrupts in Assembly Programming
Coal 10 instruction cycle and interrupts in Assembly ProgrammingCoal 10 instruction cycle and interrupts in Assembly Programming
Coal 10 instruction cycle and interrupts in Assembly Programming
Muhammad Taqi Hassan Bukhari
 
13 risc
13 risc13 risc
13 risc
dilip kumar
 
16 control unit
16 control unit16 control unit
16 control unit
dilip kumar
 
17 micro programmed control
17 micro programmed control17 micro programmed control
17 micro programmed control
dilip kumar
 
Intro to the unit
Intro to the unitIntro to the unit
Intro to the unit
Graeme Smith
 
Basic ops concept of comp
Basic ops  concept of compBasic ops  concept of comp
Basic ops concept of comp
gaurav jain
 
Control unit
Control  unitControl  unit
Control unit
Sameer Patil
 
Basic non pipelined cpu architecture
Basic non pipelined cpu architectureBasic non pipelined cpu architecture
Basic non pipelined cpu architecture
kalyani yogeswaranathan
 
03 top level view of computer function and interconnection.ppt.enc
03 top level view of computer function and interconnection.ppt.enc03 top level view of computer function and interconnection.ppt.enc
03 top level view of computer function and interconnection.ppt.enc
Anwal Mirza
 
Unit 2
Unit 2Unit 2
CPU Organization,Datatransfer and manipulation
CPU Organization,Datatransfer and manipulationCPU Organization,Datatransfer and manipulation
CPU Organization,Datatransfer and manipulation
NITISH KUMAR
 
HHCJ AMUMARA:COMPUTER STUDIES LECTURE NOTE FOR SS1:002
HHCJ AMUMARA:COMPUTER STUDIES LECTURE NOTE FOR SS1:002HHCJ AMUMARA:COMPUTER STUDIES LECTURE NOTE FOR SS1:002
HHCJ AMUMARA:COMPUTER STUDIES LECTURE NOTE FOR SS1:002
SOLOMONCHINAEMEUCHEA
 
Data Manipulation
Data ManipulationData Manipulation
Data Manipulation
Asfi Bhai
 
03 top level view of computer function and interconnection
03 top level view of computer function and interconnection03 top level view of computer function and interconnection
03 top level view of computer function and interconnection
Sher Shah Merkhel
 

What's hot (20)

Computer Organisation and Architecture
Computer Organisation and ArchitectureComputer Organisation and Architecture
Computer Organisation and Architecture
 
Central Processing Unit (Instruction Circle)
Central Processing Unit (Instruction Circle)Central Processing Unit (Instruction Circle)
Central Processing Unit (Instruction Circle)
 
1353142173system unit
1353142173system unit1353142173system unit
1353142173system unit
 
Program execution
Program executionProgram execution
Program execution
 
Computer organization basics
Computer organization  basicsComputer organization  basics
Computer organization basics
 
Algorithm and flowchart
Algorithm and flowchartAlgorithm and flowchart
Algorithm and flowchart
 
Coal 10 instruction cycle and interrupts in Assembly Programming
Coal 10 instruction cycle and interrupts in Assembly ProgrammingCoal 10 instruction cycle and interrupts in Assembly Programming
Coal 10 instruction cycle and interrupts in Assembly Programming
 
13 risc
13 risc13 risc
13 risc
 
16 control unit
16 control unit16 control unit
16 control unit
 
17 micro programmed control
17 micro programmed control17 micro programmed control
17 micro programmed control
 
Intro to the unit
Intro to the unitIntro to the unit
Intro to the unit
 
Basic ops concept of comp
Basic ops  concept of compBasic ops  concept of comp
Basic ops concept of comp
 
Control unit
Control  unitControl  unit
Control unit
 
Basic non pipelined cpu architecture
Basic non pipelined cpu architectureBasic non pipelined cpu architecture
Basic non pipelined cpu architecture
 
03 top level view of computer function and interconnection.ppt.enc
03 top level view of computer function and interconnection.ppt.enc03 top level view of computer function and interconnection.ppt.enc
03 top level view of computer function and interconnection.ppt.enc
 
Unit 2
Unit 2Unit 2
Unit 2
 
CPU Organization,Datatransfer and manipulation
CPU Organization,Datatransfer and manipulationCPU Organization,Datatransfer and manipulation
CPU Organization,Datatransfer and manipulation
 
HHCJ AMUMARA:COMPUTER STUDIES LECTURE NOTE FOR SS1:002
HHCJ AMUMARA:COMPUTER STUDIES LECTURE NOTE FOR SS1:002HHCJ AMUMARA:COMPUTER STUDIES LECTURE NOTE FOR SS1:002
HHCJ AMUMARA:COMPUTER STUDIES LECTURE NOTE FOR SS1:002
 
Data Manipulation
Data ManipulationData Manipulation
Data Manipulation
 
03 top level view of computer function and interconnection
03 top level view of computer function and interconnection03 top level view of computer function and interconnection
03 top level view of computer function and interconnection
 

Similar to Co m1-1

chapter 1 -Basic Structure of Computers.pptx
chapter 1 -Basic Structure of Computers.pptxchapter 1 -Basic Structure of Computers.pptx
chapter 1 -Basic Structure of Computers.pptx
janani603976
 
Computer Organisation & Architecture (chapter 1)
Computer Organisation & Architecture (chapter 1) Computer Organisation & Architecture (chapter 1)
Computer Organisation & Architecture (chapter 1)
Subhasis Dash
 
Computer Organization and Architechuture basics
Computer Organization and Architechuture basicsComputer Organization and Architechuture basics
Computer Organization and Architechuture basics
Lucky Sithole
 
Basic Structure of Computers: Functional Units, Basic Operational Concepts, B...
Basic Structure of Computers: Functional Units, Basic Operational Concepts, B...Basic Structure of Computers: Functional Units, Basic Operational Concepts, B...
Basic Structure of Computers: Functional Units, Basic Operational Concepts, B...
Abhishekn84
 
CAO.pptx
CAO.pptxCAO.pptx
CAO.pptx
FarhanaMariyam1
 
introduction COA(M1).pptx
introduction COA(M1).pptxintroduction COA(M1).pptx
introduction COA(M1).pptx
BhavanaMinchu
 
Unit 1 Computer organization and Instructions
Unit 1 Computer organization and InstructionsUnit 1 Computer organization and Instructions
Unit 1 Computer organization and Instructions
Balaji Vignesh
 
module 1 computer architecture diploma
 module 1 computer architecture diploma   module 1 computer architecture diploma
module 1 computer architecture diploma
Manoharan Ragavan
 
Cao u1
Cao u1Cao u1
unit-i.pdf
unit-i.pdfunit-i.pdf
unit-i.pdf
RISHI643981
 
Co notes3 sem
Co notes3 semCo notes3 sem
Co notes3 sem
dilshad begum
 
Unit iii
Unit iiiUnit iii
Unit iii
Janani S
 
Computer organisation and architecture updated unit 2 COA ppt.pptx
Computer organisation and architecture updated unit 2 COA ppt.pptxComputer organisation and architecture updated unit 2 COA ppt.pptx
Computer organisation and architecture updated unit 2 COA ppt.pptx
MalligaarjunanN
 
Computer_Organization and architecture _unit 1.pptx
Computer_Organization and architecture _unit 1.pptxComputer_Organization and architecture _unit 1.pptx
Computer_Organization and architecture _unit 1.pptx
ManimegalaM3
 
Processor Organization and Architecture
Processor Organization and ArchitectureProcessor Organization and Architecture
Processor Organization and Architecture
Dhaval Bagal
 
Computer Organization and Architecture.pptx
Computer Organization and Architecture.pptxComputer Organization and Architecture.pptx
Computer Organization and Architecture.pptx
AshokRachapalli1
 
COMPUTER SYSTEM ARCHITECTURE UNIT 3 FULL SLIDES
COMPUTER SYSTEM ARCHITECTURE UNIT 3 FULL SLIDESCOMPUTER SYSTEM ARCHITECTURE UNIT 3 FULL SLIDES
COMPUTER SYSTEM ARCHITECTURE UNIT 3 FULL SLIDES
ShahidSultan24
 
L-2 (Computer Performance).ppt
L-2 (Computer Performance).pptL-2 (Computer Performance).ppt
L-2 (Computer Performance).ppt
ImranKhan997082
 
Unit 1 computer architecture (1)
Unit 1   computer architecture (1)Unit 1   computer architecture (1)
Unit 1 computer architecture (1)
DevaKumari Vijay
 
Unit - 5 Pipelining.pptx
Unit - 5 Pipelining.pptxUnit - 5 Pipelining.pptx
Unit - 5 Pipelining.pptx
Medicaps University
 

Similar to Co m1-1 (20)

chapter 1 -Basic Structure of Computers.pptx
chapter 1 -Basic Structure of Computers.pptxchapter 1 -Basic Structure of Computers.pptx
chapter 1 -Basic Structure of Computers.pptx
 
Computer Organisation & Architecture (chapter 1)
Computer Organisation & Architecture (chapter 1) Computer Organisation & Architecture (chapter 1)
Computer Organisation & Architecture (chapter 1)
 
Computer Organization and Architechuture basics
Computer Organization and Architechuture basicsComputer Organization and Architechuture basics
Computer Organization and Architechuture basics
 
Basic Structure of Computers: Functional Units, Basic Operational Concepts, B...
Basic Structure of Computers: Functional Units, Basic Operational Concepts, B...Basic Structure of Computers: Functional Units, Basic Operational Concepts, B...
Basic Structure of Computers: Functional Units, Basic Operational Concepts, B...
 
CAO.pptx
CAO.pptxCAO.pptx
CAO.pptx
 
introduction COA(M1).pptx
introduction COA(M1).pptxintroduction COA(M1).pptx
introduction COA(M1).pptx
 
Unit 1 Computer organization and Instructions
Unit 1 Computer organization and InstructionsUnit 1 Computer organization and Instructions
Unit 1 Computer organization and Instructions
 
module 1 computer architecture diploma
 module 1 computer architecture diploma   module 1 computer architecture diploma
module 1 computer architecture diploma
 
Cao u1
Cao u1Cao u1
Cao u1
 
unit-i.pdf
unit-i.pdfunit-i.pdf
unit-i.pdf
 
Co notes3 sem
Co notes3 semCo notes3 sem
Co notes3 sem
 
Unit iii
Unit iiiUnit iii
Unit iii
 
Computer organisation and architecture updated unit 2 COA ppt.pptx
Computer organisation and architecture updated unit 2 COA ppt.pptxComputer organisation and architecture updated unit 2 COA ppt.pptx
Computer organisation and architecture updated unit 2 COA ppt.pptx
 
Computer_Organization and architecture _unit 1.pptx
Computer_Organization and architecture _unit 1.pptxComputer_Organization and architecture _unit 1.pptx
Computer_Organization and architecture _unit 1.pptx
 
Processor Organization and Architecture
Processor Organization and ArchitectureProcessor Organization and Architecture
Processor Organization and Architecture
 
Computer Organization and Architecture.pptx
Computer Organization and Architecture.pptxComputer Organization and Architecture.pptx
Computer Organization and Architecture.pptx
 
COMPUTER SYSTEM ARCHITECTURE UNIT 3 FULL SLIDES
COMPUTER SYSTEM ARCHITECTURE UNIT 3 FULL SLIDESCOMPUTER SYSTEM ARCHITECTURE UNIT 3 FULL SLIDES
COMPUTER SYSTEM ARCHITECTURE UNIT 3 FULL SLIDES
 
L-2 (Computer Performance).ppt
L-2 (Computer Performance).pptL-2 (Computer Performance).ppt
L-2 (Computer Performance).ppt
 
Unit 1 computer architecture (1)
Unit 1   computer architecture (1)Unit 1   computer architecture (1)
Unit 1 computer architecture (1)
 
Unit - 5 Pipelining.pptx
Unit - 5 Pipelining.pptxUnit - 5 Pipelining.pptx
Unit - 5 Pipelining.pptx
 

Recently uploaded

BPV-GUI-01-Guide-for-ASME-Review-Teams-(General)-10-10-2023.pdf
BPV-GUI-01-Guide-for-ASME-Review-Teams-(General)-10-10-2023.pdfBPV-GUI-01-Guide-for-ASME-Review-Teams-(General)-10-10-2023.pdf
BPV-GUI-01-Guide-for-ASME-Review-Teams-(General)-10-10-2023.pdf
MIGUELANGEL966976
 
Presentation of IEEE Slovenia CIS (Computational Intelligence Society) Chapte...
Presentation of IEEE Slovenia CIS (Computational Intelligence Society) Chapte...Presentation of IEEE Slovenia CIS (Computational Intelligence Society) Chapte...
Presentation of IEEE Slovenia CIS (Computational Intelligence Society) Chapte...
University of Maribor
 
2008 BUILDING CONSTRUCTION Illustrated - Ching Chapter 02 The Building.pdf
2008 BUILDING CONSTRUCTION Illustrated - Ching Chapter 02 The Building.pdf2008 BUILDING CONSTRUCTION Illustrated - Ching Chapter 02 The Building.pdf
2008 BUILDING CONSTRUCTION Illustrated - Ching Chapter 02 The Building.pdf
Yasser Mahgoub
 
Modelagem de um CSTR com reação endotermica.pdf
Modelagem de um CSTR com reação endotermica.pdfModelagem de um CSTR com reação endotermica.pdf
Modelagem de um CSTR com reação endotermica.pdf
camseq
 
TIME DIVISION MULTIPLEXING TECHNIQUE FOR COMMUNICATION SYSTEM
TIME DIVISION MULTIPLEXING TECHNIQUE FOR COMMUNICATION SYSTEMTIME DIVISION MULTIPLEXING TECHNIQUE FOR COMMUNICATION SYSTEM
TIME DIVISION MULTIPLEXING TECHNIQUE FOR COMMUNICATION SYSTEM
HODECEDSIET
 
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressions
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsKuberTENes Birthday Bash Guadalajara - K8sGPT first impressions
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressions
Victor Morales
 
132/33KV substation case study Presentation
132/33KV substation case study Presentation132/33KV substation case study Presentation
132/33KV substation case study Presentation
kandramariana6
 
New techniques for characterising damage in rock slopes.pdf
New techniques for characterising damage in rock slopes.pdfNew techniques for characterising damage in rock slopes.pdf
New techniques for characterising damage in rock slopes.pdf
wisnuprabawa3
 
Optimizing Gradle Builds - Gradle DPE Tour Berlin 2024
Optimizing Gradle Builds - Gradle DPE Tour Berlin 2024Optimizing Gradle Builds - Gradle DPE Tour Berlin 2024
Optimizing Gradle Builds - Gradle DPE Tour Berlin 2024
Sinan KOZAK
 
哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样
哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样
哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样
insn4465
 
ACEP Magazine edition 4th launched on 05.06.2024
ACEP Magazine edition 4th launched on 05.06.2024ACEP Magazine edition 4th launched on 05.06.2024
ACEP Magazine edition 4th launched on 05.06.2024
Rahul
 
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODEL
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODELDEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODEL
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODEL
gerogepatton
 
Textile Chemical Processing and Dyeing.pdf
Textile Chemical Processing and Dyeing.pdfTextile Chemical Processing and Dyeing.pdf
Textile Chemical Processing and Dyeing.pdf
NazakatAliKhoso2
 
Question paper of renewable energy sources
Question paper of renewable energy sourcesQuestion paper of renewable energy sources
Question paper of renewable energy sources
mahammadsalmanmech
 
ML Based Model for NIDS MSc Updated Presentation.v2.pptx
ML Based Model for NIDS MSc Updated Presentation.v2.pptxML Based Model for NIDS MSc Updated Presentation.v2.pptx
ML Based Model for NIDS MSc Updated Presentation.v2.pptx
JamalHussainArman
 
Embedded machine learning-based road conditions and driving behavior monitoring
Embedded machine learning-based road conditions and driving behavior monitoringEmbedded machine learning-based road conditions and driving behavior monitoring
Embedded machine learning-based road conditions and driving behavior monitoring
IJECEIAES
 
学校原版美国波士顿大学毕业证学历学位证书原版一模一样
学校原版美国波士顿大学毕业证学历学位证书原版一模一样学校原版美国波士顿大学毕业证学历学位证书原版一模一样
学校原版美国波士顿大学毕业证学历学位证书原版一模一样
171ticu
 
ISPM 15 Heat Treated Wood Stamps and why your shipping must have one
ISPM 15 Heat Treated Wood Stamps and why your shipping must have oneISPM 15 Heat Treated Wood Stamps and why your shipping must have one
ISPM 15 Heat Treated Wood Stamps and why your shipping must have one
Las Vegas Warehouse
 
Computational Engineering IITH Presentation
Computational Engineering IITH PresentationComputational Engineering IITH Presentation
Computational Engineering IITH Presentation
co23btech11018
 
Manufacturing Process of molasses based distillery ppt.pptx
Manufacturing Process of molasses based distillery ppt.pptxManufacturing Process of molasses based distillery ppt.pptx
Manufacturing Process of molasses based distillery ppt.pptx
Madan Karki
 

Recently uploaded (20)

BPV-GUI-01-Guide-for-ASME-Review-Teams-(General)-10-10-2023.pdf
BPV-GUI-01-Guide-for-ASME-Review-Teams-(General)-10-10-2023.pdfBPV-GUI-01-Guide-for-ASME-Review-Teams-(General)-10-10-2023.pdf
BPV-GUI-01-Guide-for-ASME-Review-Teams-(General)-10-10-2023.pdf
 
Presentation of IEEE Slovenia CIS (Computational Intelligence Society) Chapte...
Presentation of IEEE Slovenia CIS (Computational Intelligence Society) Chapte...Presentation of IEEE Slovenia CIS (Computational Intelligence Society) Chapte...
Presentation of IEEE Slovenia CIS (Computational Intelligence Society) Chapte...
 
2008 BUILDING CONSTRUCTION Illustrated - Ching Chapter 02 The Building.pdf
2008 BUILDING CONSTRUCTION Illustrated - Ching Chapter 02 The Building.pdf2008 BUILDING CONSTRUCTION Illustrated - Ching Chapter 02 The Building.pdf
2008 BUILDING CONSTRUCTION Illustrated - Ching Chapter 02 The Building.pdf
 
Modelagem de um CSTR com reação endotermica.pdf
Modelagem de um CSTR com reação endotermica.pdfModelagem de um CSTR com reação endotermica.pdf
Modelagem de um CSTR com reação endotermica.pdf
 
TIME DIVISION MULTIPLEXING TECHNIQUE FOR COMMUNICATION SYSTEM
TIME DIVISION MULTIPLEXING TECHNIQUE FOR COMMUNICATION SYSTEMTIME DIVISION MULTIPLEXING TECHNIQUE FOR COMMUNICATION SYSTEM
TIME DIVISION MULTIPLEXING TECHNIQUE FOR COMMUNICATION SYSTEM
 
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressions
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsKuberTENes Birthday Bash Guadalajara - K8sGPT first impressions
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressions
 
132/33KV substation case study Presentation
132/33KV substation case study Presentation132/33KV substation case study Presentation
132/33KV substation case study Presentation
 
New techniques for characterising damage in rock slopes.pdf
New techniques for characterising damage in rock slopes.pdfNew techniques for characterising damage in rock slopes.pdf
New techniques for characterising damage in rock slopes.pdf
 
Optimizing Gradle Builds - Gradle DPE Tour Berlin 2024
Optimizing Gradle Builds - Gradle DPE Tour Berlin 2024Optimizing Gradle Builds - Gradle DPE Tour Berlin 2024
Optimizing Gradle Builds - Gradle DPE Tour Berlin 2024
 
哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样
哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样
哪里办理(csu毕业证书)查尔斯特大学毕业证硕士学历原版一模一样
 
ACEP Magazine edition 4th launched on 05.06.2024
ACEP Magazine edition 4th launched on 05.06.2024ACEP Magazine edition 4th launched on 05.06.2024
ACEP Magazine edition 4th launched on 05.06.2024
 
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODEL
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODELDEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODEL
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODEL
 
Textile Chemical Processing and Dyeing.pdf
Textile Chemical Processing and Dyeing.pdfTextile Chemical Processing and Dyeing.pdf
Textile Chemical Processing and Dyeing.pdf
 
Question paper of renewable energy sources
Question paper of renewable energy sourcesQuestion paper of renewable energy sources
Question paper of renewable energy sources
 
ML Based Model for NIDS MSc Updated Presentation.v2.pptx
ML Based Model for NIDS MSc Updated Presentation.v2.pptxML Based Model for NIDS MSc Updated Presentation.v2.pptx
ML Based Model for NIDS MSc Updated Presentation.v2.pptx
 
Embedded machine learning-based road conditions and driving behavior monitoring
Embedded machine learning-based road conditions and driving behavior monitoringEmbedded machine learning-based road conditions and driving behavior monitoring
Embedded machine learning-based road conditions and driving behavior monitoring
 
学校原版美国波士顿大学毕业证学历学位证书原版一模一样
学校原版美国波士顿大学毕业证学历学位证书原版一模一样学校原版美国波士顿大学毕业证学历学位证书原版一模一样
学校原版美国波士顿大学毕业证学历学位证书原版一模一样
 
ISPM 15 Heat Treated Wood Stamps and why your shipping must have one
ISPM 15 Heat Treated Wood Stamps and why your shipping must have oneISPM 15 Heat Treated Wood Stamps and why your shipping must have one
ISPM 15 Heat Treated Wood Stamps and why your shipping must have one
 
Computational Engineering IITH Presentation
Computational Engineering IITH PresentationComputational Engineering IITH Presentation
Computational Engineering IITH Presentation
 
Manufacturing Process of molasses based distillery ppt.pptx
Manufacturing Process of molasses based distillery ppt.pptxManufacturing Process of molasses based distillery ppt.pptx
Manufacturing Process of molasses based distillery ppt.pptx
 

Co m1-1

  • 3. Basic Operational Concepts: •A typical instruction may be like Add LOCA, R0 This instruction adds the operand at the memory location LOCA to the operand in a register R0 and places the result in the register. Similarly: Load LOCA, R1 Add R1,R0
  • 4. • Figure below shows the connection between the memory and the processor Figure 1.2. Connections between the processor and the memory. Processor Memory PC IR MDR Control ALU Rn 1- R1 R0 MAR n general purpose registers
  • 5. • The processor contains a number of registers used for different purposes. • The Instruction Register (IR) holds the instruction that is currently being executed. • The Program Counter(PC) is a specialized register which keeps track of the address of the next instruction to be fetched and executed. • The Memory Address Register(MAR) holds the address of the location to be accessed. • The Memory Data Register(MDR) contains the data to be written into or read out of the addressed location. • The n general purpose registers which stores the contents
  • 6. Interrupt: • Normal execution of the program may be preempted if some device requires urgent servicing • In order to deal with the request, the normal execution is interrupted and the device raises the interrupt signal. • ISR (Interrupt Service Routine) • ISR saves the internal state of the processor, PC, the general registers and some control information. • When ISR is completed the state of the processor is restored and interrupted program may continue its execution.
  • 7. Bus Structures • A group of lines that serve as a connecting path for several devices is called a bus. • The system bus has three parts: • Data bus • Address bus • Control bus • There are two types of bus: • Single bus structure • Multi bus structure
  • 8. Single Bus Structure • All units are connected to a single bus. • Only two devices can connect at a time. • Single bus structure is vastly used because of its low cost and flexibility. • The device connected to the bus widely vary with their speed of operation. • Consider the transfer of an encoded character from the processor to the printer. Figure 1.3. Single-bus structure. MemoryInput Output Processor
  • 9. • Drawback of Single Bus Structure: • The performance of the computer system suffers when large number of device is connected to the bus. • Propagation Delay • Bus- Bottleneck Multiple Bus Structure: • Achieve more concurrency • Leads to better performance • Increased cost
  • 10. PERFORMANCE • Performance is the time taken by the system to execute a program. • The parameters that effect the performance are processor clock speed, type of instruction, memory access time, type of I/O devices connected, and data transfer capacity. • Elapsed time: The total time required to execute the program. • Processor Time: The period in which the processor is active.
  • 12. Processor Clock • Processor circuits are controlled by a timing signal called Clock. • The clock defines a regular time interval called clock cycles. • The length P of one clock cycle is an important parameter that effects the processor performance. Clock rate R=1/P • Where P- Length of one clock cycle. Clock Cycle P=I*CPI • Where I is number of instructions • CPI –Average clock cycle per instruction
  • 13. Basic Performance Equation • Let T be the processor time required to execute a program. • Assume that complete execution of the program requires the execution of N machine language Instructions. • Suppose that average number of basic step needed to execute one machine instruction is S. • If the clock rate is R cycles per sec then the program execution time is given by T= N* S/ R (Basic performance Equation)
  • 14. Clock Rate • There are two possibilities of increasing the clock rate R, • First, Improving the IC technology makes the logical circuit faster, which reduces the time of execution of basic steps, This allows the clock period P, to be reduced and the clock rate to be increased. • Second, Reducing the amount of processing done in one basic step.
  • 15. Performance Measurement • Let us consider two programs P1 and P2 with first one having all operands in memory and second having all operands in CPU. Consider two computers C1 and C2. The clock speed of C1 is greater than that of C2. However memory access time in C1 is faster than C2. With these conditions which program gets executed faster??? Which computer is faster??
  • 16. • Measure of instruction execution performance are based on average figures which are usually determined by measuring the runtimes of representative called benchmark program. • SPEC (System Performance Evaluation Corporation). • SPEC rating = Running time on the reference computer Running time on the computer under test Let SPEC I be the rating for the program I in the suite SPEC rating = Where n is the number of programs in the suite.