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Test Insight Semiconductors test challenges
Agenda ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
The control gap Company Test Programs database Rev 2.0.52 Acceptance Alignment Install – Rev 2.0.49 ? Fabless in Israel Subcon in Asia
The control gap Do we actually have 99.9% fault coverage in Production? Scan Test 98% coverage Func. Test 1.99% coverage On Total: 99.9% coverage DUT design Test Plan Production 99.9%  Test development Test Development
So, we have like 99.9% coverage, but now the test engineer is alone on the tester !
Mask failures Remove tests The control gap   The weakest point in quality chain is debug  Before debug After  “ debug ”
The bigger picture - challenges Product Start   Tape Out   1st  Silicon   Product  Ready Product  Ship ProductEnd   Start  TP End TP  Maintain TP   Consolidate TP   Debug TP   Fill TP   Test Program planning Debug TP   Pre-silicon Debug Manage Program Releases to Production Get Visibility of Changes Multiple Engineers developing one Program Multiple Engineers debugging one Program Add and Remove Tests (at different locations?)
Discussion - challenges ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Meeting the Challenges  Closing the loop ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Analysis
Meeting the Challenges  Enforce company methodology Product Start   Tape Out   1st  Silicon   Product  Ready Product  Ship ProductEnd   Start  TP End TP  Maintain TP   Consolidate TP   Debug TP   Fill TP   Test Program planning (A skeleton) Analyse And extract A skeleton Mature TP Skeleton TP
[object Object],[object Object],[object Object],Meeting the Challenges  Enforce company methodology
Test Program Compliance Checker Report
Meeting the Challenges  Managing Collaborative work ProductEnd   Analyse Smart Merge Product Start   Tape Out   1st  Silicon   Product  Ready Product  Ship Start  TP End TP  Maintain TP   Consolidate TP   Debug TP   Fill TP   Multiple Engineers developing one Program Multiple Engineers debugging one Program Add and Remove Tests (at different locations?) Split TP Merge TP
Meeting the Challenges  Managing test usage - Releases Product Start   Tape Out   1st  Silicon   Product  Ready Product  Ship ProductEnd   Start  TP End TP  Maintain TP   Consolidate TP   Debug TP   Fill TP   Add and Remove Tests (at different locations?) Get Visibility of Changes "Golden"  Program/Rules Report Analyse
Applying Incremental Changes 93k Single- Test- Suite TP Master TP Rev. 1 Master TP Rev. 2 Merge Rules Changes ,[object Object],[object Object],[object Object],[object Object],[object Object],Identify changes Viewpoint of master TP Apply changes Semantic Compare Merge
Preparing Single-Test-Suite TPs   A customer case ,[object Object],[object Object],[object Object],[object Object],[object Object],incremental integration stpm .setup Test Program Template Merge Rules from DFT SmarTest Program Manager N1160A Rev. 1 Rev. 2 pmfl/ burst/ binl DFT Patterns incl. timing and levels DFT Patterns incl. timing and levels 93k Single- Test- Suite TPs prepare_stp
Meeting the Challenges   Test Program Analyzer ( Test Insight Product) Location of Reference  or Golden Program Path to test program to be checked. (Just a pointer) Report showing differences between Master and Checked ,[object Object],[object Object],[object Object],[object Object],[object Object],A report control setup. Define list of checks
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Meeting the Challenges   Test Program Analyzer
Meeting the Challenges  Pre-silicon Debug Product Start   Tape Out   1st  Silicon   Product  Ready Product  Ship ProductEnd   Start  TP End TP  Maintain TP   Consolidate TP   Debug TP   Fill TP   Debug TP   Pre-silicon Debug Neutral Database (STIL) DUT Model Simulation TestBench
Meeting the Challenges  Generating Test Vectors Product Start   Tape Out   1st  Silicon   Product  Ready Product  Ship ProductEnd   Start  TP End TP  Maintain TP   Consolidate TP   Debug TP   Fill TP   Generating ATE vectors ,[object Object],[object Object],Neutral Database (STIL) DUT Model Simulation TestBench View Edit
Meeting the Challenges Migration between platforms Neutral Database (STIL) Product Start   Tape Out   1st  Silicon   Product  Ready Product  Ship ProductEnd   Start  TP End TP  Maintain TP   Consolidate TP   Debug TP   Fill TP   Generating ATE vectors ,[object Object],Migrate TP   Process
Summary ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
About TestInsight ,[object Object],[object Object],[object Object],[object Object]
About TestInsight ,[object Object],plus others …

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Track g semiconductor test program - testinsight

  • 1. Test Insight Semiconductors test challenges
  • 2.
  • 3. The control gap Company Test Programs database Rev 2.0.52 Acceptance Alignment Install – Rev 2.0.49 ? Fabless in Israel Subcon in Asia
  • 4. The control gap Do we actually have 99.9% fault coverage in Production? Scan Test 98% coverage Func. Test 1.99% coverage On Total: 99.9% coverage DUT design Test Plan Production 99.9% Test development Test Development
  • 5. So, we have like 99.9% coverage, but now the test engineer is alone on the tester !
  • 6. Mask failures Remove tests The control gap The weakest point in quality chain is debug Before debug After “ debug ”
  • 7. The bigger picture - challenges Product Start Tape Out 1st Silicon Product Ready Product Ship ProductEnd Start TP End TP Maintain TP Consolidate TP Debug TP Fill TP Test Program planning Debug TP Pre-silicon Debug Manage Program Releases to Production Get Visibility of Changes Multiple Engineers developing one Program Multiple Engineers debugging one Program Add and Remove Tests (at different locations?)
  • 8.
  • 9.
  • 10. Meeting the Challenges Enforce company methodology Product Start Tape Out 1st Silicon Product Ready Product Ship ProductEnd Start TP End TP Maintain TP Consolidate TP Debug TP Fill TP Test Program planning (A skeleton) Analyse And extract A skeleton Mature TP Skeleton TP
  • 11.
  • 12. Test Program Compliance Checker Report
  • 13. Meeting the Challenges Managing Collaborative work ProductEnd Analyse Smart Merge Product Start Tape Out 1st Silicon Product Ready Product Ship Start TP End TP Maintain TP Consolidate TP Debug TP Fill TP Multiple Engineers developing one Program Multiple Engineers debugging one Program Add and Remove Tests (at different locations?) Split TP Merge TP
  • 14. Meeting the Challenges Managing test usage - Releases Product Start Tape Out 1st Silicon Product Ready Product Ship ProductEnd Start TP End TP Maintain TP Consolidate TP Debug TP Fill TP Add and Remove Tests (at different locations?) Get Visibility of Changes "Golden" Program/Rules Report Analyse
  • 15.
  • 16.
  • 17.
  • 18.
  • 19. Meeting the Challenges Pre-silicon Debug Product Start Tape Out 1st Silicon Product Ready Product Ship ProductEnd Start TP End TP Maintain TP Consolidate TP Debug TP Fill TP Debug TP Pre-silicon Debug Neutral Database (STIL) DUT Model Simulation TestBench
  • 20.
  • 21.
  • 22.
  • 23.
  • 24.

Editor's Notes

  1. Current situation – and problem description: In the current process, a very controlled process is built to achieve a very high fault coverage for any new design. The ATPG and functional tests are required to achieve a 99+% coverage. However, after the set off patterns is created, management assumes that this set of tests is fully implemented in production. In reality the weakest point in the quality chain is the test engineer sitting at the test floor debugging the test program with all the pressure from management on his back. This poor test engineer is pushed to release the test program ASAP as the silicon is already available and customers are waiting for it. So, the test engineer may mask some failures or remove some tests from the test program in order to get it done sooner.
  2. the test engineer may mask some failures or remove some tests from the test program in order to get it done sooner.