SlideShare a Scribd company logo
1 Refer to VHDL code and identify the logic
LIBRARYieee;
USE ieee.std_logic_1164.all;
ENTITYpriority IS
PORT( w : INSTD_LOGIC_VECTOR(3DOWNTO0);
y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
z : OUT STD_LOGIC);
END priority;
ARCHITECTUREBehavior OF priority IS
BEGIN
PROCESS ( w )
BEGIN
IF w(3) = '1' THEN
y <= "11" ;
ELSIF w(2) ='1' THEN
y <= "10" ;
ELSIF w(1) ='1' THEN
y <= "01" ;
ELSE
y <= "00" ;
END IF ;
END PROCESS ;
z <= '0' WHEN w = "0000" ELSE'1';
END Behavior ;
2-bitpriorityencoder
2 Among the VHDL features, which language statements are executed
at the same time in parallel flow?
a. Concurrent
b. Sequential
c. Net-list
d. Test-bench
concurrent
3 In Net-list language, the net-list is generated _______synthesizing
VHDL code.
a. Before
b. At the time of (during)
c. After
d. None of the above
After
4 Which data type in VHDL is non synthesizable & allows the designer
to model the objects of dynamic nature?
a. Scalar
b. Access
c. Composite
d. File
access
5 In the simulation process, which step specifies the conversion of
VHDL intermediate code so that it can be used by the simulator?
a. Compilation
b. Elaboration
c. Initialization
d. Execution
Elaboration
6 Hold time is defined as the time required for the data to ________ after
the triggering edge of clock.
a. Increase
b. Decrease
c. Remain stable
d. All of the above
remainstable
7 An Antifuse programming technology is predominantly associated
with _____.
a. SPLDs
b. FPGAs
c. CPLDs
d. All of the above
FPGAs
8 In fusible link technologies, the undesired fuses are removed by the
pulse application of _____voltage & current to device input.
a. Low
b. Moderate
c. High
d. All of the above
High
9 The utilization of CAD tools for drawing timing waveform diagram
and transforming it into a network of logic gates is known as ________.
a. Waveform Editor
b. Waveform Estimator
c. Waveform Simulator
d. Waveform Evaluator
waveformeditor
10 State box without decision and conditional box is
A. ASM block
B. defined block
C. simple block
D. both a and b
Simple block
11
Table that is not a part of asynchronous analysis procedure is
a. transition table
b. state table
c. flow table
d. excitation table
d

More Related Content

What's hot

How to design Programs using VHDL
How to design Programs using VHDLHow to design Programs using VHDL
How to design Programs using VHDL
Eutectics
 
VHdl lab report
VHdl lab reportVHdl lab report
VHdl lab report
Jinesh Kb
 
Lecture2 vhdl refresher
Lecture2 vhdl refresherLecture2 vhdl refresher
Lecture2 vhdl refresher
Nima Shafiee
 
Introduction to VHDL
Introduction to VHDLIntroduction to VHDL
Introduction to VHDL
Mohamed Samy
 
Vhdl
VhdlVhdl
Lecture3 combinational blocks
Lecture3 combinational blocksLecture3 combinational blocks
Lecture3 combinational blocks
Nima Shafiee
 
Programs of VHDL
Programs of VHDLPrograms of VHDL
Programs of VHDL
Rkrishna Mishra
 
VHDL-Behavioral-Programs-Structure of VHDL
VHDL-Behavioral-Programs-Structure of VHDLVHDL-Behavioral-Programs-Structure of VHDL
VHDL-Behavioral-Programs-Structure of VHDL
Revathi Subramaniam
 
VHDL course
VHDL courseVHDL course
VHDL course
Ibrahim Mezzah
 
INTRODUCTION TO VHDL
INTRODUCTION    TO    VHDLINTRODUCTION    TO    VHDL
INTRODUCTION TO VHDL
karthikpunuru
 
Basic structures in vhdl
Basic structures in vhdlBasic structures in vhdl
Basic structures in vhdlRaj Mohan
 
Introduction to VHDL
Introduction to VHDLIntroduction to VHDL
Introduction to VHDL
Farzan Dehbashi
 
Vhdl introduction
Vhdl introductionVhdl introduction
Vhdl introduction
Dhaval Shukla
 
VHDL Entity
VHDL EntityVHDL Entity
VHDL Entity
Ramasubbu .P
 
VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x Additions
VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x AdditionsVHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x Additions
VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x Additions
Amal Khailtash
 
Verilogspk1
Verilogspk1Verilogspk1
Verilogspk1
supriya kurlekar
 
Verilog HDL
Verilog HDLVerilog HDL
Verilog HDL
Mantra VLSI
 
Introduction to-vhdl
Introduction to-vhdlIntroduction to-vhdl
Introduction to-vhdl
Neeraj Gupta
 

What's hot (20)

How to design Programs using VHDL
How to design Programs using VHDLHow to design Programs using VHDL
How to design Programs using VHDL
 
VHdl lab report
VHdl lab reportVHdl lab report
VHdl lab report
 
Lecture2 vhdl refresher
Lecture2 vhdl refresherLecture2 vhdl refresher
Lecture2 vhdl refresher
 
Introduction to VHDL
Introduction to VHDLIntroduction to VHDL
Introduction to VHDL
 
Vhdl
VhdlVhdl
Vhdl
 
Lecture3 combinational blocks
Lecture3 combinational blocksLecture3 combinational blocks
Lecture3 combinational blocks
 
Basics of Vhdl
Basics of VhdlBasics of Vhdl
Basics of Vhdl
 
Programs of VHDL
Programs of VHDLPrograms of VHDL
Programs of VHDL
 
VHDL-Behavioral-Programs-Structure of VHDL
VHDL-Behavioral-Programs-Structure of VHDLVHDL-Behavioral-Programs-Structure of VHDL
VHDL-Behavioral-Programs-Structure of VHDL
 
VHDL course
VHDL courseVHDL course
VHDL course
 
INTRODUCTION TO VHDL
INTRODUCTION    TO    VHDLINTRODUCTION    TO    VHDL
INTRODUCTION TO VHDL
 
Basic structures in vhdl
Basic structures in vhdlBasic structures in vhdl
Basic structures in vhdl
 
Introduction to VHDL
Introduction to VHDLIntroduction to VHDL
Introduction to VHDL
 
Vhdl 1 ppg
Vhdl 1 ppgVhdl 1 ppg
Vhdl 1 ppg
 
Vhdl introduction
Vhdl introductionVhdl introduction
Vhdl introduction
 
VHDL Entity
VHDL EntityVHDL Entity
VHDL Entity
 
VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x Additions
VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x AdditionsVHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x Additions
VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x Additions
 
Verilogspk1
Verilogspk1Verilogspk1
Verilogspk1
 
Verilog HDL
Verilog HDLVerilog HDL
Verilog HDL
 
Introduction to-vhdl
Introduction to-vhdlIntroduction to-vhdl
Introduction to-vhdl
 

Similar to Vhdl

Session1
Session1Session1
Session1
omarAbdelrhman2
 
Digital system design lab manual
Digital system design lab manualDigital system design lab manual
Digital system design lab manual
Santhosh Poralu
 
Practical file
Practical filePractical file
Practical file
rajeevkr35
 
Digital System Design Lab Report - VHDL ECE
Digital System Design Lab Report - VHDL ECEDigital System Design Lab Report - VHDL ECE
Digital System Design Lab Report - VHDL ECE
Ramesh Naik Bhukya
 
VHDL PROGRAMS FEW EXAMPLES
VHDL PROGRAMS FEW EXAMPLESVHDL PROGRAMS FEW EXAMPLES
VHDL PROGRAMS FEW EXAMPLES
karthik kadava
 
Pipeline stalling in vhdl
Pipeline stalling in vhdlPipeline stalling in vhdl
Pipeline stalling in vhdlSai Malleswar
 
Data Acquisition
Data AcquisitionData Acquisition
Data Acquisition
azhar557
 
Kroening et al, v2c a verilog to c translator
Kroening et al, v2c   a verilog to c translatorKroening et al, v2c   a verilog to c translator
Kroening et al, v2c a verilog to c translator
sce,bhopal
 
VHDL summer training (ppt)
 VHDL summer training (ppt) VHDL summer training (ppt)
VHDL summer training (ppt)
HoneyKumar34
 
verilog ppt .pdf
verilog ppt .pdfverilog ppt .pdf
verilog ppt .pdf
RavinaBishnoi8
 
Building Hierarchy
Building HierarchyBuilding Hierarchy
Building Hierarchy
Mohamed Samy
 
Verilog_Cheat_sheet_1672542963.pdf
Verilog_Cheat_sheet_1672542963.pdfVerilog_Cheat_sheet_1672542963.pdf
Verilog_Cheat_sheet_1672542963.pdf
sagar414433
 
Verilog_Cheat_sheet_1672542963.pdf
Verilog_Cheat_sheet_1672542963.pdfVerilog_Cheat_sheet_1672542963.pdf
Verilog_Cheat_sheet_1672542963.pdf
sagar414433
 
Verilog Cheat sheet-2 (1).pdf
Verilog Cheat sheet-2 (1).pdfVerilog Cheat sheet-2 (1).pdf
Verilog Cheat sheet-2 (1).pdf
DrViswanathKalannaga1
 
Vhdl lab manual
Vhdl lab manualVhdl lab manual
Vhdl lab manual
Mukul Mohal
 
Session 02 _rtl_design_with_vhdl 101
Session 02 _rtl_design_with_vhdl 101Session 02 _rtl_design_with_vhdl 101
Session 02 _rtl_design_with_vhdl 101
Mahmoud Abdellatif
 

Similar to Vhdl (20)

Session1
Session1Session1
Session1
 
Digital system design lab manual
Digital system design lab manualDigital system design lab manual
Digital system design lab manual
 
Practical file
Practical filePractical file
Practical file
 
Digital System Design Lab Report - VHDL ECE
Digital System Design Lab Report - VHDL ECEDigital System Design Lab Report - VHDL ECE
Digital System Design Lab Report - VHDL ECE
 
Data Flow Modeling
Data Flow ModelingData Flow Modeling
Data Flow Modeling
 
Fpga creating counter with internal clock
Fpga   creating counter with internal clockFpga   creating counter with internal clock
Fpga creating counter with internal clock
 
VHDL PROGRAMS FEW EXAMPLES
VHDL PROGRAMS FEW EXAMPLESVHDL PROGRAMS FEW EXAMPLES
VHDL PROGRAMS FEW EXAMPLES
 
Pipeline stalling in vhdl
Pipeline stalling in vhdlPipeline stalling in vhdl
Pipeline stalling in vhdl
 
Data Acquisition
Data AcquisitionData Acquisition
Data Acquisition
 
Kroening et al, v2c a verilog to c translator
Kroening et al, v2c   a verilog to c translatorKroening et al, v2c   a verilog to c translator
Kroening et al, v2c a verilog to c translator
 
Fpga creating counter with external clock
Fpga   creating counter with external clockFpga   creating counter with external clock
Fpga creating counter with external clock
 
VHDL summer training (ppt)
 VHDL summer training (ppt) VHDL summer training (ppt)
VHDL summer training (ppt)
 
verilog ppt .pdf
verilog ppt .pdfverilog ppt .pdf
verilog ppt .pdf
 
Building Hierarchy
Building HierarchyBuilding Hierarchy
Building Hierarchy
 
Verilog_Cheat_sheet_1672542963.pdf
Verilog_Cheat_sheet_1672542963.pdfVerilog_Cheat_sheet_1672542963.pdf
Verilog_Cheat_sheet_1672542963.pdf
 
Verilog_Cheat_sheet_1672542963.pdf
Verilog_Cheat_sheet_1672542963.pdfVerilog_Cheat_sheet_1672542963.pdf
Verilog_Cheat_sheet_1672542963.pdf
 
Verilog Cheat sheet-2 (1).pdf
Verilog Cheat sheet-2 (1).pdfVerilog Cheat sheet-2 (1).pdf
Verilog Cheat sheet-2 (1).pdf
 
Vhdl lab manual
Vhdl lab manualVhdl lab manual
Vhdl lab manual
 
Vhdl new
Vhdl newVhdl new
Vhdl new
 
Session 02 _rtl_design_with_vhdl 101
Session 02 _rtl_design_with_vhdl 101Session 02 _rtl_design_with_vhdl 101
Session 02 _rtl_design_with_vhdl 101
 

Recently uploaded

space technology lecture notes on satellite
space technology lecture notes on satellitespace technology lecture notes on satellite
space technology lecture notes on satellite
ongomchris
 
Final project report on grocery store management system..pdf
Final project report on grocery store management system..pdfFinal project report on grocery store management system..pdf
Final project report on grocery store management system..pdf
Kamal Acharya
 
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptx
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxCFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptx
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptx
R&R Consult
 
Fundamentals of Electric Drives and its applications.pptx
Fundamentals of Electric Drives and its applications.pptxFundamentals of Electric Drives and its applications.pptx
Fundamentals of Electric Drives and its applications.pptx
manasideore6
 
ASME IX(9) 2007 Full Version .pdf
ASME IX(9)  2007 Full Version       .pdfASME IX(9)  2007 Full Version       .pdf
ASME IX(9) 2007 Full Version .pdf
AhmedHussein950959
 
The role of big data in decision making.
The role of big data in decision making.The role of big data in decision making.
The role of big data in decision making.
ankuprajapati0525
 
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdf
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdfHybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdf
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdf
fxintegritypublishin
 
English lab ppt no titlespecENG PPTt.pdf
English lab ppt no titlespecENG PPTt.pdfEnglish lab ppt no titlespecENG PPTt.pdf
English lab ppt no titlespecENG PPTt.pdf
BrazilAccount1
 
AKS UNIVERSITY Satna Final Year Project By OM Hardaha.pdf
AKS UNIVERSITY Satna Final Year Project By OM Hardaha.pdfAKS UNIVERSITY Satna Final Year Project By OM Hardaha.pdf
AKS UNIVERSITY Satna Final Year Project By OM Hardaha.pdf
SamSarthak3
 
ethical hacking-mobile hacking methods.ppt
ethical hacking-mobile hacking methods.pptethical hacking-mobile hacking methods.ppt
ethical hacking-mobile hacking methods.ppt
Jayaprasanna4
 
Cosmetic shop management system project report.pdf
Cosmetic shop management system project report.pdfCosmetic shop management system project report.pdf
Cosmetic shop management system project report.pdf
Kamal Acharya
 
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdfTop 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
Teleport Manpower Consultant
 
Architectural Portfolio Sean Lockwood
Architectural Portfolio Sean LockwoodArchitectural Portfolio Sean Lockwood
Architectural Portfolio Sean Lockwood
seandesed
 
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
bakpo1
 
weather web application report.pdf
weather web application report.pdfweather web application report.pdf
weather web application report.pdf
Pratik Pawar
 
power quality voltage fluctuation UNIT - I.pptx
power quality voltage fluctuation UNIT - I.pptxpower quality voltage fluctuation UNIT - I.pptx
power quality voltage fluctuation UNIT - I.pptx
ViniHema
 
block diagram and signal flow graph representation
block diagram and signal flow graph representationblock diagram and signal flow graph representation
block diagram and signal flow graph representation
Divya Somashekar
 
Runway Orientation Based on the Wind Rose Diagram.pptx
Runway Orientation Based on the Wind Rose Diagram.pptxRunway Orientation Based on the Wind Rose Diagram.pptx
Runway Orientation Based on the Wind Rose Diagram.pptx
SupreethSP4
 
H.Seo, ICLR 2024, MLILAB, KAIST AI.pdf
H.Seo,  ICLR 2024, MLILAB,  KAIST AI.pdfH.Seo,  ICLR 2024, MLILAB,  KAIST AI.pdf
H.Seo, ICLR 2024, MLILAB, KAIST AI.pdf
MLILAB
 
Standard Reomte Control Interface - Neometrix
Standard Reomte Control Interface - NeometrixStandard Reomte Control Interface - Neometrix
Standard Reomte Control Interface - Neometrix
Neometrix_Engineering_Pvt_Ltd
 

Recently uploaded (20)

space technology lecture notes on satellite
space technology lecture notes on satellitespace technology lecture notes on satellite
space technology lecture notes on satellite
 
Final project report on grocery store management system..pdf
Final project report on grocery store management system..pdfFinal project report on grocery store management system..pdf
Final project report on grocery store management system..pdf
 
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptx
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxCFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptx
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptx
 
Fundamentals of Electric Drives and its applications.pptx
Fundamentals of Electric Drives and its applications.pptxFundamentals of Electric Drives and its applications.pptx
Fundamentals of Electric Drives and its applications.pptx
 
ASME IX(9) 2007 Full Version .pdf
ASME IX(9)  2007 Full Version       .pdfASME IX(9)  2007 Full Version       .pdf
ASME IX(9) 2007 Full Version .pdf
 
The role of big data in decision making.
The role of big data in decision making.The role of big data in decision making.
The role of big data in decision making.
 
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdf
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdfHybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdf
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdf
 
English lab ppt no titlespecENG PPTt.pdf
English lab ppt no titlespecENG PPTt.pdfEnglish lab ppt no titlespecENG PPTt.pdf
English lab ppt no titlespecENG PPTt.pdf
 
AKS UNIVERSITY Satna Final Year Project By OM Hardaha.pdf
AKS UNIVERSITY Satna Final Year Project By OM Hardaha.pdfAKS UNIVERSITY Satna Final Year Project By OM Hardaha.pdf
AKS UNIVERSITY Satna Final Year Project By OM Hardaha.pdf
 
ethical hacking-mobile hacking methods.ppt
ethical hacking-mobile hacking methods.pptethical hacking-mobile hacking methods.ppt
ethical hacking-mobile hacking methods.ppt
 
Cosmetic shop management system project report.pdf
Cosmetic shop management system project report.pdfCosmetic shop management system project report.pdf
Cosmetic shop management system project report.pdf
 
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdfTop 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
 
Architectural Portfolio Sean Lockwood
Architectural Portfolio Sean LockwoodArchitectural Portfolio Sean Lockwood
Architectural Portfolio Sean Lockwood
 
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
一比一原版(SFU毕业证)西蒙菲莎大学毕业证成绩单如何办理
 
weather web application report.pdf
weather web application report.pdfweather web application report.pdf
weather web application report.pdf
 
power quality voltage fluctuation UNIT - I.pptx
power quality voltage fluctuation UNIT - I.pptxpower quality voltage fluctuation UNIT - I.pptx
power quality voltage fluctuation UNIT - I.pptx
 
block diagram and signal flow graph representation
block diagram and signal flow graph representationblock diagram and signal flow graph representation
block diagram and signal flow graph representation
 
Runway Orientation Based on the Wind Rose Diagram.pptx
Runway Orientation Based on the Wind Rose Diagram.pptxRunway Orientation Based on the Wind Rose Diagram.pptx
Runway Orientation Based on the Wind Rose Diagram.pptx
 
H.Seo, ICLR 2024, MLILAB, KAIST AI.pdf
H.Seo,  ICLR 2024, MLILAB,  KAIST AI.pdfH.Seo,  ICLR 2024, MLILAB,  KAIST AI.pdf
H.Seo, ICLR 2024, MLILAB, KAIST AI.pdf
 
Standard Reomte Control Interface - Neometrix
Standard Reomte Control Interface - NeometrixStandard Reomte Control Interface - Neometrix
Standard Reomte Control Interface - Neometrix
 

Vhdl

  • 1. 1 Refer to VHDL code and identify the logic LIBRARYieee; USE ieee.std_logic_1164.all; ENTITYpriority IS PORT( w : INSTD_LOGIC_VECTOR(3DOWNTO0); y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); z : OUT STD_LOGIC); END priority; ARCHITECTUREBehavior OF priority IS BEGIN PROCESS ( w ) BEGIN IF w(3) = '1' THEN y <= "11" ; ELSIF w(2) ='1' THEN y <= "10" ; ELSIF w(1) ='1' THEN y <= "01" ; ELSE y <= "00" ; END IF ; END PROCESS ; z <= '0' WHEN w = "0000" ELSE'1'; END Behavior ; 2-bitpriorityencoder 2 Among the VHDL features, which language statements are executed at the same time in parallel flow? a. Concurrent b. Sequential c. Net-list d. Test-bench concurrent 3 In Net-list language, the net-list is generated _______synthesizing VHDL code. a. Before b. At the time of (during)
  • 2. c. After d. None of the above After 4 Which data type in VHDL is non synthesizable & allows the designer to model the objects of dynamic nature? a. Scalar b. Access c. Composite d. File access 5 In the simulation process, which step specifies the conversion of VHDL intermediate code so that it can be used by the simulator? a. Compilation b. Elaboration c. Initialization d. Execution Elaboration 6 Hold time is defined as the time required for the data to ________ after the triggering edge of clock. a. Increase b. Decrease c. Remain stable d. All of the above remainstable 7 An Antifuse programming technology is predominantly associated with _____. a. SPLDs b. FPGAs c. CPLDs d. All of the above FPGAs 8 In fusible link technologies, the undesired fuses are removed by the pulse application of _____voltage & current to device input. a. Low b. Moderate
  • 3. c. High d. All of the above High 9 The utilization of CAD tools for drawing timing waveform diagram and transforming it into a network of logic gates is known as ________. a. Waveform Editor b. Waveform Estimator c. Waveform Simulator d. Waveform Evaluator waveformeditor 10 State box without decision and conditional box is A. ASM block B. defined block C. simple block D. both a and b Simple block 11 Table that is not a part of asynchronous analysis procedure is a. transition table b. state table c. flow table d. excitation table d