Successfully reported this slideshow.
We use your LinkedIn profile and activity data to personalize ads and to show you more relevant ads. You can change your ad preferences anytime.

VHDL Part 4

2,119 views

Published on

Lec 13

Published in: Education
  • Be the first to comment

VHDL Part 4

  1. 1. FunctionsA function accepts a number of arguments and returns a result.Each of the arguments and the result in a function definition orfunction call have a predetermined type.When a function is called, the actual parameters in the function callare substituted for the formal parametersWhen a function is called from within an architecture, a value ofthe type return-type is returned in place of the function callA function may define its own local types, constants, variables andnested functions and proceduresThe keywords begin and end enclose a series of “sequentialstatements” that are executed when the function is called 1
  2. 2. A simple exampleentity Inhibit is -- a.k.a. “but-not” as in “X but not Y” port (X,Y: in BIT; Z: out BIT);end Inhibit; -- end of entity declarationarchitecture Inhibit_arch of Inhibit isbegin Z <= ‘1’ when X=‘1’ and Y=‘0’ else ‘0’;end Inhibit_arch -- end of architecture declaration 2
  3. 3. But-not gate using a function architecture Inhibit_archf of Inhibit is function ButNot (A,B: bit) return bit is begin if B = ‘0’ then return A; else return ‘0’; end if; end ButNot; begin Z <= ButNot(X,Y); end Inhibit_archf 3
  4. 4. LibrariesA VHDL library is a place where the compiler stores information about aparticular design project, including intermediate files that are used in theanalysis, simulation and synthesis of the design.Library location is implementation-dependentFor a given VHDL design, the compiler automatically creates and uses alibrary named “work”.When compiler analyzes each file in the design, it puts the results there.A complete VHDL design usually has multiple files, each containingdifferent design units including entities and architectures.Not all the information needed in a design may be in the “work” library. 4
  5. 5. LibrariesA designer may rely on common definitions or functional modulesacross a family of different projects.Even small projects may use a standard library such as the onecontaining IEEE standard definitionsThe designer can specify the name of such a library using alibrary clause at the beginning of the design file.For example one can specify the IEEE library aslibrary IEEE;Specifying a library name in a design gives it access to anypreviously analyzed entities and architectures stored in the library,but does not give access to type definitions and the like. This isthe function of “packages” and “use clauses” 5
  6. 6. Library statement in VHDLlibrary ieee;-- needed if you want to use the ieee librarylibrary unisim;-- will see this in Xilinx-generated fileslibrary work;-- implicitly included in every VHDL file 6
  7. 7. What’s in a package? A package is a file containing definitions of “objects” that can be used in other programs Is an ADA concept Like the entity-architecture pair, the package is another precursor to the OOP idea! “object” here means signals, types, constants, functions, procedures, components declarations, etc. NOT objects as in OOP. The kind of objects are signal, type, constant, function, procedure, and component declarations 7
  8. 8. PackagesSignals that are defined in a package are “global” signals,available to any VHDL entity that uses the packageTypes and constants defined in a package are known in anyfile that uses the packageLikewise functions and procedures defined in a package canbe called in files that use the package and components can be“instantiated” in architectures that use the package.To use a package you say “use” … for example:use ieee.std_logic_1164.all; -- use alldefinitions in pkguse ieee.std_logic_1164.std_ulogic -- usejust def std_ulogic type 8
  9. 9. PackagesA design can use a package by including a use clause at thebeginning of the design fileTo use all the definitions in the IEEE standard 1164 package onewould writeuse ieee.std_logic_1164.all;Here “ieee” is the name of the library which has previously beengiven in the library clauseWithin the library , the file named “std_logic_1164” containsthe desired definitions and the suffix “all” tells the compiler to useall of the definitions in this filePackage is not limited to standard bodies, anyone can write apackage using the proper syntax 9
  10. 10. VHDL Design Styles VHDL Design Styles dataflow structural behavioral Concurrent Components and Sequential statements statements interconnects • Registers • State machines • Test benches Subset most suitable for synthesis 10
  11. 11. VHDL Example Entity declaration for the 2 to 1 MUXENTITY mux2_1 IS PORT (in0, in1, sel: IN STD_LOGIC; yout: OUT STD_LOGIC);END mux2_1; 11
  12. 12. VHDL Example Logic circuit for a 2-1 MUX device Helpful for understanding architecturein1sel youtin0 12
  13. 13. Behavioral architecture for the 2 to 1 MUXARCHITECTURE a1 OF mux2_1 IS P1: PROCESS (sel, in0, in1) BEGIN IF (sel = ‘0’) THEN yout <= in0; ELSE yout <= in1; END IF; END P1;END a1; in1 sel yout in0 13
  14. 14. Structural architecture for the 2 to 1 MUXARCHITECTURE a2 OF mux2_1 IS SIGNAL sel_not, in0_and, in1_and: STD_LOGIC; COMPONENT OR_GATE PORT(x,y: IN STD_LOGIC; z: OUT STD_LOGIC); COMPONENT AND_GATE PORT (x,y: IN STD_LOGIC; z: OUT STD_LOGIC); COMPONENT INV_GATE PORT (x: IN STD_LOGIC; z: OUT STD_LOGIC);BEGIN U1: AND_GATE PORT MAP (in0, sel_not, in0_and); U2: AND_GATE PORT MAP (in1, sel, in1_and); U3: INV_GATE PORT MAP (sel, sel_not); U4: OR_GATE PORT MAP (in0_and, in1_and, yout);END a2; in1 In1_and sel yout in0 In0_and sel_not 14
  15. 15. Dataflow architecture for the 2 to 1 MUXARCHITECTURE a3 OF mux2_1 ISBEGIN yout <= ((in0 AND NOT(sel)) OR (in1 AND sel));END a3; In1 sel yout In0 15
  16. 16. Half Adder Circuit Looking at the truth table for a half adder, it is easy to visualize the circuit AB CS A S B C 16
  17. 17. Full Adder Circuit The circuit at right shows a half adder full adder constructed from two half adders. XOR generates the sum output AND generates the carry output half adder [ ]C = ( A ⋅ B + A ⋅ B ) ⋅ C ′ + ( A ⋅ B ) = ( A ⋅ B ⋅ C ′) + ( A ⋅ B ⋅ C ′) + ( A ⋅ B ) = ( A ⋅ C ′) + ( B ⋅ C ′) + ( A ⋅ B )S = A ⊕ B ⊕ C′ 17
  18. 18. -- Dataflow model for a full adder circuit-- Library Statement declares the ieee synthesis libraryLIBRARY ieee;USE ieee.std_logic_1164.ALL;-- Entity declarationENTITY fulladder IS PORT(Ain, Bin, Cin: IN STD_LOGIC; Cout, Sout: OUT STD_LOGIC);END fulladder;-- Architecture defines the function-- In this case the function is defined using BooleanequationsARCHITECTURE dataflow OF fulladder ISBEGIN -- Concurrent Signal Assignment Statements Sout <= Ain XOR Bin XOR Cin; Cout <= (Ain AND Bin) OR (Ain AND Cin) OR (Bin AND Cin);END dataflow;
  19. 19. -- Structural architecture is defined by a circuitARCHITECTURE structural OF fulladder ISCOMPONENT AND2 PORT( A, B: IN STD_LOGIC; F: OUT STD_LOGIC);END COMPONENT;COMPONENT OR3 PORT( A, B, C: IN STD_LOGIC; F: OUT STD_LOGIC);END COMPONENT;COMPONENT XOR2 PORT( A, B: IN STD_LOGIC; F: OUT STD_LOGIC);END COMPONENT;SIGNAL AXB, AB, BC, AC: STD_LOGIC;BEGIN F1: XOR2 port map (Ain, Bin, AXB); --Port Map Statements F2: XOR2 port map (AXB, Cin, Sout); F3: AND2 port map (Ain, Bin, AB); F4: AND2 port map (Bin, Cin, BC); F5: AND2 port map (Ain, Cin, AC); F6: OR3 port map (AB, BC, AC, Cout);END structural;
  20. 20. Binary Addition: 4-Bit NumbersThe following example illustrates the addition of two4-bit numbers A(A3A2A1A0) and B(B3B2B1B0): 20
  21. 21. Binary Addition: 4-Bit NumbersThe addition can be split-up in bitslicesEach slice performs the addition ofthe bits Ai, Bi and the Carry-in bit Ci Ci <= carry-out bit of the previous sliceEach slice is simply a full adder 21
  22. 22. 4-Bit Binary AdderCircuit for a 4-bit parallel binary adder constructedfrom full adder building blocks 22
  23. 23. LIBRARY ieee;USE ieee.std_logic_1164.ALL;-- VHDL model of a 4-bit adder using four full addersENTITY four_bit_adder_st ISPORT (A, B : IN STD_LOGIC_VECTOR(3 downto 0); SUM : OUT STD_LOGIC_VECTOR(3 downto 0); CIN : IN STD_LOGIC; COUT : OUT STD_LOGIC);END four_bit_adder_st; Cin Cout Internal Signals
  24. 24. -- The architecture is a structural one.ARCHITECTURE structural OF four_bit_adder_st IS-- First all the components are declared. The full adder-- is declared only once, even though it will be used 4times.COMPONENT fulladder PORT(Ain, Bin, Cin: IN STD_LOGIC; Cout, Sout: OUT STD_LOGIC);END COMPONENT;-- The full adders are connected by carry signals. These-- must be declared also.SIGNAL C : STD_LOGIC_VECTOR(1 to 3);-- Port map statements are used to define full adder-- instances and how they are connected.BEGIN F1: fulladder port map (A(0),B(0),CIN,C(1),SUM(0)); F2: fulladder port map (A(1),B(1),C(1),C(2),SUM(1)); F3: fulladder port map (A(2),B(2),C(2),C(3),SUM(2)); F4: fulladder port map (A(3),B(3),C(3),COUT,SUM(3));END structural;
  25. 25. -- The architecture in this case is a dataflow oneARCHITECTURE dataflow OF four_bit_add_df IS-- Again there will be internal carry signals that are not-- inputs or outputs. These must be declared as signals.SIGNAL C : STD_LOGIC_VECTOR(1 to 3);-- Concurrent signal assignments can be used to describe-- each of the 4 outputs and the carry signals.BEGIN SUM(0) <= A(0) XOR B(0) XOR Cin; C(1) <= (A(0) AND B(0)) OR (A(0) AND Cin) OR (B(0) AND Cin); SUM(1) <= A(1) XOR B(1) XOR C(1); C(2) <= (A(1) AND B(1)) OR (A(1) AND C(1)) OR (B(1) AND C(1)); SUM(2) <= A(2) XOR B(2) XOR C(2); C(3) <= (A(2) AND B(2)) OR (A(2) AND C(2)) OR (B(2) AND C(2)); SUM(3) <= A(3) XOR B(3) XOR C(3); COUT <= (A(3) AND B(3)) OR (A(3) AND C(3)) OR (B(3) AND C(3));END dataflow;
  26. 26. D latch with an async clear and level sensitivitylibrary IEEE;use IEEE.Std_logic_1164.all;entity latch_wc is port (CLK, D, CLR: in Std_logic; Q: out Std_logic);end latch_wc; CLRArchitecture design of latch_wc isbegin process (CLK, D, CLR) begin if CLR = 1 then -- CLR active High Q <= 0; elsif CLK = 1 then -- CLK active High Q <= D; -- note that Q is not assigned a value for CLK = 0 end if; end process;end design; 26
  27. 27. D latch with asynch clear and rising-edge triggeredlibrary IEEE;use IEEE.Std_logic_1164.all;entity dff_wac is port (CLK, D, CLR: in Std_logic; Q: out Std_logic); CLRend dff_wac;Architecture design of dff_wac isbegin process (CLK, D, CLR) begin if CLR = 1 then -- asynchronous CLR active High Q <= 0; elsif (CLKevent and CLK=1) then Q <= D; -- CLK rising edge, CLKevent and CLK = 1 can be replaced by the "function" rising_edge (CLK) end if; end process;end design; 27
  28. 28. T f-f with an asynch clear and rising edge triggeredlibrary IEEE;use IEEE.Std_logic_1164.all;entity t_ff is port (T, CLK, CLR: in std_logic; Q: buffer std_logic);end t_ff; CLRarchitecture design of t_ff isbegin process (CLK, CLR, T) begin if (CLR = 1) then Q <= 0; elsif rising_edge (CLK) then case T is when 0 => Q <= Q; when 1 => Q <= not Q; when others => Q <= 0; end case; end if; 28 end process;
  29. 29. JK f-f with an asynch reset and rising edge triggeredlibrary IEEE;use IEEE.Std_logic_1164.all;entity JK_FF isport (clock, J, K, reset: in std_logic; reset Q, Qbar: out std_logic);end JK_FF;architecture behv of JK_FF is signal state: std_logic; -- define the useful signals here signal input: std_logic_vector(1 downto 0); 29
  30. 30. JK f-f with an asynch reset and rising edge triggeredbegin input <= J & K; -- combine inputs into 2-bit vector p: process(clock, reset) is begin if (reset=1) then state <= 0; elsif (rising_edge(clock)) then case (input) is -- compare to the truth table when "11" => state <= not state; when "10" => state <= 1; when "01" => state <= 0; when others => null; end case; end if; end process; -- concurrent statements Q <= state; Qbar <= not state;end behv; reset 30
  31. 31. JK f/f with enable using if-then-else structurelibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity JK_FF_VHDL is port( J,K: in std_logic; Reset: in std_logic; Clock_enable: in std_logic; Clock: in std_logic; Output: out std_logic);end JK_FF_VHDL; 31
  32. 32. JK f/f with enable using if-then-else structurearchitecture Behavioral of JK_FF_VHDL issignal temp: std_logic;begin process (Clock) begin if Clockevent and Clock=1 then if Reset=1 then temp <= 0; elsif Clock_enable =1 then if (J=0 and K=0) then temp <= temp; elsif (J=0 and K=1) then temp <= 0; elsif (J=1 and K=0) then temp <= 1; elsif (J=1 and K=1) then temp <= not(temp); end if; end if; end if; end process; Output <= temp;end Behavioral; 32

×