This document provides an overview of a course on Synthesis and Optimization of Digital Circuits. The course aims to present automatic logic synthesis techniques for computer-aided design of very large-scale integrated circuits and systems. The course will broadly survey the state of the art in logic-level synthesis and optimization techniques for combinational and sequential circuits. It will cover various representations of Boolean functions and their applications in logic synthesis. Students will implement Verilog and C/C++ projects focusing on optimization and synthesis methods discussed in class.

1. SYNTHESIS & OPTIMIZATION
OF DIGITAL CIRCUITS
Prabhavathi P,
Associate Professor,
Department of ECE
(14EVE41)
B N M Institute of Technology,
12th Main, 27th Cross, BSK II Stage,
Banashankari, Bengaluru- 560070
Karnataka, India

2. SYNTHESISANDOPTIMIZATIONOFDIGITALCIRCUITS
-14EVE41
Motivation.-Microelectronics , Microeconomics
Introduction
Design Challenges
Design Process and Design Styles
Microelectronics and Microeconomics
Synthesis and Optimization – Automated Synthesis
Design Space and Design Evaluation Space
Page 8
Page 14
Page 19
Page 22
Page 25
Page 27
Page 42
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Outline
Course objective and Outcomes Page 3

3. Course description
Subject: Synthesis and Optimization of Digital
circuits
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Subject Code 14EVE41 Exam
Hours
03
No. of Lecture Hours
/week
04 IA
Marks
50
Total no. of Lecture
Hours
50 Exam
Marks
100
Teaching Scheme Credits Examination Marks
L T P External
exam
Tutorial Internal
Tests
Total
4 2 0 100 20 30 150

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-14EVE41
Course description
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The aim of this course is to present automatic logic synthesis techniques
for computer-aided design (CAD) of very large-scale integrated (VLSI)
circuits and systems. This is a highly active research area, enabling the
design of increasingly complex digital systems.
This course will broadly survey the state of the art, and give a detailed
study of various problems, pertaining to the logic-level synthesis of VLSI
circuits and systems, including: two-level Boolean network
optimization, multi-level Boolean network optimization, technology
mapping for library-based designs and field-programmable gate-array
(FPGA) designs, and state-assignment and re-timing for sequential circuits.
The course will also cover various representations of Boolean
functions, such as binary decision diagrams (BDDs), and discuss their
applications in logic synthesis
NOTE: Students will be expected to implement a variety of Verilog and C/C++ projects
throughout the semester. While specific programming assignments may change with the course
offering, projects typically focus on the implementation of optimization and synthesis methods
discussed in class, as well as the RTL design.

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-14EVE41
Course Objectives
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To introduce students to basic optimization techniques used in circuits
design
To introduce students to advanced tools and techniques in digital
systems design. These include Hardware Modeling and Compilation
Techniques.
To introduce in details Logic-Level synthesis and optimization
techniques for combinational and sequential circuits.
To introduce students to Library binding algorithms to achieve
implementations with specific cell libraries.
To get an idea about the algorithms used in building commercial
computer-aided design tools like Synopsis, Cadence, etc.
To build sufficient background such that one can understand research
papers in the area
To understand why these algorithms are considered computationally
expensive and why commercial tools are so costly

6. SYNTHESISANDOPTIMIZATIONOFDIGITALCIRCUITS
-14EVE41
Reference Books
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1. Giovanni De Micheli, “Synthesis and Optimization of Digital
Circuits”, Tata McGraw-Hill, 2003.
2. Srinivas Devadas, Abhijit Ghosh, and Kurt Keutzer, “Logic
Synthesis”, McGraw-Hill, USA, 1994.
3. Neil Weste and K. Eshragian, “Principles of CMOS VLSI Design:
A System Perspective”, 2nd edition, Pearson
Education(Asia) Pvt. Ltd., 2000.
4. Kevin Skahill, “VHDL for Programmable Logic”, Pearson
Education(Asia) Pvt. Ltd., 2000

7. SYNTHESISANDOPTIMIZATIONOFDIGITALCIRCUITS
Outcomes of the course
At the end of the course the student will be able to
1. Understand the process of synthesis and optimization in a
top down approach for digital circuits models using
HDLs.
2. Understand the terminologies of graph theory and its
algorithms to optimize a Boolean equation
3. Apply different two level and multilevel optimization
algorithms for combinational circuits
4. Apply the different sequential circuit optimization
methods using state models and network models
5. Apply different scheduling algorithms with resource
binding and without resource binding for pipelined
sequential circuits and extended sequencing models.
6. Understand the role of verification and testing using
CAD as another dimension of optimization.
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8. Agenda
•Introduction
– Microelectronics
– Micro “economics”
– What is “design”?
– Design styles
– Computer Aided Design
• Techniques for Digital Synthesis
– Architectural-Level Synthesis
– Logic-Level Synthesis
– Geometric Synthesis
• Logic Synthesis: an Overview
• Design Space and Optimization
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9. INTRODUCTION
Introduction
Very Large Scale Integration (VLSI)
Computer-Aided Design
Design Process
Design Styles
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10. Introduction - VLSI
•IC technology has progressed tremendously over 40 yrs.
– Moore‟s Law [SSI - „60, MSI - „70, VLSI - „90, ?? - ‟00]
Costs have increased tremendously as well
– Larger capital investment due to cost of refining precision
– Larger scale increases effort to achieve zero-defect design
• ICs are nearly impossible to repair
• The design must be correct (and manufacturing defects limited)
– Design and manufacturing costs must be recovered via sales
• Few designs do enjoy a high volume of sales or long life
• Many systems require specialized devices (ASICs) – few hold a
significant market share individually
• Improvement of technology causes immediate obsolescence
• Microelectronics is the Enabling Technology
(Micro-Electro-Mechanics more recently)
• Design Automation is the Enabling Tool
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SYNTHESISANDOPTIMIZATIONOFDIGITALCIRCUITS

11. DESIGNTECHNOLOGYCHALLENGES
Design Technology Challenges
•Productivity
• Design meaningfully with huge number of transistors
•Power
• Design under the single-chip package power limit
•Manufacturing Integration
•Interference
• Resource-efficient communication and synchronization
•Error-Tolerance
• Relaxation of the requirement of 100% correctness
•Source: ITRS 2001 Edition
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12. COMPUTERAIDEDDESIGN
Computer Aided Design
•Role
•History
•Difficulty: size, NP-hard
•Market and Key Players
• Tens of billions $ industry
• 4 major CAD companies
• CAD groups in large companies
• Universities with strong CAD groups
•Conferences and Journals
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13. BRIEFHISTORYOFCAD
CAD - History
13
•1950-1965
• manual design, impractical algorithms (even for MSI).
•1965-1975
• physical design tools for automatic layout of gate arrays
• IBM: Engineering Design System
• AT&T: LTX system for standard cells
• logic design tools:
• IBM‟s Mini: 2-level heuristic minimizer
• Espresso: (IBM and Berkeley) PLA-based design
•1975-1985
• placement and routing, technology mapping, multi-level
optimization
• theoretical development in physical design
•1985-
• performance/power driven design methodologies
• parallel algorithm, graph theory, combinatorial optimization
problems
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14. Historical Perspective
• The earliest CAD tools targeted automatic layout at physical
level of abstraction (1960s, Engineering Design System, IBM).
• As Large-scale integration (LSI) became possible, the CAD-tools
shifted to transistor- and logic-levels of abstraction
(MINI, IBM, 1970s)
• Logic synthesis tools became popular in the early 1980s, as VLSI
technology matured (Multiple-level Interactive System
MIS, Berkeley University)
• The early high-level synthesis systems were not coupled with
logic synthesis tools (Alert, IBM)
• The first fully integrated systems were IBM‟s Yorktown Silicon
Compiler and the CATHEDRAL system developed at the
Catholic University of Leuven, Belgium.
• Fully integrated CAD system are normally developed for a
specific application and implementation styles, e.g.
CATHEDRAL transforms behavioral model of a particular class
of designs (digital signal processors) into circuits with particular
design styles
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15. Design Challenges
• Systems are becoming huge, design schedules are
getting tighter
– 20 Mio gates becoming common for ASICs
– 0.4 Mio lines of C-code to describe system behavior
– 5 Mi lines of RTL code
• Design teams are getting very large for big projects
– several hundred people
– differences in skills
– concurrent work on multiple levels
– management of design complexity and communication
very difficult
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16. Stages of IC design
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17. Focus of this Course
• CAD tools for synthesis and verification at
logic level of abstraction
• Theory behind: functions representation and
manipulation
– representation data structures
– manipulation algorithms
• In-depth course:
– you should be able create a small CAD-tool
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18. DESIGNPROCESS
Design Process
•System Specification
• size, speed, power, and functionality factors to consider:
performance, functionality, physical dimension (area)
•Functional Design
• Determine the timing diagram and other relationships between sub-units.
•Logic Design
• Derive and test the functionality, usually in boolean expressions and graphic
description minimization (or optimization) to achieve the smallest logic design
•Circuit Design
• Develop a circuit representation (circuit diagram) based on the logic design
•Physical Design
• Geometric representation of circuit components, layout and connection
(partitioning, floor-planning and placement, routing, compaction), most complex
and time consuming process
•Fabrication
• Preparation of wafer (the silicon base for the circuit), deposition, and diffusion of
various materials on the wafer according to the layout description
•Packaging
• Packaging, testing, and debugging: each chip is packaged and tested to ensure that
it meets all the design specifications.
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19. Design Styles
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Semicustom
Cell based Array based
Standard
cells
Hierarchical
Cells
Macro Cells
Generators
Memory
PLA
Sparse logic
Gate Matrics
Pre-diffused
Gate arrays
Sea of Gates
Compacted arrays
Prewired
Anti-fuse based
Memory based

20. Comparison of Design styles
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Custom Cell based Pre
diffused
Prewired
Density Very high High High Medium - low
Performance Very high High High Medium - low
Flexibility Very high High Medium Low
Design Time Very long Short Short Very short
Manufacturing time Medium Medium Short Very short
Cost – Low volume Very high High High Low
Cost – High Volume Low Low Low High

21. What is a microelectronic component?
• Devices which exploit the properties of semiconductor
materials
• Constructed by patterning a substrate and locally
modifying its properties to shape “wires” and logical
“devices”
• Complex functions are “integrated” into one physical
package
• Fabrication is very complex Microelectronic
components enable “smart” system
Microelectronic components enable “smart” systems
• Prevalent in modern systems
• Failures are not taken well - most applications are “critical”
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Introduction - Microelectronics and Microeconomics

22. Overview: “Micro” Economics
•How can costs be reduced and net profit
increased?
– Minimize Design (and test) time Reduces both time-to-
market and designers‟ salaries
– Increase quality of design to increase fabrication yield
and provide competitive performance
• Design automation techniques provide an
effective means for designing economically
viable products
– Carrying out a full design w/o errors is increasingly
difficult w/o systematic techniques to handle data
– CAD techniques tend to focus on Digital Synchronous
circuits as they represent the vast majority of circuits in
the market
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23. Overview of Synthesis and Optimization
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Scheduling Sharing
Boolean
Function
Minimization
Boolean
Relation
Minimization
State
Minimization
Graph
Theory
Boolean
Algebra
Synthesis & Optimization
Architectural Level Logic Level
Architectural Level
SatisfiabilityCoveringColoring

24. Overview: What is “Design”?
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25. Automated Synthesis
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26. Automated Synthesis
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27. Example of Architectural view
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Source: Giovanni De Micheli, “Synthesis and Optimization of
Digital Circuits”, Tata McGraw-Hill, 2003.

28. Example of Logic Synthesis
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Source: Giovanni De Micheli, “Synthesis and Optimization of
Digital Circuits”, Tata McGraw-Hill, 2003.

29. High-level Synthesis
•High-level (Architectural-level) synthesis deals with
the transformation of an abstract model of behavior
into a model consisting of standard functional units
• Goal: to construct the macroscopic structure of a
circuit
• Input: an abstract model of behavior
- Common Abstract Models: HDLs, State
diagrams, ASM charts, Sequencing graphs or
Control/Data-flow graphs.
• Output: a structural view of the circuit, in particular of
its Datapath, and a logic-level specification of its
control unit
- often referred to as the register-transfer level or
macro-module model
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30. High-level Synthesis
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31. High-level Synthesis
•Measuring cost
• Evaluation Metrics: area, cycle-time (clock
period), latency, and throughput (pipelines)
• The objectives form a n-dimensional design space
• Architectural exploration is the traversal of the design
space to provide a spectrum of solutions for the
designers selection
• Generally only the resources are considered (resource
dominant)
•The fundamental architectural synthesis problem
• Explore the design space to minimize “cost” given:
• A circuit model (behavioral)
• A set of constraints (on cost)
• A set of functional resources (characterized for
area, delay, etc.)
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32. Why Logic Level?
• Logic-level synthesis is the core of today's CAD flows for
IC and system design
– course covers many algorithms and data structures that are used
in a broad range of CAD tools
– basis for other optimization techniques
– basis for functional verification techniques
• Most algorithms are computationally hard
– covered algorithms and flows are good example for approaching
hard algorithmic problems
– course covers theory as well as implementation details
– demonstrates an engineering approaches based on theoretical
solid but also practical solutions
• Very few research areas can offer this combination
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33. Logic Synthesis
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34. Typical Logic Synthesis Flow
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35. Objectives of Logic Synthesis
• Minimize area
– in terms of literal count, gate count, register count, etc.
• Minimize power
– in terms of switching activity in individual
gates, blocks, etc.
• Maximize performance
– in terms of maximal clock frequency of
synchronous systems,throughput for
asynchronous systems
• Any combination of the above
– combined with different weights
– formulated as a constraint problem
• “minimize area for a clock speed > 300MHz”
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36. Constraints on Synthesis
•Given implementation style:
– two-level implementation (PLA)
– multi-level logic (ASIC or FPGA)
• Given performance requirements
– minimal clock speed requirement
• Given cell library
– set of cells in standard cell library
– fan-out constraints (maximum number of gates connected
to another gate)
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37. Mapping functions into gates
• One of the main steps of logic synthesis is to
map a given Boolean functions into a
combinational circuit with the minimum “cost”
• This task is VERY hard because:
– Usually, many different circuits can
implement the same function
• How to search for a “best circuit”: (1) construct
one circuit and try to improve it, or (2) directly
construct the best
• How to decide which gates to use
(AND, OR, NOT, XOR, …)
• How to evaluate “cost” (gates, variables, …)
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38. Design Space
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39. Optimization trade – off in Combinational circuits
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40. Optimization trade – off in Sequential Circuits
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Source: Giovanni De Micheli, “Synthesis and Optimization of
Digital Circuits”, Tata McGraw-Hill, 2003.

41. Synthesis and Optimization – Simplified view
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Source: Giovanni De Micheli, “Synthesis and Optimization of
Digital Circuits”, Tata McGraw-Hill, 2003.

42. Pareto Points
• Multi – criteria Optimization
• Multiple Objectives
• Pareto Point
• A Point of the design space is a Pareto Point if
there is no other point with
• At least one inferior objective
• All other objectives are inferior or equal
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