This report provides a reverse cost analysis of Samsung's Exynos 9110 application processor module used in the Samsung Galaxy Watch. The module utilizes Samsung's innovative ePLP (embedded Panel-Level Packaging) technology, which enables a package-on-package configuration with an embedded DRAM die. The ePLP module is extremely small at less than 80mm2 and includes the Exynos 9110 application processor die and a Samsung power management die embedded on a fan-out substrate with four redistribution layers. The report includes physical analysis of the package and dies, comparison to other advanced packaging technologies, manufacturing process flow analysis, and cost analysis.
Intel Foveros and TSMC 3D SoIC are competing head-to-head for high-end packaging – How will Samsung react ?More information here : https://www.i-micronews.com/products/high-end-performance-packaging-3d-2-5d-integration-2020/
2.5D heterogeneous and 3D wafer-level stacking are reshaping the packaging landscape.
More information on that report at https://www.i-micronews.com/advanced-packaging-report/product/p2-5d-3d-tsv-wafer-level-stacking-technology-market-updates-2019.html
Status of The Advanced Packaging Industry_Yole Développement reportYole Developpement
IoT driven semiconductor industry consolidation is reflecting into a highly dynamic Advanced Packaging landscape. Demand for advanced packaging and market size is increasing. Focus is turning
to integration and wafer level packages to enable a functionality driven roadmap and revive the cost/performance curve.
Samsung’s Galaxy S9 Plus Processor Packages: Samsung’s iPoP vs. Qualcomm/Shin...system_plus
Comparison of both Samsung Galaxy S9 processor packages: Samsung Exynos 9810 with new TMV Package-on-Package vs. Qualcomm Snapdragon 845 with MCeP Packaging.
More information on that report at: https://www.i-micronews.com/report/product/samsung’s-galaxy-s9-plus-processor-packages-samsung’s-ipop-vs-qualcomm-shinko-mcep.html
Status of Advanced Packaging - 2017 Report by Yole DeveloppementYole Developpement
How can advanced packaging decrease semiconductor market uncertainty and enable future semiconductor products?
From supporting technology to enabler of future semiconductor products
Future semiconductor drivers are expected to be fragmented and more diverse than in the mobile era. Scaling continues, but functionality and system level features are becoming increasingly important for product differentiation rather than raw computation power. An outlook into the future brings the Internet of Things (from end device to backbone infrastructure), including the Industrial Internet of Things, the semiconductorization of the automotive industry, 5G connectivity, augmented & virtual reality and artificial intelligence. In such an environment, advanced packaging is transforming from follower of scaling technology nodes to enabler of future semiconductor applications and products. Heterogeneous integration of multiple dies from the latest to legacy front-end nodes, involving a mixture of latest technology high density interconnects to lower cost mature interconnects, at high levels of customization is the future of packaging. Advanced packaging has direct impact on product success rates and semiconductor revenues.
More information on that report at: https://www.i-micronews.com/reports.html
Second Generation of TSMC’s Integrated Fan-Out (inFO) Packaging for the Apple...system_plus
The latest Apple application processor engine : from the stacked board to the A11, and reverse costing of TSMC's updated inFO packaging
More information on that report at http://www.systemplus.fr/reverse-costing-reports/second-generation-of-tsmcs-integrated-fan-out-info-packaging-for-the-apple-a11-found-in-the-iphone-x/
Status and Prospects for the Advanced Packaging Industry in China - 2016 Repo...Yole Developpement
Driven by a strong semiconductor market outlook and aggressive investment in advanced packaging capability fueled by strong government support, advanced packaging revenue in China is expected to reach $4.6B in 2020 at an impressive 16% CAGR.
What is driving the advanced packaging market in China?
China has the world’s largest population, and its economy will continue to grow at a high pace (more than 6%), reaching around $16T by 2020. Also, an increase in per capita income (more purchasing power) will ensure China remains a dominant market in the coming years. No business can afford to ignore China. China commands a significant market for key electronic products. In fact, over half of all key electronic products are consumed in China. In 2014, the Chinese smartphone, LCD, notebook/tablet, and wearable markets were around 81%, 63%, 71%, and 47% of the global market, respectively. The global IC market will grow by a CAGR of 4% from 2014 - 2020, while the Chinese IC market will grow by 7% over the same period. The Chinese IC market is expected to reach ~$149B by 2020, around 40% of the total IC market. There is a huge gap between China’s IC consumption and its manufacturing. In 2015, China produced only ~12.5% of the IC it consumes, and the gap between IC consumption and production is ~$91B. Currently, IC is China’s #1 import commodity, exceeding oil. China considers the IC industry to be a key strategic sector. The Chinese government is making a significant effort through funding and a national IC policy, with an aggressive growth strategy to make China an IC design and manufacturing hub. The goal by 2030 is to become the global leader in all primary IC industrial supply chain segments. This report gives an overview of China’s semiconductor ecosystem and discusses in detail the country’s advanced packaging market. This report will also describe China’s semiconductor outlook, prospects, market drivers, key players, and supply chain evolution. It will discuss at length the Chinese government’s approach to developing China’s IC industry, including details about different private funds, their objectives, and investments made to date. Overall, this report will help local and global players identify challenges and opportunities in the Chinese IC market and assist them in developing strategies to maximize their market share in China’s fast-growing IC ecosystem, particularly in advanced packaging.
Intel Foveros and TSMC 3D SoIC are competing head-to-head for high-end packaging – How will Samsung react ?More information here : https://www.i-micronews.com/products/high-end-performance-packaging-3d-2-5d-integration-2020/
2.5D heterogeneous and 3D wafer-level stacking are reshaping the packaging landscape.
More information on that report at https://www.i-micronews.com/advanced-packaging-report/product/p2-5d-3d-tsv-wafer-level-stacking-technology-market-updates-2019.html
Status of The Advanced Packaging Industry_Yole Développement reportYole Developpement
IoT driven semiconductor industry consolidation is reflecting into a highly dynamic Advanced Packaging landscape. Demand for advanced packaging and market size is increasing. Focus is turning
to integration and wafer level packages to enable a functionality driven roadmap and revive the cost/performance curve.
Samsung’s Galaxy S9 Plus Processor Packages: Samsung’s iPoP vs. Qualcomm/Shin...system_plus
Comparison of both Samsung Galaxy S9 processor packages: Samsung Exynos 9810 with new TMV Package-on-Package vs. Qualcomm Snapdragon 845 with MCeP Packaging.
More information on that report at: https://www.i-micronews.com/report/product/samsung’s-galaxy-s9-plus-processor-packages-samsung’s-ipop-vs-qualcomm-shinko-mcep.html
Status of Advanced Packaging - 2017 Report by Yole DeveloppementYole Developpement
How can advanced packaging decrease semiconductor market uncertainty and enable future semiconductor products?
From supporting technology to enabler of future semiconductor products
Future semiconductor drivers are expected to be fragmented and more diverse than in the mobile era. Scaling continues, but functionality and system level features are becoming increasingly important for product differentiation rather than raw computation power. An outlook into the future brings the Internet of Things (from end device to backbone infrastructure), including the Industrial Internet of Things, the semiconductorization of the automotive industry, 5G connectivity, augmented & virtual reality and artificial intelligence. In such an environment, advanced packaging is transforming from follower of scaling technology nodes to enabler of future semiconductor applications and products. Heterogeneous integration of multiple dies from the latest to legacy front-end nodes, involving a mixture of latest technology high density interconnects to lower cost mature interconnects, at high levels of customization is the future of packaging. Advanced packaging has direct impact on product success rates and semiconductor revenues.
More information on that report at: https://www.i-micronews.com/reports.html
Second Generation of TSMC’s Integrated Fan-Out (inFO) Packaging for the Apple...system_plus
The latest Apple application processor engine : from the stacked board to the A11, and reverse costing of TSMC's updated inFO packaging
More information on that report at http://www.systemplus.fr/reverse-costing-reports/second-generation-of-tsmcs-integrated-fan-out-info-packaging-for-the-apple-a11-found-in-the-iphone-x/
Status and Prospects for the Advanced Packaging Industry in China - 2016 Repo...Yole Developpement
Driven by a strong semiconductor market outlook and aggressive investment in advanced packaging capability fueled by strong government support, advanced packaging revenue in China is expected to reach $4.6B in 2020 at an impressive 16% CAGR.
What is driving the advanced packaging market in China?
China has the world’s largest population, and its economy will continue to grow at a high pace (more than 6%), reaching around $16T by 2020. Also, an increase in per capita income (more purchasing power) will ensure China remains a dominant market in the coming years. No business can afford to ignore China. China commands a significant market for key electronic products. In fact, over half of all key electronic products are consumed in China. In 2014, the Chinese smartphone, LCD, notebook/tablet, and wearable markets were around 81%, 63%, 71%, and 47% of the global market, respectively. The global IC market will grow by a CAGR of 4% from 2014 - 2020, while the Chinese IC market will grow by 7% over the same period. The Chinese IC market is expected to reach ~$149B by 2020, around 40% of the total IC market. There is a huge gap between China’s IC consumption and its manufacturing. In 2015, China produced only ~12.5% of the IC it consumes, and the gap between IC consumption and production is ~$91B. Currently, IC is China’s #1 import commodity, exceeding oil. China considers the IC industry to be a key strategic sector. The Chinese government is making a significant effort through funding and a national IC policy, with an aggressive growth strategy to make China an IC design and manufacturing hub. The goal by 2030 is to become the global leader in all primary IC industrial supply chain segments. This report gives an overview of China’s semiconductor ecosystem and discusses in detail the country’s advanced packaging market. This report will also describe China’s semiconductor outlook, prospects, market drivers, key players, and supply chain evolution. It will discuss at length the Chinese government’s approach to developing China’s IC industry, including details about different private funds, their objectives, and investments made to date. Overall, this report will help local and global players identify challenges and opportunities in the Chinese IC market and assist them in developing strategies to maximize their market share in China’s fast-growing IC ecosystem, particularly in advanced packaging.
Polymeric Materials for Advanced Packaging at the Wafer-Level 2018 Report by...Yole Developpement
Polymeric materials market revenue will double over the next five years.
More information on that report at : https://www.i-micronews.com/report/product/polymeric-materials-for-advanced-packaging-at-the-wafer-level.html
In-depth physical and cost analysis of Samsung’s ‘1y-nm’ low power DRAM.
More information: https://www.systemplus.fr/reverse-costing-reports/samsung-lpddr5-12gb-mobile-memory/
Fan-Out and Embedded Die: Technologies & Market Trends 2015 Report by Yole De...Yole Developpement
Fan-Out and Embedded Die: Two promising Wafer/Panel-Level-Packaging technologies. What are the next steps for the growth?
Fan-Out Wafer Level Packaging is already in high-volume – but it’s about to grow even more strongly
Fan-Out Wafer Level Packaging (FOWLP) started volume commercialization in 2009/2010 and started promisingly, with initial push by Intel Mobile. However, it was limited to a narrow range of applications – essentially single die packages for cell phone baseband chips – reaching its limit in 2011. In 2012 big fab-less wireless/mobile players started slowly volume production after qualifying the technology...
Advanced Substrates Overview: From IC Package to Board - 2017 Report by Yole ...Yole Developpement
How can advanced substrates and boards bridge the gap created by front-end scaling?
Advanced substrates as a key enabler of future products and markets
In an uncertain, transformative semiconductor market, advanced packaging is one of the key technologies offering stability and a long-term solution. On one hand it can adapt to product diversification, offering more functionality, system integration, and performance, as well as potentially lower manufacturing cost; and on the other hand it can adhere to future scaling requirements. Advanced substrates are the key interconnect component of advanced packaging architectures and are critical in enabling future products and markets. For this reason, Yole has established this stand-alone dedicated advanced substrate activity, focused on exploring the market and technologies of PCBs, package substrates and RDLs. This first report will serve as an overview of advanced substrate technologies, markets, and supply chain, to be supported by subsequent in-depth reports.
Today’s advanced substrates in volume are Flip Chip (FC) substrates, 2.5D/3D TSV assemblies, and thin-film RDLs (Fan-Out WLP, or “FOWLP”) below an L/S resolution of 15/15 um and with transition below L/S < 10/10 um. These advanced substrates are traditionally linked to higher-end logic (CPUs/GPUs, DSPs, etc.) driven by ICs in the latest technology nodes in the computing, networking, mobile, and high-end consumer market segments (gaming, HD/Smart TV). However, due to additional form factor and low power demands, WLP and advanced FC substrates are also widespread in majority of smartphone functions: application processors, baseband, transceivers, filters, amplifiers, WiFi modules, drivers, codecs, power management, etc.
For more information, please visit our website: http://www.i-micronews.com/reports.html
Status of the Advanced Packaging Industry 2018 Report by Yole Developpement Yole Developpement
In the era of a slowing Moore’s Law, advanced packaging has emerged as the savior of future semiconductor development.
More information on that report at https://www.i-micronews.com/report/product/status-of-the-advanced-packaging-industry-2018.html
Fan-Out Packaging: Technologies and Market Trends 2019 report by Yole Dévelop...Yole Developpement
Samsung and PTI, with panel-level packaging, have entered the Fan-Out battlefield.
More information on that report at : https://www.i-micronews.com/report/product/fan-out-packaging-technologies-and-market-trends-2019.htm
Fibre Reinforced Plastic manufacturing methodsjeff jose
Composites manufacturing processes are complex, and involve combinations of the following physical processes:
1) Reinforcement Shaping
2) Resin Infusion
3) Composite Consolidation
Advantages and disadvantages of processing techniques
plastic composite manufacturing
Hand Lay-up
Spray up method
Filament winding
Match die molding
Pultrusion
Resin transfer molding
Reaction injection molding
Hand Lay-Up is well suited for low volume production of product.
This method can be used for both corrosion barrier and the structural portion
Fiber is chopped in a hand-held gun and fed into a spray of catalyzed resin directed at the mold. The deposited materials are left to cure under standard atmospheric conditions.
Status of Panel Level Packaging 2018 Report by Yole Developpement Yole Developpement
Panel level packaging players are ready for high volume production.
More information on that report at https://www.i-micronews.com/report/product/status-of-panel-level-packaging-2018.html
Status of Panel-Level Packaging & Manufacturing 2015 Report by Yole Developpe...Yole Developpement
Which applications will drive panel platforms?
For more than four decades, the semiconductor industry has rigorously followed Moore’s Law in scaling down CMOS technologies. However, a huge investment in new lithography solutions is required to achieve advanced nodes in a range of 20 nm. Although some packaging platforms processed on wafer, i.e. SI interposer, exhibit good performance, high cost is still the main obstacle that limits its adoption for high-volume manufacturing.
The demand for lower cost with higher performance has driven the semiconductor industry to develop innovative solutions. One new approach to reducing overall cost is to switch from wafer to a larger-size panel format. Indeed, the panel infrastructure has attracted considerable interest from the semiconductor industry and is certainly a promising market due to its cost advantages and economy of scale benefits. Panel-level manufacturing has the potential to leverage the knowledge and infrastructure of wafer-level packaging (WLP) and the PCB/Flat-Panel Display/Photovoltaic industries....
System-in-Package Technology and Market Trends 2020 report by Yole DéveloppementYole Developpement
How is System-in-Package capably meeting the stringent requirements of consumer applications?
More info here: https://www.i-micronews.com/products/system-in-package-technology-and-market-trends-2020/
Lithography technology and trends for « Semiconductor frontier » held by Aman...Yole Developpement
Lithography technology and trends for « Semiconductor frontier »
Mask aligners are the fastest lithography technology
Stepper technology provides the best resolution
Key requirements for Advanced Packaging
LED manufacturers use small diameter wafers (2”, 3”, 4” or 6”) and transition more rapidly than traditional semiconductor’s industry to larger diameters
WAFER SIZE
Wafer bow can reach up to 50μm for 2” wafers and 100μm for 4”, inducing pattern distortion.
WAFER BOW
2”
4”
6”
LED manufacturers can use different substrates, mostly sapphire or SiCwafers, which are transparent with light-diffusing features such as rough or patterned surfaces. Also, they can use metal wafers for vertical structures, so there’s large material variability.
System-in-Package Technology and Market Trends 2021 - SampleYole Developpement
Through enabling design and supply chain agility, SiP will reach $19B by 2026, with IDMs, OSATs, and foundries taking advantage of it.
More information : https://www.i-micronews.com/products/system-in-package-technology-and-market-trends-2021/
Advanced Packaging Role after Moore’s Law: Transition from Technology Node Er...Yole Developpement
The growing and diversifying system requirements have continued to drive the development of a variety of new package styles and configurations:
Small-form-factor
Lightweight technology
Low-profile technology
High-pin-count technology
High-speed technology
High Reliability
Improved thermal management
Lower cost
Fan-in WLP maintains its appeal as the package that can provide 2 unmatchable advantages:
• Reduced form factor
• Low cost
Demand is reaching available capacity
Technology innovation in fan-in WLP continues:
• Die size increases
• Bump pitch reduces
Foundry involvement is no longer a dent in fan-in WLP production
Increased activity of Chinese capital on the market
New applications are emerging while other are declining
• Disruptions also expected in the MEMS and CIS domains
• Internet of Things
Mobile sector is driving fan-in WLP production and growing
IoT is on the horizon and is expected to have a significant impact on fan-in packages and the packaging industry as a whole
3DIC and 2.5D TSV Interconnect for Advanced Packaging: 2016 Business Update -...Yole Developpement
3D TSV technology is becoming a key solution platform for heterogeneous interconnection, high end memory and performance applications.
TSVs have been adopted for MEMS, Sensors, and Memory devices. What will the next technology driver be?
Through-silicon vias (TSVs) have now become the preferred interconnect choice for high-end memory. They are also an enabling technology for heterogeneous integration of logic circuits with CMOS image sensors (CIS), MEMS, sensors, and radio frequency (RF) filters. In the near future they will also enable photonics and LED function integration. The market for 3D TSV and 2.5D interconnect is expected to reach around two million wafers in 2020, expanding at a 22% compound annual growth rate (CAGR). The growth is driven by increased adoption of 3D memory devices in high-end graphics, high-performance computing, networking and data centers, and penetration into new areas, including fingerprint and ambient light sensors, RF filters and LEDs.
CIS still commanded more than 70% % share of TSV market wafer volume in 2015, although this will decrease to around 60% by 2020. This is primarily due to the growth of the other TSV applications, led by 3D memories, RF filters and fingerprint sensors (FPS). However, hybrid stacked technology, which uses direct copper-copper bonding, not TSVs, will penetrate around 30% of CIS production by 2020. The TSV markets for RF filters and FPS are expected to reach around $1.6B and $0.5B by 2020 respectively. The report will explain the market’s dynamics and give an overview of all segments and key markets. It will also provide market data in terms of revenues, units and wafer starts for all the different segments, including market share.
Comparison of main players AP: Apple A10 with inFO vs. Qualcomm Snapdragon 820 with MCeP packaging technology vs. HiSilicon Kirin 955 & Samsung Exynos 8 with standard Package-on-Package
Five major players are sharing the smartphone application processors (AP) market. Among them, Qualcomm, Apple, Samsung and HiSilicon propose the most powerful AP. They use almost the same technology node for the die, and the innovation is now at the packaging level. During this year, we observed different technologies inside the four main smartphone flagships: classic Package-on-Package (PoP) developed by Amkor for the Kirin 955 and for the Exynos 8, Molded Core Embedded Package (MCeP) technology developed by Shinko for the Snapdragon 820 and integrated Fan-Out packaging (inFO) developed by TSMC for the A10.
Located under the DRAM chip on the main board, the AP are packaged using PoP technology. The Apple A10 can be found in the iPhone 7 series. The HiSilicon Kirin 955 can be found in the Huawei P9 and the Samsung Exynos 8 as the Qualcomm Snapdragon 820 can be found in the Samsung Galaxy S7 series depending on the world version (US and Asia for the Snapdragon and International for the Exynos).
In this report, we highlight the differences and the innovations of the packages chosen by the end-user OEMs. Whereas some AP providers like for HiSilicon or Samsung choose to consider conventional PoP with embedded land-side capacitor (LSC), others like Apple or Qualcomm use innovative technologies like Fan-Out PoP and silicon based Deep Trench LSC or embedded die packaging with advanced PCB substrate. The detailed comparison between the four players will give the pros and the cons of the packaging technologies.
This report also compares the costs of the different approaches and includes a detailed technical comparison between the packaging structure of the Qualcomm Snapdragon 820, the Samsung Exynos 8, the HiSilicon Kirin 955 and the Apple A10.
More information on: http://www.i-micronews.com/reports.html
Qualcomm QCA9500 60 GHz Chipset - reverse costing report published by System ...system_plus
Disruptive double side molded system-in-package-based chipset for millimeter-wave applications targeting consumer devices, including integrated antennae.
2018 will be a key milestone in the journey towards 5G communication. Several areas, from semiconductor to packaging, will improve their technologies to be suitable for 5G deployment. We now know that the 5G frequency will be in the millimeter wave (mmWave) range.
More information on that report at http://www.i-micronews.com/reports.html
Polymeric Materials for Advanced Packaging at the Wafer-Level 2018 Report by...Yole Developpement
Polymeric materials market revenue will double over the next five years.
More information on that report at : https://www.i-micronews.com/report/product/polymeric-materials-for-advanced-packaging-at-the-wafer-level.html
In-depth physical and cost analysis of Samsung’s ‘1y-nm’ low power DRAM.
More information: https://www.systemplus.fr/reverse-costing-reports/samsung-lpddr5-12gb-mobile-memory/
Fan-Out and Embedded Die: Technologies & Market Trends 2015 Report by Yole De...Yole Developpement
Fan-Out and Embedded Die: Two promising Wafer/Panel-Level-Packaging technologies. What are the next steps for the growth?
Fan-Out Wafer Level Packaging is already in high-volume – but it’s about to grow even more strongly
Fan-Out Wafer Level Packaging (FOWLP) started volume commercialization in 2009/2010 and started promisingly, with initial push by Intel Mobile. However, it was limited to a narrow range of applications – essentially single die packages for cell phone baseband chips – reaching its limit in 2011. In 2012 big fab-less wireless/mobile players started slowly volume production after qualifying the technology...
Advanced Substrates Overview: From IC Package to Board - 2017 Report by Yole ...Yole Developpement
How can advanced substrates and boards bridge the gap created by front-end scaling?
Advanced substrates as a key enabler of future products and markets
In an uncertain, transformative semiconductor market, advanced packaging is one of the key technologies offering stability and a long-term solution. On one hand it can adapt to product diversification, offering more functionality, system integration, and performance, as well as potentially lower manufacturing cost; and on the other hand it can adhere to future scaling requirements. Advanced substrates are the key interconnect component of advanced packaging architectures and are critical in enabling future products and markets. For this reason, Yole has established this stand-alone dedicated advanced substrate activity, focused on exploring the market and technologies of PCBs, package substrates and RDLs. This first report will serve as an overview of advanced substrate technologies, markets, and supply chain, to be supported by subsequent in-depth reports.
Today’s advanced substrates in volume are Flip Chip (FC) substrates, 2.5D/3D TSV assemblies, and thin-film RDLs (Fan-Out WLP, or “FOWLP”) below an L/S resolution of 15/15 um and with transition below L/S < 10/10 um. These advanced substrates are traditionally linked to higher-end logic (CPUs/GPUs, DSPs, etc.) driven by ICs in the latest technology nodes in the computing, networking, mobile, and high-end consumer market segments (gaming, HD/Smart TV). However, due to additional form factor and low power demands, WLP and advanced FC substrates are also widespread in majority of smartphone functions: application processors, baseband, transceivers, filters, amplifiers, WiFi modules, drivers, codecs, power management, etc.
For more information, please visit our website: http://www.i-micronews.com/reports.html
Status of the Advanced Packaging Industry 2018 Report by Yole Developpement Yole Developpement
In the era of a slowing Moore’s Law, advanced packaging has emerged as the savior of future semiconductor development.
More information on that report at https://www.i-micronews.com/report/product/status-of-the-advanced-packaging-industry-2018.html
Fan-Out Packaging: Technologies and Market Trends 2019 report by Yole Dévelop...Yole Developpement
Samsung and PTI, with panel-level packaging, have entered the Fan-Out battlefield.
More information on that report at : https://www.i-micronews.com/report/product/fan-out-packaging-technologies-and-market-trends-2019.htm
Fibre Reinforced Plastic manufacturing methodsjeff jose
Composites manufacturing processes are complex, and involve combinations of the following physical processes:
1) Reinforcement Shaping
2) Resin Infusion
3) Composite Consolidation
Advantages and disadvantages of processing techniques
plastic composite manufacturing
Hand Lay-up
Spray up method
Filament winding
Match die molding
Pultrusion
Resin transfer molding
Reaction injection molding
Hand Lay-Up is well suited for low volume production of product.
This method can be used for both corrosion barrier and the structural portion
Fiber is chopped in a hand-held gun and fed into a spray of catalyzed resin directed at the mold. The deposited materials are left to cure under standard atmospheric conditions.
Status of Panel Level Packaging 2018 Report by Yole Developpement Yole Developpement
Panel level packaging players are ready for high volume production.
More information on that report at https://www.i-micronews.com/report/product/status-of-panel-level-packaging-2018.html
Status of Panel-Level Packaging & Manufacturing 2015 Report by Yole Developpe...Yole Developpement
Which applications will drive panel platforms?
For more than four decades, the semiconductor industry has rigorously followed Moore’s Law in scaling down CMOS technologies. However, a huge investment in new lithography solutions is required to achieve advanced nodes in a range of 20 nm. Although some packaging platforms processed on wafer, i.e. SI interposer, exhibit good performance, high cost is still the main obstacle that limits its adoption for high-volume manufacturing.
The demand for lower cost with higher performance has driven the semiconductor industry to develop innovative solutions. One new approach to reducing overall cost is to switch from wafer to a larger-size panel format. Indeed, the panel infrastructure has attracted considerable interest from the semiconductor industry and is certainly a promising market due to its cost advantages and economy of scale benefits. Panel-level manufacturing has the potential to leverage the knowledge and infrastructure of wafer-level packaging (WLP) and the PCB/Flat-Panel Display/Photovoltaic industries....
System-in-Package Technology and Market Trends 2020 report by Yole DéveloppementYole Developpement
How is System-in-Package capably meeting the stringent requirements of consumer applications?
More info here: https://www.i-micronews.com/products/system-in-package-technology-and-market-trends-2020/
Lithography technology and trends for « Semiconductor frontier » held by Aman...Yole Developpement
Lithography technology and trends for « Semiconductor frontier »
Mask aligners are the fastest lithography technology
Stepper technology provides the best resolution
Key requirements for Advanced Packaging
LED manufacturers use small diameter wafers (2”, 3”, 4” or 6”) and transition more rapidly than traditional semiconductor’s industry to larger diameters
WAFER SIZE
Wafer bow can reach up to 50μm for 2” wafers and 100μm for 4”, inducing pattern distortion.
WAFER BOW
2”
4”
6”
LED manufacturers can use different substrates, mostly sapphire or SiCwafers, which are transparent with light-diffusing features such as rough or patterned surfaces. Also, they can use metal wafers for vertical structures, so there’s large material variability.
System-in-Package Technology and Market Trends 2021 - SampleYole Developpement
Through enabling design and supply chain agility, SiP will reach $19B by 2026, with IDMs, OSATs, and foundries taking advantage of it.
More information : https://www.i-micronews.com/products/system-in-package-technology-and-market-trends-2021/
Advanced Packaging Role after Moore’s Law: Transition from Technology Node Er...Yole Developpement
The growing and diversifying system requirements have continued to drive the development of a variety of new package styles and configurations:
Small-form-factor
Lightweight technology
Low-profile technology
High-pin-count technology
High-speed technology
High Reliability
Improved thermal management
Lower cost
Fan-in WLP maintains its appeal as the package that can provide 2 unmatchable advantages:
• Reduced form factor
• Low cost
Demand is reaching available capacity
Technology innovation in fan-in WLP continues:
• Die size increases
• Bump pitch reduces
Foundry involvement is no longer a dent in fan-in WLP production
Increased activity of Chinese capital on the market
New applications are emerging while other are declining
• Disruptions also expected in the MEMS and CIS domains
• Internet of Things
Mobile sector is driving fan-in WLP production and growing
IoT is on the horizon and is expected to have a significant impact on fan-in packages and the packaging industry as a whole
3DIC and 2.5D TSV Interconnect for Advanced Packaging: 2016 Business Update -...Yole Developpement
3D TSV technology is becoming a key solution platform for heterogeneous interconnection, high end memory and performance applications.
TSVs have been adopted for MEMS, Sensors, and Memory devices. What will the next technology driver be?
Through-silicon vias (TSVs) have now become the preferred interconnect choice for high-end memory. They are also an enabling technology for heterogeneous integration of logic circuits with CMOS image sensors (CIS), MEMS, sensors, and radio frequency (RF) filters. In the near future they will also enable photonics and LED function integration. The market for 3D TSV and 2.5D interconnect is expected to reach around two million wafers in 2020, expanding at a 22% compound annual growth rate (CAGR). The growth is driven by increased adoption of 3D memory devices in high-end graphics, high-performance computing, networking and data centers, and penetration into new areas, including fingerprint and ambient light sensors, RF filters and LEDs.
CIS still commanded more than 70% % share of TSV market wafer volume in 2015, although this will decrease to around 60% by 2020. This is primarily due to the growth of the other TSV applications, led by 3D memories, RF filters and fingerprint sensors (FPS). However, hybrid stacked technology, which uses direct copper-copper bonding, not TSVs, will penetrate around 30% of CIS production by 2020. The TSV markets for RF filters and FPS are expected to reach around $1.6B and $0.5B by 2020 respectively. The report will explain the market’s dynamics and give an overview of all segments and key markets. It will also provide market data in terms of revenues, units and wafer starts for all the different segments, including market share.
Comparison of main players AP: Apple A10 with inFO vs. Qualcomm Snapdragon 820 with MCeP packaging technology vs. HiSilicon Kirin 955 & Samsung Exynos 8 with standard Package-on-Package
Five major players are sharing the smartphone application processors (AP) market. Among them, Qualcomm, Apple, Samsung and HiSilicon propose the most powerful AP. They use almost the same technology node for the die, and the innovation is now at the packaging level. During this year, we observed different technologies inside the four main smartphone flagships: classic Package-on-Package (PoP) developed by Amkor for the Kirin 955 and for the Exynos 8, Molded Core Embedded Package (MCeP) technology developed by Shinko for the Snapdragon 820 and integrated Fan-Out packaging (inFO) developed by TSMC for the A10.
Located under the DRAM chip on the main board, the AP are packaged using PoP technology. The Apple A10 can be found in the iPhone 7 series. The HiSilicon Kirin 955 can be found in the Huawei P9 and the Samsung Exynos 8 as the Qualcomm Snapdragon 820 can be found in the Samsung Galaxy S7 series depending on the world version (US and Asia for the Snapdragon and International for the Exynos).
In this report, we highlight the differences and the innovations of the packages chosen by the end-user OEMs. Whereas some AP providers like for HiSilicon or Samsung choose to consider conventional PoP with embedded land-side capacitor (LSC), others like Apple or Qualcomm use innovative technologies like Fan-Out PoP and silicon based Deep Trench LSC or embedded die packaging with advanced PCB substrate. The detailed comparison between the four players will give the pros and the cons of the packaging technologies.
This report also compares the costs of the different approaches and includes a detailed technical comparison between the packaging structure of the Qualcomm Snapdragon 820, the Samsung Exynos 8, the HiSilicon Kirin 955 and the Apple A10.
More information on: http://www.i-micronews.com/reports.html
Qualcomm QCA9500 60 GHz Chipset - reverse costing report published by System ...system_plus
Disruptive double side molded system-in-package-based chipset for millimeter-wave applications targeting consumer devices, including integrated antennae.
2018 will be a key milestone in the journey towards 5G communication. Several areas, from semiconductor to packaging, will improve their technologies to be suitable for 5G deployment. We now know that the 5G frequency will be in the millimeter wave (mmWave) range.
More information on that report at http://www.i-micronews.com/reports.html
SiGe based millimeter-wave chipset commercially available for
backhaul applications with beamforming capability.
More information on that report at: http://www.systemplus.fr/reverse-costing-reports/peraso-x710-chipset-60ghz-outdoor-wireless-broadband-solution/
Advanced packaging technology in the Apple Watch Series 4’s System-in-Packagesystem_plus
Four major packaging technologies: TSMC’s info, ASE’s Double Side Molding/SESUB and SiP, Skyworks’ Double Side BGA.
More information on that report at: https://www.systemplus.fr/reverse-costing-reports/advanced-packaging-technology-in-the-apple-watch-series-4s-system-in-package/
Broadcom AFEM-8100 System-in-Package in the Apple iPhone 11 Seriessystem_plus
Cost effective third generation of mid/high band Front-End Module with advanced and innovative packaging.
Reverse Costing - Structure, process and cost report - find more here: https://www.systemplus.fr/reverse-costing-reports/broadcom-afem-8100-system-in-package-in-the-apple-iphone-11-series/
Qorvo QPF4006 39GHz GaN MMIC Front End Modulesystem_plus
The first MMIC FEM targeting 5G base stations and terminals using a 0.15µm GaN-on-SiC process.
More information on that report at: https://www.systemplus.fr/reverse-costing-reports/qorvo-qpf4006-39ghz-gan-mmic-front-end-module/
Sensirion SGP30 Gas Sensor 2018 - teardown reverse costing report published b...system_plus
The first monolithic multi-gas sensor from Sensirion, with a unique and innovative design using metal oxide technology.
More information on that report at http://www.systemplus.fr/reverse-costing-reports/sgp30-gas-sensor-from-sensirion/
Sensirion, a leading manufacturer of digital microsensors and systems, recently released a gas sensor designed for consumer and appliance applications: the SGP30 Multi-Pixel. The SGP30 gas sensor is a new kind of sensor which measures different gas types in any environment. With a DFN package volume under 5.5 mm3, this gas sensor can be embedded in a variety of low-power systems, including smartphones, tablets, and laptops.
NVIDIA’s new generation Graphics Processing Unit (GPU) with TSMC CoWoS, 40GB Samsung HBM2, 2.5D and 3D packaging.
More information: https://www.systemplus.fr/reverse-costing-reports/nvidia-a100-ampere-gpu/
GaN Systems GS61004B GaN HEMT 2018 teardown reverse costing report published ...system_plus
Discover how GaN Systems has designed its high-current, low-voltage PCB embedded GaN-on-Si transistor.
More information on that report at: http://www.systemplus.fr/reverse-costing-reports/gan-systems-gs61004b-gan-hemt/
Take a look at the fifth generation of EPC’s low voltage transistor
The low voltage GaN device market is increasingly important, and Efficient Power Conversion Corporation (EPC) is a major player in low voltage GaN-on-silicon high-electron-mobility transistor (HEMT) devices. 100V GaN HEMTs are a very new technology but they already compete with silicon transistors, especially in the field of megahertz high frequency applications.
System Plus Consulting has investigated the company’s EPC2045 device, its latest driving 100V for applications such as single-stage 48V converters, USB-C data and power connectors, LiDAR sensors, point-of-load converters and loads in open rack server architectures.
With its new transistor and GaN epitaxy design, the EPC2045 achieves a breakdown voltage of 100V for a current of 16A at 25°C, and a very low RdsOn on-resistance of 7mΩ compared to the previous generation.
The chip-scale packaging of EPC products reduces the final device cost and decreases its inductance, bringing advantages not only with respect to competitors in GaN, but also silicon.
Compared to silicon transistors, GaN process developments have significantly lowered capacitance. This translates into lower gate drive losses and lower device switching losses at higher frequencies for the same on-resistance and voltage rating.
More information on that report at http://www.i-micronews.com/reports.html
SPR21610 - Vitesco Technologies Power Module in Jaguar I-PACE Invertersystem_plus
Multiple optimized packaging innovations for this automotive power module from Vitesco Technologies.
More : https://www.systemplus.fr/reverse-costing-reports/vitesco-technologies-power-module-in-jaguar-i-pace-inverter/
Deep dive analysis of the fourth generation of mid/high band front-end module for 4G and 5G from Broadcom.
More information : https://www.systemplus.fr/reverse-costing-reports/broadcom-afem-8200-pamid-in-the-apple-iphone-12-series/
First consumer application in the Intel Core 8th Generation i7-8809G, the world’s first On-Package CPU and GPU with High Bandwidth Memory.
More information on that report at: https://www.systemplus.fr/reverse-costing-reports/intels-embedded-multi-die-interconnect-bridge-emib/
Panasonic PGA26C09DV 600V GaN HEMT teardown reverse costing report published ...Yole Developpement
Panasonic’s first 600V GaN HEMT has an innovative structure designed to integrate a normally-off transistor in a standard package, without a cascade structure
System Plus Consulting unveils Panasonic’s first GaN HEMT, assembled in a standard TO220 package. Thanks to its specific die design, the component is normally-off without using a cascade structure or special packaging.
Panasonic’s PGA26C09DV features a medium-voltage breakdown of 600V for a current of 15A (25°C), with very low RdsOn compared to its competitors. The transistor is optimized for AC-DC power supply, photovoltaic, and motor inverters.
The GaN and AlGaN layers are deposited by epitaxy on a silicon substrate. A complex buffer and template layer structure is used to reduce stress and dislocation. This is complemented by a thick superlattice structure clearly visible in the TEM analysis.
Based on a complete teardown analysis, this report also provides a production cost estimate for the epitaxy, HEMT, and package.
Moreover, this report offers a comparison with GaN Systems’ GS66504B and Transphorm’s GaN HEMT, highlighting the huge differences in design and manufacturing process and their impact on device size and production cost.
For more information visite us at: http://www.i-micronews.com/reports.html
Fingerprint Cards’ FPC1268 in the Huawei Mate 9 Pro & P10 series 2017 teardow...Yole Developpement
The world’s first capacitive fingerprint successfully integrated under glass, in collaboration with TPK
Fingerprint Cards AB (FPC), a leader in capacitive fingerprint technology, has over the last year equipped a large number of smartphones worldwide. One of its biggest clients, Huawei, traditionally integrates the latest technology in its flagship model every year. With the integration of the FPC1268 in the Huawei Mate 9 Pro and the Huawei P10 series, FPC has introduced a new kind of capacitive fingerprint integration: one that can be successfully integrated under glass. This technology, developed in collaboration with TPK, aims to be the new low-cost solution for fingerprint scanner integration.
Following the Mate 9 Pro, the Huawei P10 is the latest smartphone to feature the capacitive fingerprint completely hidden behind the cover glass. The sensor is located under the home button in the device’s front, under a unique TPK-developed glass cover that allows for new, highly attractive designs like the ultrasonic fingerprint.
Using the same process as FPC’s previous flagship product, the 1025, the integration no longer requires wire bonding but instead a specific TSV designed by an identified OSAT and based on Tessera’s WLCSP solution. While previously used for CIS integration, this is the first time it has been used for fingerprint. Along with the ASIC, the fingerprint is integrated into an LGA package which is soldered on a flex PCB and covered by TPK’s specially-designed glass.
Thanks to conductive layers, TPK’s solution allows for the precise detection and identification of the fingerprint under glass. Everything is packaged in a metal ring that forms part of the home button.
This report provides a complete analysis of chip fabrication and package processes, along with a cost estimate. Also included is a comparison with FPC’s previous capacitive fingerprint generation, the FPC1025, and Qualcomm’s new ultrasonic fingerprint, the Sense ID.
More information on that report at http://www.i-micronews.com/reports.html
Texas Instruments’ Time of Flight Image Sensor 2017 teardown reverse costing ...Yole Developpement
A look into Texas Instruments’ system-on-chip, including Sony/Softkinetic’s time-of-flight pixel technology, for industrial applications
Today, Time-of-Flight (ToF) systems are among the most innovative technologies offering imaging companies an opportunity to lead the market. Every major player wants to integrate these devices to provide functions such as 3D imaging, proximity sensing, ambient light sensing and gesture recognition.
Sony/Softkinetic has been investigating this technology deeply, providing a unique pixel technology to several image sensor manufacturers in three application areas: consumer, automotive and industrial. For industrial applications, Sony/Softkinetic has licensed its technology to Texas Instruments, which is providing ToF imagers for human detection or robot-human interaction.
The OPT8241 3D ToF imager is packaged using Chip-On-Glass (COG) technology. The device comprises a system-on-chip (SoC) and glass filter in the same component in thin, 0.7 mm-thick, packaging.
This report analyzes the complete component, from the glass near-infrared band-pass filter to the collector based on ToF pixel licenses developed by Sony/Softkinetic and adapted by Texas Instruments. The report includes a complete cost analysis and price estimation of the device based on a detailed description of the package, and the ToF imager.
It also features a complete ToF pixel technology comparison with the Infineon/pmd, STMicroelectronics and Melexis automotive ToF imagers, which are all also based on Sony/Softkinetic technology, with details on the companies’ design choices.
More information on that report at http://www.i-micronews.com/reports.html
Xaar partners with Ricoh to develop its first MEMS inkjet die with thin film PZT technology.
More information on that report at: http://www.systemplus.fr/reverse-costing-reports/xaar-1201-gs2p5-pzt-printhead/
Panasonic 600 V GaN HEMT PGA26E19BA 2017 teardown reverse costing report publ...Yole Developpement
Panasonic adopts a DFN 8x8 package for its normally-off GaN HEMT structure
System Plus Consulting unveils the first GaN HEMT from Panasonic assembled in a dual flat no-lead (DFN) 8x8 package. Panasonic decided to abandon the standard TO220 package, probably because of poor electrical performance. Thanks to its proprietary X-GaN transistor structure and new die design the company has managed to produce a very competitive normally-off component.
The new PGA26E19BA from Panasonic features a medium breakdown voltage of 600V for a current of 10A at 25°C, with very low on-resistance with respect to its competitors and the TO220 assembled component.The transistor is optimized to be used in power supplies and AC-DC, photovoltaic and motor inverters.
STMicroelectronics Proximity & Flood Illuminator in the Apple iPhone X - reve...system_plus
A unique combination of STMicroelectronics’ latest proximity sensor, based on single-photon avalanche diode (SPAD) technology and a VCSEL illuminator, all in Apple’s most advanced handset.
More information on that report at http://www.i-micronews.com/reports.html
LG Display Medianav ECU Available in the Dacia Dustersystem_plus
A competitive high resolution, high luminance and wide viewing angle automotive display.
Reverse Costing - Structure, process and cost report - find more here: https://www.systemplus.fr/reverse-costing-reports/lg-display-medianav-ecu-available-in-the-dacia-duster/
Similar to Samsung Exynos 9110 with ePLP: First Generation of Samsung’s Fan-Out Panel Level Packaging (FO-PLP) (20)
First self-made SoC for advanced driving in Tesla Driver Assist Autopilot 3.0
More : https://www.systemplus.fr/reverse-costing-reports/tesla-ubq01b0-fsd-chip/
SP20569 - IRay T3S Thermal Camera for Smartphonesystem_plus
Multiple optimized packaging innovations for this automotive power module from Vitesco Technologies.
More : https://www.systemplus.fr/reverse-costing-reports/iray-t3s-thermal-camera-for-smartphone/
Technical and cost overview of the evolution of radio frequency front-end module technologies integrated in 5G mmWave and Sub-6 GHz Phones.
More : https://www.systemplus.fr/reverse-costing-reports/rf-front-end-module-comparison-2021-vol-2-focus-on-5g-chipset/
Technical and cost overview of the evolution of the radio frequency front-end module technologies integrated in the Apple iPhone series from 2016 - 2020.
More : https://www.systemplus.fr/reverse-costing-reports/rf-front-end-module-comparison-2021-vol-1-focus-on-apple/
Apple iPhone 12 series mmWave 5G Chipset and Antennasystem_plus
A study of the complete first generation of the 5G millimeter-wave chipset for Apple’s phones including custom antenna, front-end module and antenna-on-package.
More information : https://www.systemplus.fr/reverse-costing-reports/apple-iphone-12-series-mmwave-5g-chipset-and-antenna/
Deep analysis of the 400Gb optical transceiver from a leading Chinese company.
More information: https://www.systemplus.fr/reverse-costing-reports/innolights-400g-qsfp-dd-optical-transceiver/
EPC’s 70 V ePower stage with separate and independent high and low side control inputs.
More information: https://www.systemplus.fr/reverse-costing-reports/epc2152-half-bridge-monolithic-gan-ic/
Microsoft - Holographic Lens from Hololens 2system_plus
See-through holographic display for mixed reality smartglasses.
More on : https://www.systemplus.fr/reverse-costing-reports/microsoft-holographic-lens-from-hololens-2/
Cost-effective 1 mm2 miniature camera with customizable wafer-level optics for endoscopy and novel medical imaging devices.
More information : https://www.systemplus.fr/reverse-costing-reports/ams-naneye-mini-camera/
Discover Axis’s high-end product integrating its latest ARTPEC-7 in-house system-on-chip dedicated to network video and machine learning capabilities.
More information : https://www.systemplus.fr/reverse-costing-reports/axis-p1375-e-network-camera/
Hikvision Intelligent Thermal Network Camera (DS-2TD2166-15 V1)system_plus
Dig deep into Hikvision’s AI-powered thermal network camera for security applications.
More information: https://www.systemplus.fr/reverse-costing-reports/hikvision-intelligent-thermal-network-camera-ds-2td2166-15-v1/
The first 600V system-in-package half-bridge driver from STMicroelectronics integrating two GaN-based HEMTs.
More information: https://www.systemplus.fr/reverse-costing-reports/stmicroelectronics-mastergan1-half-bridge-driver/
Physical and cost analysis of Micron’s fifth-generation low-power DRAM memory.
More information: https://www.systemplus.fr/reverse-costing-reports/micron-lpddr5-12gb-mobile-memory/
Safran Colibrys MS1010 and MEMSIC MXA2500M High-End Accelerometerssystem_plus
Detailed technology and cost analysis of the high-end single-axis and dual-axis accelerometers integrated in the STIM318 IMU.
More information: https://www.systemplus.fr/reverse-costing-reports/safran-colibrys-ms1010-and-memsic-mxa2500m-high-end-accelerometers/
Sensonor STIM318 Inertial Measurement Unit (IMU)system_plus
Newest IMU with 9-axis detection and gyro bias instability of 0.3°/h from Sensonor.
More information: https://www.systemplus.fr/reverse-costing-reports/sensonor-stim318-inertial-measurement-unit-imu/
Hamamatsu Photodiode and Laser in Livox’s Horizon LiDARsystem_plus
Analysis of the six channels and 905nm pulsed laser and photodiode from Hamamatsu, in Livox’s LiDAR for automotive ADAS.
More information: https://www.systemplus.fr/reverse-costing-reports/hamamatsu-photodiode-and-laser-in-livox-horizon-lidar/
Everspin’s Spin Transfer Torque MRAM with perpendicular magnetic tunnel junction.
More information: https://www.systemplus.fr/reverse-costing-reports/everspin-emd3d256m-sttmram-memory/
MEMS Fabry-Perot interferometer in a very tiny NIR spectrometer.
More information: https://www.systemplus.fr/reverse-costing-reports/spectral-engines-nirone-sensor-x/
World’s first 76-81 GHz automotive single-chip radar in a System-on-Chip device with integrated Antenna-in-Package using Fan-Out packaging technology.
Reverse Costing - Structure, process and cost report by System Plus Consulting - find more here: https://www.systemplus.fr/reverse-costing-reports/mediatek-autus-r10-mt2706-77-79-ghz-ewlbaip-radar-chipset/
Deep analysis of the latest generation of under-display optical fingerprint sensors using micro-optics.
Reverse Costing - Structure, process and cost report by System Plus Consulting - find more here: https://www.systemplus.fr/reverse-costing-reports/goodixs-ultra-thin-optical-in-display-fingerprint/
Elevating Tactical DDD Patterns Through Object CalisthenicsDorra BARTAGUIZ
After immersing yourself in the blue book and its red counterpart, attending DDD-focused conferences, and applying tactical patterns, you're left with a crucial question: How do I ensure my design is effective? Tactical patterns within Domain-Driven Design (DDD) serve as guiding principles for creating clear and manageable domain models. However, achieving success with these patterns requires additional guidance. Interestingly, we've observed that a set of constraints initially designed for training purposes remarkably aligns with effective pattern implementation, offering a more ‘mechanical’ approach. Let's explore together how Object Calisthenics can elevate the design of your tactical DDD patterns, offering concrete help for those venturing into DDD for the first time!
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...UiPathCommunity
💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
Speakers:
👨🏫 Andras Palfi, Senior Product Manager, UiPath
👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
DevOps and Testing slides at DASA ConnectKari Kakkonen
My and Rik Marselis slides at 30.5.2024 DASA Connect conference. We discuss about what is testing, then what is agile testing and finally what is Testing in DevOps. Finally we had lovely workshop with the participants trying to find out different ways to think about quality and testing in different parts of the DevOps infinity loop.
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
Generating a custom Ruby SDK for your web service or Rails API using Smithyg2nightmarescribd
Have you ever wanted a Ruby client API to communicate with your web service? Smithy is a protocol-agnostic language for defining services and SDKs. Smithy Ruby is an implementation of Smithy that generates a Ruby SDK using a Smithy model. In this talk, we will explore Smithy and Smithy Ruby to learn how to generate custom feature-rich SDKs that can communicate with any web service, such as a Rails JSON API.
JMeter webinar - integration with InfluxDB and GrafanaRTTS
Watch this recorded webinar about real-time monitoring of application performance. See how to integrate Apache JMeter, the open-source leader in performance testing, with InfluxDB, the open-source time-series database, and Grafana, the open-source analytics and visualization application.
In this webinar, we will review the benefits of leveraging InfluxDB and Grafana when executing load tests and demonstrate how these tools are used to visualize performance metrics.
Length: 30 minutes
Session Overview
-------------------------------------------
During this webinar, we will cover the following topics while demonstrating the integrations of JMeter, InfluxDB and Grafana:
- What out-of-the-box solutions are available for real-time monitoring JMeter tests?
- What are the benefits of integrating InfluxDB and Grafana into the load testing stack?
- Which features are provided by Grafana?
- Demonstration of InfluxDB and Grafana using a practice web application
To view the webinar recording, go to:
https://www.rttsweb.com/jmeter-integration-webinar
Key Trends Shaping the Future of Infrastructure.pdfCheryl Hung
Keynote at DIGIT West Expo, Glasgow on 29 May 2024.
Cheryl Hung, ochery.com
Sr Director, Infrastructure Ecosystem, Arm.
The key trends across hardware, cloud and open-source; exploring how these areas are likely to mature and develop over the short and long-term, and then considering how organisations can position themselves to adapt and thrive.
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
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