System-in-Package Technology and Market Trends 2020 report by Yole Développement

From Technologies to Markets
© 2020
From Technologies to Markets
System-in-Package
Technology
and Market
Trends 2020
SAMPLE

222
 Glossary 2
 Table of contents 3
 Report scope and objectives 5
 Report methodology 7
 About the authors 8
 Companies cited in this report 9
 Who should be interested in this report 10
 Yole Group’s related reports 11
 Three-page summary 12
 Executive summary 16
 Introduction 66
o SiP definitions, historical perspectives, drivers 67
o Report focus 79
 Combined market forecasts: system-in-ackage 82
o Market and forecasts (units, revenue) 83
o Market trends: explanation of SiP growth 87
 Combined market share and supply chain: system-in-package 89
o Combined market share (2018 and 2019) 91
o Supply chain analysis 95
o SiP manufacturers and key customers
o SiP business model evolution
o SiP business model is key to SiP success
o Chapter conclusion
System-in-Package Technology and Market Trends 2020 | Sample | www.yole.fr | ©2020
TABLE OF CONTENTS
(1/2)
 Combined roadmaps: system-in-package 108
o SiP roadmaps, by application 109
o SiP roadmaps, by players 116
 Flip-chip and wire-bond: system-in-package 124
o Definition and process flow 125
o Market forecasts (units, revenue) 133
o Mobile and consumer market
o Telecom and infrastructure market
o Automotive and transportation market
o Medical, industrial, defense and aerospace markets
o Market trends 147
o What drives FC and WB SiP in the mobile and consumer market?
o What drives FC and WB SiP in telecom and infrastructure market?
o Key drivers for FC and WB SiP
o Supply chain 151
o Geographical mapping
o Supply chain analysis
o New business-model evolution
o Technology trends 157
o By application: mobile and consumer
o By application: telecom and infrastructure
o By application: automotive and transportation
o Chapter conclusion 221
Combined: a combination of flip-chip, wire-bond, fan-out, and embedded die technologies are covered in this report.

333
 Fan-Out packaging: system-in-package 224
o Definition and focus 225
o Market forecasts 230
o Package units (Mu)
o Wafer volume (kwspy)
o Revenue ($M)
o Market trends 238
o FO SiP drivers
o Integration capabilities
o Supply chain 243
o Fan-out packaging - timeline and evolution
o Global map of fan-out system-in-package players
o Key players that commercialized FO SiP
o FO SiP supply chain analysis
o Market share 254
o 2019 FO SiP market share
o Fo SiP market - player analysis
o FO SiP wafer-volume production - roadmap
o Fan-out technology space
o Commercialized fan-out SiP products
o Adoption challenge 271
TABLE OF CONTENTS
(2/2)
 Embedded die: system-in-package 277
o Definition and focus 278
o Introduction 284
o Market forecasts 288
o Revenue (value)
o Package (units)
o Market trends 292
o Roadmaps, market drivers, and technical requirements
o Supply chain 299
o Players involved in an embedded die activity
o Supply chain analysis - business model
o Segmentation (technology features and players’ activities)
o Adoption rationale
o Available commercial products, and future product launches
 Conclusion 330
 Yole Développement presentation 332

444
Favier SHOO
Favier Shoo is a Technology and Market Analyst in the Semiconductor and Software division at Yole Développement (Yole), part of Yole Group of Companies.
Based in Singapore, he is engaged in the development of reports as well as the production of custom consulting projects. With prior experience at Applied
Materials and REC Solar, Favier has developed a deep understanding of the supply chain and core business values. Being knowledgeable in this field, Favier has
conducted professional training for industry players and obtained two patents. He also co-founded a startup company. Favier holds a bachelor’s in Materials
Engineering (Hons) and a minor in Entrepreneurship from Nanyang Technological University (NTU) (Singapore).
Contact: favier.shoo@yole.fr
Santosh KUMAR
Santosh Kumar currently works as Principal Analyst and Director of Packaging, Assembly and Substrates for Yole Korea. Based in Seoul, Santosh is involved in the
market, technology, and strategic analysis of microelectronic assembly and packaging technologies. His main area of interest is advanced IC packaging technology,
including equipment and materials. He has authored several reports on fan-out / fan-in WLP, flip chip, and 3D/2.5D packaging.
Santosh received a bachelor’s and master’s degree in Engineering from the Indian Institute of Technology (IIT), Roorkee and the University of Seoul, respectively.
He has published more than 40 papers in peer-reviewed journals and has obtained two patents. Moreover, Santosh has presented and given talks at numerous
conferences and technical symposiums related to advanced microelectronics packaging.
Contact: santosh.kumar@yole.fr
ABOUT THE AUTHORS
Biographies and contacts

555
Access,Amkor,Analog Devices,Apple,ARM,ASE,Avago,ATandS, Bosch, Broadcom,
Carsem, ChinaWLCSP, Chipbond, ChipMOS, Cisco, Continental, Cyntec, Cypress
Semiconductor, DecaTechnologies, Dyconex, Facebook, Fitbit, Flexceed, Flip Chip
International, Formosa, Fraunhofer IZM, Freescale, Fujikura, Fujitsu, GaN Systems,
General Electric, GlobalFoundries, Google, Hana Micron, Hella, Huawei, IMEC, Inari
Berhad, Infineon, Intel, J-Devices, JCET, KingYuan, Lenovo, LinearTechnology, LB
Semicon, MediaTek, Medtronic, Meiko, Microchip, Microsemi, Nanium, Nepes, Nvidia,
NXP, Nokia, ON Semiconductor, Orient Semiconductor, Powertech Technology Inc,
Renesas, QDOS, Qorvo, Qualcomm, Rohm, Sarda Technologies, Samsung Electronics,
SCC, Schweizer, SEMCO, SIMMTECH, SK Hynix, Shinko, ShunSin, SiPlus, Softbank,
SONY, SPIL, Spreadtrum, STMicroelectronics, STATS ChipPAC, STS Semiconductor,
TaiyoYuden,TDK,Teraprobe,Texas Instruments, Tianshui Huatian,Tongfu
Microelectronics,Tong Hsing,Toshiba,TSMC, Unimicron, Unisem, USI, UTAC,Wurth
Electronics, and many more..
COMPANIES CITED IN THIS REPORT
Non-exhaustive list

666
This report’s main objectives are to:
• Describe technologies that can be classified as “system-in-package”
• Identify and detail the system-in-package platform’s key process steps
• Analyze the supply chain for system-in-package technologies
• For these steps, provide a market forecast for the coming years and a prediction of future trends
System-in-package is studied from the following perspectives:
• Available technologies and their inherent challenges
• Market size
• Revenue and market valuation
• Market share of players involved
• Supply chain analysis
REPORT SCOPE
Are your needs
beyond this
report’s scope?
Contact us for a custom
analysis:

777
Advanced System-in-Package (SiP) 2020 is a new report that explores in detail the hottest trends in
advanced semiconductor packaging.The report’s objectives are as follows:
• A three-page summary providing an overview of this report’s main points
• Provide a market forecast for system-in-package revenue (2018 - 2025)
• Focus on flip-chip, wire-bond, fan-out, and embedded die
• Explanation of growth for end-markets and end-devices
• Market trends
• Key drivers, by technology
• Drivers, by end-market
• Market share
• Breakdown, by manufacturer
• Furnish a full supply-chain analysis of SiP players
• SiP manufacturers and key customers
• SiP business models - full analysis
• Technology trends for SiP technologies
• By end-market
• Technical roadmaps
REPORT OBJECTIVES

888System-in-Package Technology and Market Trends 2020 | Sample | www.yole.fr | ©2020
REPORT METHODOLOGIES
Market
Volume (in Munits)
ASP (in $)
Revenue (in $M)
Yole’s market forecast model is based on the matching of several sources:
Information
Aggregation
Preexisting
information

WHO SHOULD BE INTERESTED IN THIS REPORT?
• Equipment and materials suppliers:
• Understand the overall SiP business and
technology trends
• Identify SiP’s high-growth areas
• Spot business opportunities and prospects
• See the positioning and market share of various
tool suppliers
• Monitor and benchmark potential competitors
• OSATs, IDMs, foundries:
• Grasp technology trends related to SiP
• Find new opportunities and define
diversification strategies
• Comprehend the overall SiP market
• Discern the supply chains involved in SiP
• RandD players:
• Obtain insight into the latest developments in SiP
technologies
• Grasp the market potential of different emerging
technologies
• Financial and strategic investors:
• Distinguish the key players involved in SiP business
• See which markets have the highest growth
potential, and how the SiP supply chain involved in
these segments will benefit
• Explore MandA opportunities
• OEMs and integrators:
• Highlight technology trends in SiP
• Confirm new opportunities and define
diversification strategies
• Realize the overall SiP market

101010
It is a fact that there is confusion in the market regarding how to define System-in-Package (SiP). However, this is understandable because companies with different business models
(OSAT, Foundry, IDM, and substrate manufacturers) define SiP based on their technology and business context. In fact, there actually is industry agreement on the definition of SiP.
Yole’s definition is stated clearly in the next slide. A list of SiP’s definition according to different players is shown below.
ASE: OSAT
System-in-Package (SiP) meets growing demands for semiconductor miniaturization and multiple functions. SiP performs full functional system or sub-system functions at the package level.
SiP has evolved into 2D and 3D integrated modules of several chip packages lined up side by side or stacked, or adding passives or other required components into the package to build a
full sub-system function.
Amkor: OSAT
Amkor Technology defines advanced SiPs as multi-component, multifunction products in an IC package. They require high-precision assembly technologies, which leverage Amkor’s
strengths.
JCET Group: OSAT
System-in-Package (SiP) is a functional electronic system or sub-system that includes two or more heterogeneous semiconductor die (often from different technology nodes optimized for
their individual functionalities), usually with passive components. The physical form of SiP is a module, and depending on the end-application, the module could include a logic chip,
memory, integrated passive devices (IPD), RF filters, sensors, heat sinks, antennas, connectors, and/or power chip in packaged or bare die form.
TSMC: Foundry
TSMC's innovative CoWoS® advanced packaging technology integrates logic computing and memory chips in a 3-D way for advanced products targeting artificial intelligence, cloud
computing, data center, and supercomputer applications.
SEMCO: IDM
This product is developed by realizing complex functions into one system, by mounting multiple ICs and passive components in a package.
Intel: IDM
Heterogeneous system-in-package (SiP) products are highly integrated semiconductors that combine FPGAs with various advanced components, all within a single package.
Shinko: Substrate manufacturer
The SiP integrates multiple chips in one package and allows the product to function as a whole system. This helps in the miniaturization and sophistication of such devices. It is also
possible to integrate semiconductors with different processes in the same package
SYSTEM-IN-PACKAGE DEFINITION - ALL THE DIFFERENTVERSIONS

11
YOLE DEVELOPPEMENT’S SYSTEM-IN-PACKAGE DEFINITION
A System-in-Package (SiP) is characterized by any combination of one or more integrated circuit(s) of different functionality, which may include
passive components and/or MEMS, assembled into a single package that performs as a system or sub-system. SiPs can utilize a combination of
advanced packaging technologies including flip-chip, wire-bonding,fan-out, or embedded die in 2D, 2.5D, 3D, or any combination of these
configurations.
A SiP may contain one or more IC chips plus other components with different technologies that are traditionally found on the system mother board,
such as:
The SiP’s essential value is the ability to bring together many IC, package assembly, and test technologies to create highly integrated products with
optimized cost, size, and performance.
System-in-package technology allows multiple advanced packaging technologies to be combined to create solutions customized to each end-
application. Laminate-based SiP technology is the front-runner solution and the most popular SiP choice for cellular, IoT, power, automotive,
networking, and computing system integrations. By this definition, multichip packages (MCP) and multichip modules (MCM) aren’t considered a SiP.
Silicon Bridge
GPUDRAM (HBM Stack)
Embedded die in computing: Intel’s EMIB
Fan-out in smartphone:TSMC’s inFO-PoP (FOWLP)
Flip-chip and wire-bond SiP in IoT: packaged by Intel
Flip-chip SiP: SPIL and UMC

12
ADVANCED PACKAGING PLATFORMS - SiP INTEGRATION ENABLER
Wafer level Substrate/Strip level (Panel-based) Panel level
Level 1 - Die
Interconnection
Substrate/
leadframe
Level 2 -
Packaging
Module
Level 3 -
No SMT needed
SiP/PoP, etc. ED in PCB/Flex
ED in
laminate
Organic/
glass
substrate
etc.
Standard organic substrate
Flip Chip Wire-bond RDL
FOWLP 3D
FOPLP
Silicon/
glass
bridge
Bump/
pillar
TSV/
TGV
Ceramic/
leadframe
and others
Advanced
organic
substrate
Mold
embedding
Organic Interposer
FC
WB
CSP
BGA Standard
BGA Advanced
LGA
BGA
LGA
CSP
Organic substrate Ceramic/
leadframe
and others
FC WB
Conventional wire-bond-based SiP
is not covered in this reportFIWLP
Focus of this report System-in-Package Technology and Market Trends 2020 | Sample | www.yole.fr | ©2020

SIP - HISTORICAL EVOLUTION
1980s
Multi-chip modules
(MCMs)
Volume/adoption
SiP
2000s 2010s
•MCMs were first developed by IBM to
package processors for data centers and
enterprise applications
•Expensive, low volume, low yield
•Customized supply chain
Mobile eraPC era
Big data / AI / IoT era
•SiP as we know it today emerged during the
2000s, driven by mobile’s functionality and
miniaturization requirements
•Cost, form-factor, performance
•Volume exploded due to various SiPs (but mainly
RF) adoption in mobile
•OSATs emerged as key assemblers
•SiP business migrated from IDMs to OSATs
•Supply chain matured
High-end SiP
Low-end SiP
• Mobile, IoT, connectivity
• FC substrate-based
• LD-FO
• OSATs, substrate suppliers, EMS
• Infrastructure, networking, HPC, telecom, ADAS
• Logic +memory (HBM) integration
• Logic+ XCVRs
• Si interposer, HD-FO, hybrid bonding
• Foundries, IDMs
Interconnect: flip-chip
Ceramic substrate
Interconnect: flip-chip/wire-bond
Laminate substrate
Interconnect: flip-chip, TSV, Cu pillar, RDL
Substrate: laminate, RDL, Si interposer
Chiplets
2D 3D

14
WHY SIP?
SiP supports the
semiconductor
industry’s “MtM”
heterogeneous
integration
roadmap.
More flexibility for system designersTo mix and match IC technologies, optimize
performance of each functional block, and reduce cost. Fully integrated SiP solutions enable
designers to implement additional functionalities like Bluetooth or camera modules into a
system, with minimal design effort.
More flexibility for
system designers
Compared with SoC, different RF components are fabricated at different nodes in various fabs.
Time to market reduced.
Faster time to
market
By migrating signal-routing complexity to the package substrate => Reduced layer count in
motherboard, simplifies product design.
Reduce motherboard
complexity
Various ICs and passives placed close together => shorter line length =>lower R,L,C losses =>
Higher signal integrity and reduced power consumption.
Better performance
Compared to discrete packages, optimized SiP solutions result in overall system cost reduction.
Lower system cost
Sub-system size reduced by integrating multiple dies and passives in single SiP.
Small form-factor
Better solder joint compared to the discrete components assembled on board/PCB because the
SiPs are molded, which alleviates stress in the joints.
Reliability

KEY DRIVERS OF SIPVS STANDLONE PACKAGES
59.94 mm294.6 mm2
Apple Watch S4
Non-Cellular (Standalone)
PMIC & Passives
• Thinner / smaller form factor than individually packaged components
• Reduced system board space as compared to standalone packages
• Improved power management and more room for battery
• Increased performance and functional integration at a lower real estate
• Design flexibilities as compared to standalone packages
• Simpler cost effective SMT assembly process with fewer pass
• Cost effective “plug-and-play” solutions
• Faster time-to-market (TTM)
• Allow better electromagnetic interference (EMI) isolation
SiP Drivers
37% Package Area Reduction Apple Watch S4
Cellular (SiP)
PMIC & Passives

COMBINED SIP MARKET FORECAST

SIP - 2018 MARKET SHARE
2018 Total SiP Market Share: $12.5B
Packaging revenue, split by SiP manufacturer* [%]
Intel
Powertech Technology Inc.
Tongfu Microelectronics
Tianshui Huatian Microelectronics
UTAC
Shinko
Unisem
ChipbondChipMosTDKOthers: Inari, ShunSin, Nepes, SK
Hynix
*Speculated breakdown, not final
*Data is generated by secondary research and revised through interviews

SIP - 2019 MARKET SHARE
2019 Total SiP Market Share: $13.4B
Packaging revenue, split by SiP manufacturer* [%]
ASE w/o SPIL & USI
SONY
Amkor
JCET Group
TSMC
*Speculated breakdown, not final
*Projections are assumed, because full 2019 annual reports are not available yet

SUPPLY CHAIN - SIP MANUFACTURERS AND KEY CUSTOMERS

SUPPLY CHAIN - SIP MANUFACTURERS AND KEY DEVICES

SUPPLY CHAIN ANALYSIS
SiP business model evolution
Potential SiP business model

SUPPLY CHAIN ANALYSIS – DIFFERENT EVOLUTIONS

SUPPLY CHAIN ANALYSIS
Analyst’s point of view - adoption potential of each business model

SIP TECHNOLOGY ROADMAP
2019 - 2030: New capabilities needed for multi-die solution< 2019: Packaging technologies
Only mainstream technologies/markets are considered
COMPUTING
MOBILES
WIRELESS
COMPUTING
MOBILES
WIRELESS
GPU, CPU
CPU +
Memories
Codec
WiFi
MEMS
CIS
Display
Drivers
BB
PMIC
RF
APE
FPGA
Large Processors
Memories
GPU, CPU
CPU +
Memories
Codec
WiFi
MEMS
CIS
Display
Drivers
BB
PMIC
RF
APE
FPGA
Large Processors
Memories
IO counts
10000
100
1000
2x2 10x10 20x20 50x50 >>50x50
Package size (mm)
IO counts
10000
100
1000
2x2 10x10 20x20 50x50 >>50x50
Package size (mm)
FO
FC CSP
WB
FI CSP
FC BGA
FC BGA
2.5D/3D FC
HD FO PoP EB BGA PoP
WB SiP (Stacked Die)
FC SiP (Double Side)
FC BGA SiP
Embedded Die (AiP)
PoP and 2.5D SiP
HD FO SiP PoP
FO on Substrate 3D
FC/SMT SiP
FC SiP (EMI Shielding)
Emergence of new SiP-
like packaging
technologies will be
needed to address the
need for heterogeneous
integration for functional
performance and faster
time-to-market.
PoP PiP
FO SiP
FO on Substrate
Potential SiP technologies
covering a wide range of
I/Os and package sizes in
different end-market
applications - from low-end
to high-end.

SIP TECHNOLOGY ROADMAPS - KEY PARAMETERS

SIP TECHNOLOGY ROADMAPS - WHAT ARE THE MAJOR CHALLENGES?

27
FC/WB SIP FORECAST
Total FC/WB SiP packaging revenue, by market ($M)

28
FC/WB SIP FORECAST - MOBILE AND CONSUMER MARKET
FC/WB SiP packaging revenue, by application ($M)

29
FC/WB SIP FORECAST -TELECOM AND INFRASTRUCTURE MARKET
FC/WB SiP packaging revenue, by application ($M)

FC AND WB SIP SUPPLY CHAIN - GEOGRAPHICAL MAPPING
Non-Exhaustive list of players. Only the location of the company’s headquarters is considered.
Chart is based on company counts.
Fabless players are mainstream in North America.
NORTH AMERICA
Design house with Packaging is the
biggest business model in Europe.
EUROPE
IC Substrate Manufacturers are firmly
established in Asia.
ASIA
IC Substrate
Manufacturers
Packaging Manufacturers
Fabless or Design House
IC Substrate
Manufacturers with
Packaging Capabilities
IDM

FAN-OUT SYSTEM-IN-PACKAGE - DRIVERS
What drives FO SiP when the majority of SiP is realized using IC substrate-based packages?
Market demands: internet of things (IoT) / wearable devices in consumer / connectivity in mobile and networking / servers/datacenter in telecom and infrastructure
MINIATURIZATION PERFORMANCE TIMETO MARKET
Fan-Out System-in-Package
Market Drivers
• Interconnected within a shorter path
• Higher routing level with more I/O
density
• Die-to-die distance reduction
• Reduced or finer L/S
• High-power dissipation solution (closer
to solder balls)
• Reduce antenna signal-loss with molding
instead of metal
• Lower power consumption
• An alternative to SoC
• Ability to test and introduce new
dielectric materials
• Less reliance on substrate manufacturers
• Easier implementation of active/passive
device from supply chain point of view
• Smaller form factor with a lower profile,
substrate-less (smaller area, slimmer
thickness without IC substrate)
• Through-package via or double-side
integration
• System and discrete passive integration
• More dies put together into a package
• Increased functionality in less space
• Capable of 3D stacking
Die 1 Die 2
MINIATURIZATION PERFORMANCE TIMETO MARKET

32
FAN-OUT SIP - MARKET FORECASTS
WAFER volume (kwspy) - 300mm wafer equivalent, by end-market
System-in-Package Technology and Market Trends 2020 | Sample | www.yole.fr | ©2020*kwspy = kilo wafer start per year

33
Revenue ($M), by end-market

34
Carrier penetration rate - FOWLP vs. FOPLP
CAGR
2019 to 2025

FAN-OUT ACTIVITIES - GLOBAL MAP OF FO SIP PLAYERS*
Uncategorized players are either not involved in FO SiP, or not known to be actively developing it.

FAN-OUT SIP - SUPPLY CHAIN STATUS

FAN-OUT SIP - 2019 MARKET SHARE
Analyst’s point of view - market share analysis

38
EMBEDDED DIE SIP - MARKET FORECASTS
UNITS (Mu) and revenue ($M)
Nascent
technology
expected to have
higher impact on
the market
starting in 2021,
when more
production plants
will be up and
ready to answer
the demand with
better quality/cost
factor.
$315M market
potential in 2025.
2018 2019 2020 2021 2022 2023 2024 2025 CAGR
TOTAL 113 199 253 378 521 692 806 848 27%
0
100
200
300
400
500
600
700
800
900
Units(Mu)
ED SiP units (Mu)
CAGR
2019 to 2025
CAGR
2019 to 2025

39
UNITS (Mu), by end-market
•The mobile market will still have the major part of ED SiP unit production (around 63%). The usage of such technology by
Qualcomm for Motorola's and Samsung’s smartphones confirms continued interest.
•Nevertheless, the entry of ED SiP in automotive is expected to be powerful for applications like power devices, and thus its
growth is the highest (79% CAGR2019-2025).
•The need for more efficient, better-performing hardware in telecom and infrastructure will increasingly appeal to ED
technology over the next five years.

40
Revenue ($M), by end-market
•Despite higher volumes for mobile/telecom and infrastructure, the automotive ED SiP market will be equivalent to the
other two. This is due to an expected high ASP for ED SiP in automotive applications because of a bigger substrate
containing a higher number of embedded dies.Thus a more complex SiP to answer automotive qualifications.
•Other markets like medical, industrial, and defense will also start using ED SiP, but these markets will still be relatively small
vs. the three main ED SiP markets.

41
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SalesTeam
for more
information
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SalesTeam
for more
information
41
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for more
information
Status of the Advanced
Packaging Industry 2019
Fan-Out Packaging:
Technologies and Market
Trends 2019
Advanced RF System-in-
Package for Cellphones 2019
Advanced Packaging
Quarterly Market Monitor
YOLE GROUP OF COMPANIES RELATED REPORTS
Yole Développement

42
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SalesTeam
for more
information
42
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SalesTeam
for more
information
42
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SalesTeam
for more
information
Fan-Out Packaging Processes
Comparison 2020
YOLE GROUP OF COMPANIES RELATED REPORTS
System Plus Consulting

43
CONTACT INFORMATION
o CONSULTING AND SPECIFICANALYSIS, REPORT BUSINESS
• North America:
• Steve LaFerriere, Senior Sales Director forWestern US & Canada
Email: laferriere@yole.fr – + 1 310 600-8267
• ChrisYouman, Senior Sales Director for Eastern US & Canada
Email: chris.youman@yole.fr – +1 919 607 9839
• Japan & Rest of Asia:
• Takashi Onozawa, General Manager,Asia Business Development
(India & ROA)
Email: onozawa@yole.fr - +81 34405-9204
• Miho Ohtake, Account Manager (Japan)
Email: ohtake@yole.fr - +81 3 4405 9204
• Itsuyo Oshiba, Account Manager (Japan & Singapore)
Email: oshiba@yole.fr - +81-80-3577-3042
• Toru Hosaka, Business Development Manager (Japan)
Email: toru.hosaka@yole.fr - +81 90 1775 3866
• Korea: Peter Ok, Business Development Director
Email: peter.ok@yole.fr - +82 10 4089 0233
• Greater China: Mavis Wang, Director of Greater China Business
Development
Email: wang@yole.fr - +886 979 336 809 / +86 136 61566824
• Europe & RoW: Lizzie Levenez, EMEA Business Development Manager
Email: levenez@yole.fr - +49 15 123 544 182
o FINANCIAL SERVICES (in partnership withWoodside Capital
Partners)
• Jean-Christophe Eloy, CEO & President
Email: eloy@yole.fr - +33 4 72 83 01 80
• Ivan Donaldson,VP of Financial Market Development
Email: ivan.donaldson@yole.fr - +1 208 850 3914
o CUSTOM PROJECT SERVICES
• Jérome Azémar,Technical Project Development Director
Email: azemar@yole.fr - +33 6 27 68 69 33
o GENERAL
• CamilleVeyrier, Director, Marketing & Communication
Email: veyrier@yole.fr - +33 472 83 01 01
• Sandrine Leroy, Director, Public Relations
Email: leroy@yole.fr - +33 4 72 83 01 89
• Email: info@yole.fr - +33 4 72 83 01 80
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