1. The document describes research into resistive random access memory (RRAM) using various metal oxide materials for the cell isolation layer, including NiO, Ni90Fe10O, and Ni80Fe20O. 2. RRAM cells were fabricated with different isolation layer materials and cell sizes. I-V curves showed the cells had bi-stable resistivity that depended on voltage sweep direction, demonstrating memory capabilities. 3. Analysis of the I-V curves and measurements of unit area capacitance and current found that Ni80Fe20O had the highest resistivity and could provide more power-efficient memory operation than the other materials tested.

1. The department of Physics, Texas State University
Gregory McClendon, Yubo Cui, Xi Tang, Abdul Talukder
Resistive Random Access Memory
Measurements and resultsBackground
 Current commercially available FLASH memory is based on a floating gate CMOS design, known as NAND FLASH,
as shown in Figure 1. The limitation of this device is the density of the memory cells has become limited by
capacitive coupling between neighboring cells. [1]
 RRAM devices have the advantage of having only 2 terminals as opposed to 3 for NAND, and a much more
simple geometry allowing for greater density. The geometry is showed in Figure 2. Oxide materials such as HfO
and NiO have been used in working RRAM devices as the middle layer, which is called cell isolation, although the
physical mechanism behind the resistive state changes is not well understood [1].
 The top electrode material for oxide based RRAMs have been shown to greatly affect the switching voltages of
the material [2]. Voltage potentials that change the material to and from low to high resistive states are known
as the SET and RESET potentials (Figure 3).
 To increase the material resistivity, it is proposed that FexNi1-xO oxides be explored as an alternative material
to NiO.
Methodology
Conclusion
References
Acknowledgments
This work was supported by the Physics Department and the Materials Research Science and Engineering Center
at Texas State University in the frame of the class: PHYS5324: Thin Films Laboratory/MSEC7310: Nanoscale systems
and devices, Spring 2015 (Instructor Dr. Alex Zakhidov). The experiments were performed in part at the
Nanofabrication Research Shared Space and the Analysis Research Service Center at Texas State University. We
thank Dr. Casey Smith and Dr. Eric Schires for provided trainings and useful discussions.
Figure 1. NAND FLASH Cell (Adopted from ref. [7]) Figure 2. RRAM FLASH Cell (Adopted from ref. [7])
 Research design: the geometry of our memory cell falls into 3 parts: bottom
electrode, cell isolation, and top electrode. Figure 4 shows a depiction of the
memory cell. The active cell area is formed by the intersection between the lines
running from the top and bottom electrode layers. The width of the electrode
ends, labeled, tc defines the active area, which equals tc
2 .
Figure 4. RRAM mask Layers
We want to study the resistivity of memory cell with the following difference:
• FexNi1-xO, different ratio of Fe and Ni.
• tc
2, different active cell area.
RRAM cells are to be fabricated with FexNi1-xO of various Fe/Ni ratios. NiO will also
be used as a reference to determine the effect of adding iron to the oxide. The
adopted Fe/Ni ratios are based upon in-stock sputtering targets for deposition.
Table 1 shows the materials we use for the cell isolation layer.
Photo masks have been identified for the purpose of creating the memory cells.
This width, tc widths run from 1u to 20u, leading to various active cell area.
Material Comments
NiO Reference
Material
Fe0.1Ni0.9O
Fe0.2Ni0.8O Deposited in
2014.
Table 1: Oxide Films
 Procedure
• Manufacture overview
Four inch diameter silicon wafers are to be the substrate upon which the material is deposited.
Titanium Nitride, TiN, is to be used as a bottom electrode material. NiO RRAMs have been
fabricated with platinum as a bottom electrode, due to its low oxygen affinity. TiN is to be used
due to costs and its low affinity for oxygen. Cobalt, as a top electrode material, has been shown
to be a suitable material for NiO RRAMs, with set and reset cycles stabilizing after 5 sequences
[2]. SiO is to be used as an insulating material. A final top layer of cobalt is to be used as the
electrode probe pad material.
Figure 5 illustrates the layer stack. Figure 5. Device stack model
We manufacture the memory cell in following order:
Figure 6. Order of device stack
1. Spin:
Photoresist: AZ 5214E
Step Duration RPM Accel
1 10 1000 500
2 10 2000 1000
3 30 6000 3000
2. Soft bake:
Temperature: 100C
Duration: 1 min
3. Lithography:
Power: 30w
Exposure time: 1.6s
4. Develop
Developer: AZ 300 MIF
Step Duration RPM Accel
1 10 100 100
2 40 0 100
3 30 4000 4000
Parameters
5. O2 plasma etcher: 30w for I min 30 sec
6. Sputtering:
Material NiO/PyO Ti TiN Co bottom electrode Co top electrode
Ar flow rate (sccm) 8 50 70 50 70
O2 flow rate (sccm) 2
RF-Power (Watt) 240 250 250 250 350
Background pressure (Torr) 10-7 10-7 10-7 10-7 10-7
Pressure during deposition (Torr) 10-3 10-2 10-2 10-2 10-2
Rotation of substrate (rpm) 24 24 24 24 24
Deposition time (sec) 450 20 1200 1200 1200
 Measurement
• Thickness
From sputtering rate, we are able to calculate the thickness of Ti, TiN, Co bottom electrode and Co top
electrode. By using filmetrics, we got the thickness of SiO. By using profilometer, we got the thickness of the
isolation layer.
NiO Fe0.1Ni0.9O Fe0.2Ni0.8O
Co about 78nm Co about 78nm Co about 78nm
TiN about 20nm TiN about 20nm TiN about 20nm
NiO 50nm NiFeO 50nm NiFeO 87nm
Co 150nm Co 150nm Co 150nm
Ti 20nm Ti 20nm Ti 20nm
SiO about 1000nm SiO about 1000nm SiO about 1000nm
Electrical properties
0.00E+00
5.00E-03
1.00E-02
1.50E-02
2.00E-02
2.50E-02
3.00E-02
3.50E-02
4.00E-02
0 500 1000 1500 2000 2500 3000
Capacity/Surfacearea(F/m2)
Surface Area （1.00E-12m2）
C/S vs S
NiO NiFe90/10 NiFe80/20
0.00E+00
1.00E+02
2.00E+02
3.00E+02
4.00E+02
5.00E+02
6.00E+02
0 500 1000 1500 2000 2500 3000
Current/Surfacearea(A/m2)
Surface area (1.00E-12m2)
I/S vs S
NiO NiFe90/10
0.00E+00
2.00E-01
4.00E-01
6.00E-01
8.00E-01
1.00E+00
1.20E+00
1.40E+00
1.60E+00
1.80E+00
0 100 200 300 400 500 600 700
Current/Surfacearea(A/m2)
Surface area (1.00E-12m2)
I/S vs S
NiFe80/20
-1.40E-04
-1.20E-04
-1.00E-04
-8.00E-05
-6.00E-05
-4.00E-05
-2.00E-05
0.00E+00
2.00E-05
4.00E-05
6.00E-05
-6 -4 -2 0 2 4 6
Current(Ampere)
Voltage (Volts)
NiO I/Vcurve
-4 to 4 4 to -4
-3.00E-06
-2.00E-06
-1.00E-06
0.00E+00
1.00E-06
2.00E-06
3.00E-06
4.00E-06
5.00E-06
-6 -4 -2 0 2 4 6
Current(Ampere)
Voltage (Volts)
Ni90Fe10O I/V curve
-4 to 4 4 to -4
Figure 3. Set and Reset Hysteresis Curves
7. Lift off:
Solvent: NMP
• Equipment, steps and parameters
 Results
The pictures below are our bottom electrode, bottom electrode and cell isolation, and our final memory cell.
(The size of the contact pad is 120µm× 120µm )
Figure 10. top electrode Figure 11. top electrode and cell isolation Figure 12. top electrode, cell isolation and bottom electrode
We measured the curves of unit area capacitance and current vs surface area, and the current-voltage curve for
memory cells with different isolation material: NiO, Ni90Fe10O, and Ni80Fe20O.
Figure 7. Spin coater Figure 8. Mask aligner Figure 9. Sputtering
 Plans for continuing research:
There are also a few parameters that can be measured in the further study. Including FexNi1-xO sheet
Resistance, Pre Forming Resistance, Forming Voltage, Forming Current, Set Voltage, Set Current, Reset Voltage
and Reset Current.
Equipment includes: Spin coater Laurell WS-650MZ-23NPP, Isotemp water heater, SUSS MJB4 mask aligner, Plasma
Etch, Branson 2800.
Figure 13. microscope Figure 14. HP 4145B semiconductor parameter analyzer Figure 15. HP 4192A impedance analyzer
Scan speed: 1V/s Scan speed: 1V/s Scan speed: 1V/s
Scan speed: 1V/s
Area: 6µm× 6µm
Scan speed: 1V/s
Area: 40µm× 40µm
Scan speed: 0. 1V/s
Area: 40µm× 40µm
1. Fujisaki, Y. Review of Emerging New Solid-State Non-Volatile Memories. Jpn. J. Appl. Phys. 52, 040001 (2013).
2. Ma, G. et al. Effects of Standard Free Energy on NiO Bipolar Resistive Switching Devices. IEEE Trans. Electron Devices 61, 1237–1240 (2014).
3. Guziewicz, M. & Grochowski, J. Electrical and optical properties of NiO films deposited by magnetron sputtering. Opt. Appl. XLI, 1–10 (2011)
4. Compton, M. S. The Electric, Magnetic and Optical Characterization of Permalloy Oxide Grown by Dual Ion Beam Sputtering. (2014).
5. Goux, L. et al. Role of the anode material in the unipolar switching of TiNNiONi cells. J. Appl. Phys. 113, 054505 (2013).
6. Meena, J. S., Sze, S. M., Chand, U. & Tseng, T.-Y. Overview of emerging nonvolatile memory technologies. Nanoscale Res. Lett. 9, 526 (2014).
Scan speed: 1V/s
Area: 40µm× 40µm
 1. Each I-V curve for NiO, Ni90Fe10O, and Ni80Fe20O show different resistivity under the same
voltage when the voltage changes in opposite direction. Our Permalloy memory cell have bi-
state, which makes it able to memorize information. Comparing the I-V curves of NiO under
two different scan speed: 1V/s and 0.1V/s, the resistance difference it greater with lower scan
speed, which is the opposite to the capacitance effect. So we consider the ionic motion exist.
 2. The C/S vs S curve is obtained under scan speed as 1V/s. From our data, we got the
capacitance for different material with different area. The capacitance has order of
magnitudes as 3pF, which gives negligible current at 1V/s. That is to say, when the device is
memorizing information, the current goes through C part is small, which is power efficient.
 3. I/S vs S curve is measured under the same voltage: 1V. The resistivity of Fe0.1Ni0.9O is much
smaller than Fe0.2Ni0.8O, which is consistent with the result of measurement done by linear
four point probe. That is to say, Fe0.2Ni0.8O is possible to be a more power economical
material for the cell isolation.
Figure 16. equivalent device
Schottky
diode
capacitance
resistance
switch