Under a Compulsory Course of "Materials Physics and Technology for Nanoelectronics" a team of BE Students of Nanotechnology, Nanoelectronics and Bionnotechnology prepared this seminar for Prof. Marc Heyns, marc.heyns@imec.be Kapeldreef 75, B-3001 Heverlee IMEC Building IV, room 2.33
Tel: 016 281 348
Invited lecture of the Simposium N "Surface Engineering - functional coatings and modified surfaces" at the XIII SBPMat (Brazilian MRS) meeting, in João Pessoa (Brazil). The lecture took place on September 29th, 2014.
The speaker was Christopher Muratore, "Wright Brothers Institute Endowed Chair Professor" at the Department of Chemical and Materials Engineering from University of Dayton (USA).
A detailed presentation on Photoconducting Cells - its design, construction and working presented as a semester assignment made possibly as a reference guide for engineering students.
Invited lecture of the Simposium N "Surface Engineering - functional coatings and modified surfaces" at the XIII SBPMat (Brazilian MRS) meeting, in João Pessoa (Brazil). The lecture took place on September 29th, 2014.
The speaker was Christopher Muratore, "Wright Brothers Institute Endowed Chair Professor" at the Department of Chemical and Materials Engineering from University of Dayton (USA).
A detailed presentation on Photoconducting Cells - its design, construction and working presented as a semester assignment made possibly as a reference guide for engineering students.
Pentacene-Based Organic Field-Effect Transistors: Analytical Model and Simula...IDES Editor
Organic Field-Effect Transistors, OFETs, attract
much interest recently and their proficiency and hence
applications are being enhanced increasingly. However, only
analytical model of old field-effect transistors, developed for
silicon-based transistors, and their relevant numerical
analyses have been used for such devices, so far. Increasing
precision of such models and numerical methods are essential
now in order to modify OFETs and propose more effective
models and methods. This study pegs at comparing current
analytical model, simulation methods and experiment data
and their fitness with each other. Certainly, four aspects of
results of three abovementioned approaches were examined
comparatively: sub-threshold slope, on-state drain current,
threshold voltage and carrier mobility. We embark to analyze
related experiment data of OFETs made by pentacene, as the
organic material, along with various organic gate insulators
including CyEP, PVP, PMMA, Parylene-C and Polyimide and
then to offer their results, comparatively.
Exploiting the potential of 2-((5-(4-(diphenylamino)- phenyl)thiophen-2-yl)me...Akinola Oyedele
A comprehensive experimental study is reported on the optical and electrical characteristics of 2-((5-(4-
(diphenylamino)phenyl)thiophen-2-yl)methylene)malononitrile (DPTMM) when used as molecular donor
in an organic solar cell (OSC) device structure.
OFET Preparation by Lithography and Thin Film Depositions ProcessTELKOMNIKA JOURNAL
The length of the channel OFET based thin film is determined during preparation takes place
using the technique of lithography and mask during the metal deposition process. The lithography
technique is the basic process steps in the manufacture of semiconductor devices. Lithography is the
process of moving geometric shapes mask pattern to a thin film of material that is sensitive to light. The
pattern of geometric shapes on a mask has specifications, as follows: long-distance source and drain
channels varied, i.e. 100 μm, the width of the source and drain are made permanent. Bottom contact
OFET structure has been created using a combination of lithography and thin film deposition processes.
What can we learn from molecular dynamics simulations of carbon nanotube and ...Stephan Irle
We present the results of nonequilibrium molecular dynamics (MD) simulations of catalytic and non-catalytic carbon nanostructure formation processes, including single-walled carbon nanotube (SWCNT) and graphene nucleation and growth. In the talk, we discuss the significance of the findings in the light of more traditional, static descriptions of growth reaction mechanisms, and highlight differences as well as commonalities.
This presentation summarizes history and recent development of perovskite solar cells. If you have any questions or comments, you can reach me at agassifeng@gmail.com
Plenary lecture of the XIII SBPMat (Brazilian MRS) meeting, given on September 30th 2014 by Karl Leo, professor of optoelectronics at Dresden University of Technology (Germany) and director of the Solar and Photovoltaic Engineering Research Center at KAUST (Saudi Arabia).
Pushing the limits of ePRTC: 100ns holdover for 100 daysAdtran
At WSTS 2024, Alon Stern explored the topic of parametric holdover and explained how recent research findings can be implemented in real-world PNT networks to achieve 100 nanoseconds of accuracy for up to 100 days.
Goodbye Windows 11: Make Way for Nitrux Linux 3.5.0!SOFTTECHHUB
As the digital landscape continually evolves, operating systems play a critical role in shaping user experiences and productivity. The launch of Nitrux Linux 3.5.0 marks a significant milestone, offering a robust alternative to traditional systems such as Windows 11. This article delves into the essence of Nitrux Linux 3.5.0, exploring its unique features, advantages, and how it stands as a compelling choice for both casual users and tech enthusiasts.
Observability Concepts EVERY Developer Should Know -- DeveloperWeek Europe.pdfPaige Cruz
Monitoring and observability aren’t traditionally found in software curriculums and many of us cobble this knowledge together from whatever vendor or ecosystem we were first introduced to and whatever is a part of your current company’s observability stack.
While the dev and ops silo continues to crumble….many organizations still relegate monitoring & observability as the purview of ops, infra and SRE teams. This is a mistake - achieving a highly observable system requires collaboration up and down the stack.
I, a former op, would like to extend an invitation to all application developers to join the observability party will share these foundational concepts to build on:
Threats to mobile devices are more prevalent and increasing in scope and complexity. Users of mobile devices desire to take full advantage of the features
available on those devices, but many of the features provide convenience and capability but sacrifice security. This best practices guide outlines steps the users can take to better protect personal devices and information.
GraphSummit Singapore | The Art of the Possible with Graph - Q2 2024Neo4j
Neha Bajwa, Vice President of Product Marketing, Neo4j
Join us as we explore breakthrough innovations enabled by interconnected data and AI. Discover firsthand how organizations use relationships in data to uncover contextual insights and solve our most pressing challenges – from optimizing supply chains, detecting fraud, and improving customer experiences to accelerating drug discoveries.
Sudheer Mechineni, Head of Application Frameworks, Standard Chartered Bank
Discover how Standard Chartered Bank harnessed the power of Neo4j to transform complex data access challenges into a dynamic, scalable graph database solution. This keynote will cover their journey from initial adoption to deploying a fully automated, enterprise-grade causal cluster, highlighting key strategies for modelling organisational changes and ensuring robust disaster recovery. Learn how these innovations have not only enhanced Standard Chartered Bank’s data infrastructure but also positioned them as pioneers in the banking sector’s adoption of graph technology.
Communications Mining Series - Zero to Hero - Session 1DianaGray10
This session provides introduction to UiPath Communication Mining, importance and platform overview. You will acquire a good understand of the phases in Communication Mining as we go over the platform with you. Topics covered:
• Communication Mining Overview
• Why is it important?
• How can it help today’s business and the benefits
• Phases in Communication Mining
• Demo on Platform overview
• Q/A
Alt. GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using ...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
DevOps and Testing slides at DASA ConnectKari Kakkonen
My and Rik Marselis slides at 30.5.2024 DASA Connect conference. We discuss about what is testing, then what is agile testing and finally what is Testing in DevOps. Finally we had lovely workshop with the participants trying to find out different ways to think about quality and testing in different parts of the DevOps infinity loop.
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
GridMate - End to end testing is a critical piece to ensure quality and avoid...ThomasParaiso2
End to end testing is a critical piece to ensure quality and avoid regressions. In this session, we share our journey building an E2E testing pipeline for GridMate components (LWC and Aura) using Cypress, JSForce, FakerJS…
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
Dr. Sean Tan, Head of Data Science, Changi Airport Group
Discover how Changi Airport Group (CAG) leverages graph technologies and generative AI to revolutionize their search capabilities. This session delves into the unique search needs of CAG’s diverse passengers and customers, showcasing how graph data structures enhance the accuracy and relevance of AI-generated search results, mitigating the risk of “hallucinations” and improving the overall customer journey.
2. 2
Overview
Introduction
o Memory types
o FET-based memories
Working principle
o Charge trapping
o Band diagram analysis
o Programming sequence
Comparison of two devices
o PVA & PCBM
o PαMS & Pentacene
Conclusion
6. 6
Charge Trapping
Organic field-effect transistors with polarizable gate insulators
Howard E. Katz et al., Appl. Phys. 2002, 91, 1572–6
“There is growing appreciation of the capability to fabricate
various kinds of electronic circuits from organic materials.”
Introduction
7. 7
From MOS to FGMOS
Based on MOSFET
transistor
Gate is uncoupled, memory
is non-volatile
Charges are trapped in the
floating gate
Data sensed by Vth shift of
MOSFET
Data represented by
carriers stored in the
floating gate
J. D. Casperson et al., CIT, Journal of Applied Physics, 2009, 92, 261
Working principle
8. 8
Influences on Vth
Traps close to/in the
channel
Charge injection from
the semiconductor into
the dielectric
Slow reactions
of charge carriers in the
organic semiconductor
Mobile ions in the
semiconductor
Ferroelectric effect
Mobile ions in th
dielectric
Charge injection from the
gate electrode
M. Egginger et al., Monatsh Chem, 2009,140,735
Working principle
11. 11
Working principle
When applying an external voltage to the gate, charges
tunnel from the channel to the interface (~104
carriers to
represent 1 bit)
Both electrons and holes
Programming sequence
14. 14
Ambipolar vs unipolar
Ambipolar semiconductor: both p-type and n-type operations are
realised (eg. program by holes and erase by electrons)
→ Balanced mobility (n and p) and ON/OFF operation needed
Insufficient electron mobility
→ Trapped holes cannot be erased
Wide memory window
Working principle
15. 15
Stacking holes for memory
usage
Example: electrons tunnel back too easy -> poor
retention time
Negative part of memory window is useful
M. Debucquoy et al , Organic electronics 2009, 10, 1252
Working principle
16. 16
Search for improvement in terms of Materials and Scheme
Singh et al, 2004
Heremans et al, 2009
Comparison of two devicesComparison of
two devices
18. 18
Comparison - Semiconductor
PCBM
p-type
High mobility
High ON/OFF current ratio
T.B. Singh et al, Appl. Phys. Lett.
2004, 85, 22, 5409
Pentacene (~14 Å)
o 5 benzene rings
o Crystal Structure
p-type
High Mobility
Reasonable ON/OFF current ratio
IBM Zurich,AFM Image
Penacene Aug 2009
Campbell, 1961
molecular packing
Prof. Takao Someya
Comparison of
two devices
19. 19
Comparison - Electret
Charge trapping within bulk
or at interface
Hydrophilic
T.B. Singh et al, Appl. Phys. Lett.
2004, 85, 22, 5409
PαMS (polyalpha-methylstyrene)
Hydrophobic
(Insulator coated with a very thin-layer)
Reduces: trapped electrons at the
interface between the pentacene
and the gate dielectric
To suppress the degradation of the
on–off ratio
High-quality, electron-trap free
surface allowing excellent
electron transport
Comparison of
two devices
20. 20
Comparison - Adjacent materials
Cr for source & drain:
o No diffusion into PCBM
ITO gate
No insulator layer
Heptadecafluoro-1-decanethiol
(Thiol monolayer)
Other materials:
o Au ; SiO2 ; n++Si
Improved
interface:
Improves pentacene layer growth
Reduces interface states
Mobility increases
Threshold voltage approaches zero
Appl. Phys. Lett. 88, 222103 (2006)
Improve the interface
Contacts <-> Semiconductor layer
Comparison of
two devices
21. 21
Performance measurements (Singh)
T.B. Singh et al, Appl. Phys. Lett.
2004, 85, 22, 5409
T.B. Singh et al, Appl. Phys. Lett.
2004, 85, 22, 5409
Comparison of
two devices
22. 22
Performance Measurements (Herem.)
- pulse (write)
h trapped
Programming voltage Transistor’s mobility
e-
trapped
dielectric
ΔVon =2V
Gate
Decrease 1.9V->1.4V
h mobility decrease
Shift VON+ & VON-
Retention time
Memory Window
+pulse (erase)
e trapped
Saturation
Comparison of
two devices
23. 23
Performance Comparison
FLASH
[a]
Floating
Gate
[b]
Ferroelectric
[c]
PVA &
PCBM
[d]
PαMS &
pentacene
[e]
Retention time (h) ~ 3 years ~ 11 ~ 168 > 15 > 3 months
Programming time (s) 0.8 1 0.3e-3 500 1.5e-3
Programming/erasing
voltage (V)
+8/-8 +6/-6 +77.5/-77.5 +50/-50 -15/+15
[a] R. Bez et al, Proc. of the IEEE 2003, 91, 4, 489
[b] S. Kolliopoulou et al, Microel. Eng. 2004, 73-74, 725
[c] R.C.G. Naber et al, Nat. Mater. 2005, 4, 243
[d] T.B. Singh et al, Appl. Phys. Lett. 2004, 85, 22, 5409
[e] P. Heremans et al, Appl. Phys. Lett. 2009, 95, 103311
Comparison of
two devices
24. 24
Conclusion
Conclusion from Singh organic memory:
o The combination of PVA & PCBM
does not make a good memory-element
Conclusion from Heremans organic memory:
o It is possible to fabricate a device with
reprogrammable nonvolatile organic
memory usable in Plastic Logic.
“Organic Transistor/Memory devices will reach $21.6 Billion in 2015”, NanoMarkets (2001)
Conclusion
25. 25
References
K.J. Baeg et al, Adv. Funct. Mater. 2008, 18, 3678-3685
T.B. Singh et al, Appl. Phys. Lett. 2004, 85, 5409-5411
K.J. Baeg et al, Adv. Mater. 2006, 18, 3179-3183
Q.D. Ling et al, Progr. Polym. Sci. 2008, 33, 917-978
R. Bez et al, Proc. of the IEEE 2003, 91, 4, 489-502
S. Kolliopoulou et al, Microel. Eng. 2004, 73-74, 725-729
R.C.G. Naber et al, Nat. Mater. 2005, 4, 243-248
P. Heremans et al, Appl. Phys. Lett. 2009, 95, 103311
J. Kang et al, J. Am. Chem. Soc., 2008, 130 (37), 12273–12275
K. Myny et al, Appl. Phys. Lett. 2006, 88, 222103
K. Asadi et al, Nature Materials 2008, 7, 547
Forbes, free patents onl. 2005, 10/775908
H.E. Katz et al, Appl. Phys. 2002, 91, 1572–6
Cyferz, Wikipedia 2007, Flash_cell_structure
Cyferz, Wikipedia 2008, 1T_FeRAM_cell_structure
Cyferz, Wikipedia 2007, SONOS_cell_structure
Editor's Notes
Memory types
Two main branches: volatile and non-volatile Volatile memory is lost when the power is turned off.
Three catagories in the memory, based on the mechanistic analogy between the polymer memory element and one of the three primary circuit elements (capacitor, transistor and resistor).
Main driving force behind memory technology: higher capacity, higher system performance, lower power consumption, smaller dimensions, lower system cost.
These demands are met by further scaling of the inorganic 2D-chips:new fabrication technologies, new structures (double-/triple-gate & multi-core), new materials (strained Si, high K dielectrics, metal gate materials).
You can work with Organic Field Effect Transistors.
Three types are used:
Floating gate OFET
The charges are stored on a conducting or semiconducting layer that is completely surrounded by a dielectric, the embedded metal layer serves as the floating gate.
Ferroelectric OFET
The gate insulator is composed of a ferroelectric material the memory effect arises from attenuation of the surface charge density in the semiconductor by Pr of the ferroelectric
Charge trapping OFET
In charge trapping OFET memory, the charges are stored in an appropriate dielectric layer with electret properties
2001 Organic field-effect transistors with polarizable gate insulators
Howard E. Katz, X. Michael Hong, Ananth Dodabalapur, and Rahul Sarpeshkar
J Appl Phys 2002;91:1572–6
storage or polarization between the gate contact and the semiconductor channel imposes an added voltage between the gate and channel, thereby altering the effective channel voltage relative to the voltage nominally applied at the gate contact (the ‘‘gate voltage,’’ Vg!). The charge may be stored and/or polarized in domains within the bulk of the dielectric, or at interfaces between the gate contact and channel
“There is growing appreciation of the capability to fabricate
various kinds of electronic circuits from organic materials.”
There are several reasons why it might be desirable to modify an organic-based transistor so that the voltage applied to its channel is shifted relative to Vg . Besides the creation of additional electronic states, which can be read as stored information, devices with polarized gate dielectrics can function more effectively in certain circuits.
Applications demanding inexpensive processing and large coverage area are attractive for ‘‘organic electronics.’’
To be a non-volatile transistor for application in memory, the charges must be stored or polarized in domains within the bulk of the dielectric layer, or at interfaces between the gate contact and the semiconductor channel. An additional voltage, via charge storage or
polarization, is thus introduced between the gate and the semiconductor channel to alter the charge distribution in the transistor.
Generally SONOS is very similar to standard double polysilicon Flash, but at least in theory offers higher quality storage. This is due to the smooth homogeneity of the Si3N4 film compared with polycrystalline film which has tiny irregularities. Flash requires the construction of a very high-performance insulating barrier on the gate leads of its transistors, often requiring as many as nine different steps, whereas the oxide layering in SONOS can be more easily produced on existing lines and more easily combined with CMOS logic. (wiki)
Source figure: “Materials issues for layered tunnel barrier structures” J. D. Casperson et al. JOAP
Top contact of bottom contact?
Blue = Effects of mobile charges at the channel
Green = Effects resulting in a polarization of the gate
Dielectric
Red = Charge injection from the gate electrode into the
dielectric
“
The IV characteristics above taken at room temperature shows how the threshold voltage of the device was shifted after the floating gate was charged with different number of electrons. Charging the transistor with programming pulses of x seconds leads to a different V_threshold.
(For a pentacene device: ID vs. VGS in the initial state (dotted line) and after programming pulses with tprog = 1.5 ms and VGS,prog = 17 V
(filled squares)/17 V (filled circles)/20 V (open squares)/20 V (open circles).)
Ambipolar OFETs have been difficult to produce due to the lack of materials that exhibit both reasonably high electron and hole mobilities.
This problem arises mostly due to the strong preference of organic materials either to have high electron mobility or hole mobility and not both at the same time.
When pentacene is exposed to air, it leads to additional traps for the electrons (probably moisture related), reducing severly the mobility of them.
-&gt; V_on cannot be shifted towards a more positive Vgs value anymore.
Ambipolarity of the organic semiconductor is a strict requirment for achieving reprogrammability at low fields!
Retention measurement for a pentacene device. The first point of the Von curve is reached after a pulse with |VGS,prog| = 20 V and tprog = 1.5 ms.
The first point of the Von+ curve is reached after a pulse with |VGS,prog| = 20 V and tprog = 1.5 ms.
This indicates that the electrons are trapped in shallow traps and that the positive part of the memory window cannot be used for
practical applications. Von on the other hand, is only reduced to 3 V after 3 months. The holes are deeply trapped in a more complex distribution, making it possible to use the negative part of the memory window
The most important articles from this part
Memory Window + Retention Time
Measured:
Transfer characteristics ( VON)
Mobility (μ )
μ – hole mobility
Three bottom slides: time analysis -&gt; Feasible Memory[(Cycles ; Transfer characteristic (time); Von(time)]
Observed:
High programming voltages
Shift in turn-on voltage -&gt; Explained by trapping of holes and electrons at the gate dielectric
Low programming voltages
Electric field over PalfaMS is too low for the holes and electron to be injected into the dielectric stack (no charges trapped)
Note: Between 10-14V programing pulse Holes tunnel in negative pulse, resulting in more negative Von
So: useful part is: programming between: 14-20V (15V)
Transistor’s mobility – is it really important this difference: 0.05?
Made by trapping of holes or electrons? Damaging of pentacene/PalfaMS
Fig 3 Time analysis – Cycles§
One cycle=write and erase
After 500 still works as a memory transistor with two distinct states
Fig.4 Retention Time
After 3month all trapped electrons are lost and Von+ reduced to 0V