SlideShare a Scribd company logo
1 of 35
Download to read offline
GHT 205 Department of Geology, University of Dhaka SMK
Digital Circuit
Data and control instructions move inside a computer
by means of pulses of electricity. Certain components
of computers combine these pulses following a set of
rules. These components are logic elements.
GHT 205 Department of Geology, University of Dhaka SMK
Logic Gates
• All digital computers for the past 50 years have been
constructed using the same type of components.
• These components are called logic gates.
• Logic gates have been implemented in many different ways.
• Currently, logic gates are most commonly implemented using
electronic VLSI transistor logic.
GHT 205 Department of Geology, University of Dhaka SMK
Logic Gates
• All basic logic gates have the ability to accept either one or two
input signals (depending upon the type of gate) and generate
one output signal.
GHT 205 Department of Geology, University of Dhaka SMK
Logic Gates
• Input and Output signals are binary.
• binary:
– always in one of two possible states;
– typically treated as:
» On / Off (electrically)
» 1 / 0
» True / False
• There is a delay between when a change happens at a
logic gates inputs and when the output changes, called
gate switching time.
• The True or False view is most useful for thinking about
the meaning of the basic logic gates.
GHT 205 Department of Geology, University of Dhaka SMK
Logic Gates
• The Three basic logic gates are:
– AND
– OR
– NOT
• Each of these gates may be drawn in either
– A generic form; or
– An electrical engineering form (more common in text
books)
GHT 205 Department of Geology, University of Dhaka SMK
Logic Gates : AND
The Output signal from an AND gate is True (on, 1) if and
only if both Input signals are True (on, 1).
The Output signal from an AND gate is False (off, 0),
otherwise.
GHT 205 Department of Geology, University of Dhaka SMK
AND gate
•The diagram of the AND gate looks like a capital letter D with two "prongs" on the left
(the inputs) and one "prong" on the right (the output).
•if either of the inputs is 0, then the output of the AND gate is 0. Thus, in order to get an
AND gate to output 1, both inputs to it must be 1
Symbol
Boolean
Algebra
BA
Logic
table/Truth
table
GHT 205 Department of Geology, University of Dhaka SMK
AND Gate:
Behaviour using a Truth Table analysis and an animation.
Truth Table: The table shows that the AND gate responds with a high at the output if the signal applied to the
input A and B are both high.
5v
5v
5v
Input A
Output X
Input B
AND
Animation: In order to see how it works, the gate has been connected to 2 switches and LED. Continue to
see the syste i actio …
Logic 0
Logic 0
Logic 0
Logic 0
Logic 0
Logic 1
Logic 1
Logic 0
Logic 0
Logic 1
Logic 1
Logic 1
A B X
0 0 0
0 1 0
1 0 0
1 1 1
GHT 205 Department of Geology, University of Dhaka SMK
Logic Gate - OR
The Output signal from an OR gate is True (on, 1) if either,
or both, Input signals are True (on, 1).
The Output signal from an OR gate is False (off, 0) if and
only if both Input signals are False (off, 0).
GHT 205 Department of Geology, University of Dhaka SMK
OR gate
•if either of the inputs is 1, then the output of the OR gate is 1. Thus, in
order to get an OR gate to output 0, both inputs to it must be 0
Symbol
Boolean
Algebra
BA
Logic
table
GHT 205 Department of Geology, University of Dhaka SMK
OR Gate
Behaviour using a Truth Table analysis and an animation.
Truth Table: The table shows that the OR gate responds with a high at the output if the signal
applied to the input A or B is high.
Input A
Output X
Input B
OR
5v
5v
5v
Animation: In order to see how it works, the gate has been connected to 2 switches and LED. Continue to
see the syste i actio …
Slide #11
Logic 0
Logic 0
Logic 0
Logic 0
Logic 1
Logic 1
Logic 1
Logic 1
Logic 0
Logic 1
Logic 1
Logic 1
A B X
0 0 0
0 1 1
1 0 1
1 1 1
GHT 205 Department of Geology, University of Dhaka SMK
Logic Gates - NOT
• The Output signal from a NOT gate is True (on, 1) if and
only if the Input signal is False.
• The Output signal from a NOT gate is False (off, 0) if
and only if the Input signal is True.
GHT 205 Department of Geology, University of Dhaka SMK
NOT gate
•The operation of reversing the input state
Symbol
Boolean
Algebra
A
Logic
table
GHT 205 Department of Geology, University of Dhaka SMK
5v
NOT Gate (inverter)
Input A Output X
A X
0 1
1 0
Truth Table: Is a chart that lists the input condition on the left and the gate’s output
response on the right. The table shows that the NOT gate responds at the output
with the inverse of the signal applied to the input.
Animation: In order to see how it works, the gate has been connected to a switch and LED. Continue to see
the syste i actio …
Slide #14
Logic 1
OFF
Logic 0
ON
Logic 1
OFF
Logic 0
ON
Logic 1
OFF
Logic 0
ON
GHT 205 Department of Geology, University of Dhaka SMK
Esho Nije Kori …
a) Draw a circuit : input XY , output X’Y
b) Draw a circuit : input XY , output XY’
a) Draw a circuit : input XY , output X’+Y
b) Draw a circuit : input XY , output X+Y’
GHT 205 Department of Geology, University of Dhaka SMK
Secondary-NAND gate
•The output of the NAND gate is the negation, or reverse of the output
of an AND gate with the same inputs (0 negated equals 1, and 1 negated
equals 0).
Symbol
Boolean
Algebra
BA
Logic
table
GHT 205 Department of Geology, University of Dhaka SMK
Secondary - NOR gate
•NOR stands for "Negated OR". Thus, the output of the NOR gate is
the negation, or reverse of the output of an OR gate with the same
inputs.
Symbol
Boolean
Algebra
BA
Logic
table
GHT 205 Department of Geology, University of Dhaka SMK
Secondary – XOR/EXOR gate
•EOR stands for "Exclusive OR". The thing to remember about EOR gates
is this: An EOR gate will output 1 only if one of the inputs is 1 and the
other input 0. If both inputs are the same (1 and 1, or 0 and 0), then
EOR outputs 0
Symbol
Boolean
Algebra
BA
Logic
table
GHT 205 Department of Geology, University of Dhaka SMK
Boolean Theorem
Boolean theorems are used to simplify or manipulate logic functions.
OR
A+0=A
A+1=1
A+A=A
A+A’=
AND
A.0=0
A.1=A
A.A=A
A.A’=
NOT
A+A’=
A.A’=
A’’=A
DeMorgan’s Theorem
A+B=A. B
A.B= A+ B
GHT 205 Department of Geology, University of Dhaka SMK
Proof A+B=A. B
GHT 205 Department of Geology, University of Dhaka SMK
Proof A+B=A. B
GHT 205 Department of Geology, University of Dhaka SMK
Exercise
=
GHT 205 Department of Geology, University of Dhaka SMK
Universality of NAND Gate
Any Boolean function can be implemented using AND, OR and NOT
gates. So if AND, OR and NOT gates can be implemented using NAND
gates only, then the universality of NAND gate will be proved…..
GHT 205 Department of Geology, University of Dhaka SMK
Universality of NOR Gate
GHT 205 Department of Geology, University of Dhaka SMK
Combinational Logic Using Universal Gates
X = (AB) (CD)
X = (AB) + (CD)
X = (AB) + (CD)
GHT 205 Department of Geology, University of Dhaka SMK
GHT 205 Department of Geology, University of Dhaka SMK
Adders: Logical gates to add two numbers
• We need to use a circuit with more than one output, which clearly more powerful
than a Boolean expression.
GHT 205 Department of Geology, University of Dhaka SMK
How to add binary numbers
• Consider adding two 1-bit binary numbers x and y
 0+0 = 0
 0+1 = 1
 1+0 = 1
 1+1 = 10
• Carry is x AND y
• Sum is x XOR y
• The circuit to compute this is called a half-adder
x y Carry Sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
GHT 205 Department of Geology, University of Dhaka SMK
x y s c
1 1 0 1
1 0 1 0
0 1 1 0
0 0 0 0
= s (sum)
c (carry)
GHT 205 Department of Geology, University of Dhaka SMK
x 1 1 1 1 0 0 0 0
y 1 1 0 0 1 1 0 0
c 1 0 1 0 1 0 1 0
s (sum) 1 0 0 1 0 1 1 0
c (carry) 1 1 1 0 1 0 0 0
HAX
Y
S
C
HAX
Y
S
C
x
y
c
c
s
HAX
Y
S
C
HAX
Y
S
C
x
y
c
A full adder is a circuit that accepts as input thee bits x, y, and c, and produces as
output the binary sum cs
GHT 205 Department of Geology, University of Dhaka SMK
• The full circuitry of the full adder
x
y
s
c
c
GHT 205 Department of Geology, University of Dhaka SMK
• We can use a half-adder and full adders to
compute the sum of two Boolean numbers
1 1 0 0
+ 1 1 1 0
010?
001
Adding bigger binary numbers
GHT 205 Department of Geology, University of Dhaka SMK
Adding bigger binary numbers
• Just chain one half adder and full adders together,
e.g., to add x=x3x2x1x0 and y=y3y2y1y0 we need:
HAX
Y
S
C
FAC
Y
X
S
C
FAC
Y
X
S
C
FAC
Y
X
S
C
x1
y1
x2
y2
x3
y3
x0
y0
s0
s1
s2
s3
c
GHT 205 Department of Geology, University of Dhaka SMK
Adding bigger binary numbers
• A half adder has 4 logic gates
• A full adder has two half adders plus a OR gate
– Total of 9 logic gates
• To add n bit binary numbers, you need 1 HA and n-1 FAs
• To add 32 bit binary numbers, you need 1 HA and 31 FAs
– Total of 4+9*31 = 283 logic gates
• To add 64 bit binary numbers, you need 1 HA and 63 FAs
– Total of 4+9*63 = 571 logic gates
GHT 205 Department of Geology, University of Dhaka SMK
More about logic gates
• To implement a logic gate in hardware, you use a transistor
• Transistors are all enclosed in an IC , or integrated circuit
• The current Intel Pentium IV processors have 55 million
transistors!

More Related Content

What's hot

What's hot (20)

DIGITAL ELECTRONICS- Logic Gates
DIGITAL ELECTRONICS- Logic GatesDIGITAL ELECTRONICS- Logic Gates
DIGITAL ELECTRONICS- Logic Gates
 
Digital logic gate and its application
Digital logic gate and its applicationDigital logic gate and its application
Digital logic gate and its application
 
basic logic gates
 basic logic gates basic logic gates
basic logic gates
 
logic gates
logic gateslogic gates
logic gates
 
Presentation On Logic Gate
Presentation On Logic Gate Presentation On Logic Gate
Presentation On Logic Gate
 
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
 
Digital Logic Design
Digital Logic DesignDigital Logic Design
Digital Logic Design
 
Combinational circuits
Combinational circuitsCombinational circuits
Combinational circuits
 
Combinational circuits
Combinational circuitsCombinational circuits
Combinational circuits
 
Vhdl programming
Vhdl programmingVhdl programming
Vhdl programming
 
Universal logic gate
Universal logic gateUniversal logic gate
Universal logic gate
 
multiplexers and demultiplexers
 multiplexers and demultiplexers multiplexers and demultiplexers
multiplexers and demultiplexers
 
Latches and flip flop
Latches and flip flopLatches and flip flop
Latches and flip flop
 
Boolean Algebra
Boolean AlgebraBoolean Algebra
Boolean Algebra
 
Logic gates
Logic gatesLogic gates
Logic gates
 
Logic Gates
Logic GatesLogic Gates
Logic Gates
 
Nand gate
Nand gateNand gate
Nand gate
 
Logic gates
Logic gatesLogic gates
Logic gates
 
Chapter 4: Combinational Logic
Chapter 4: Combinational LogicChapter 4: Combinational Logic
Chapter 4: Combinational Logic
 
Subtractor
SubtractorSubtractor
Subtractor
 

Viewers also liked

Duet syllabus
Duet syllabusDuet syllabus
Duet syllabusmdnbd
 
Logic Gates Presentation
Logic Gates PresentationLogic Gates Presentation
Logic Gates Presentationnad407
 
COMPUTER ORGANIZATION - Logic gates, Boolean Algebra, Combinational Circuits
COMPUTER ORGANIZATION - Logic gates, Boolean Algebra, Combinational CircuitsCOMPUTER ORGANIZATION - Logic gates, Boolean Algebra, Combinational Circuits
COMPUTER ORGANIZATION - Logic gates, Boolean Algebra, Combinational CircuitsVanitha Chandru
 
Logic gate class 12
Logic gate class 12Logic gate class 12
Logic gate class 12Nipun Shah
 
The logic gate circuit
The logic gate circuitThe logic gate circuit
The logic gate circuitroni Febriandi
 

Viewers also liked (6)

Duet syllabus
Duet syllabusDuet syllabus
Duet syllabus
 
Logic Gates
Logic GatesLogic Gates
Logic Gates
 
Logic Gates Presentation
Logic Gates PresentationLogic Gates Presentation
Logic Gates Presentation
 
COMPUTER ORGANIZATION - Logic gates, Boolean Algebra, Combinational Circuits
COMPUTER ORGANIZATION - Logic gates, Boolean Algebra, Combinational CircuitsCOMPUTER ORGANIZATION - Logic gates, Boolean Algebra, Combinational Circuits
COMPUTER ORGANIZATION - Logic gates, Boolean Algebra, Combinational Circuits
 
Logic gate class 12
Logic gate class 12Logic gate class 12
Logic gate class 12
 
The logic gate circuit
The logic gate circuitThe logic gate circuit
The logic gate circuit
 

Similar to Digital Logic Gates and Combinational Circuits Explained

investagatory PHYSICS-LOGIC GATES
investagatory PHYSICS-LOGIC GATESinvestagatory PHYSICS-LOGIC GATES
investagatory PHYSICS-LOGIC GATESLakhvinder Singh
 
chapter 3 Boolean algebra (2).pptx
chapter 3 Boolean algebra (2).pptxchapter 3 Boolean algebra (2).pptx
chapter 3 Boolean algebra (2).pptxRithinA1
 
Logic gates 12th standard ivestigatory project
Logic gates 12th standard ivestigatory projectLogic gates 12th standard ivestigatory project
Logic gates 12th standard ivestigatory projectJaipuriar School
 
Digital Electronics-Review of Logic Gates.pptx
Digital Electronics-Review of Logic Gates.pptxDigital Electronics-Review of Logic Gates.pptx
Digital Electronics-Review of Logic Gates.pptxProfVilasShamraoPati
 
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates. Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates. Satya P. Joshi
 
Logic gatesrevised.ppt
Logic gatesrevised.pptLogic gatesrevised.ppt
Logic gatesrevised.pptDevanDev7
 
Lecture 04-Digital logic gates.pptx
Lecture 04-Digital logic gates.pptxLecture 04-Digital logic gates.pptx
Lecture 04-Digital logic gates.pptxWilliamJosephat1
 
Digital electronics lab
Digital electronics labDigital electronics lab
Digital electronics labswatymanoja
 
6_2019_04_09!08_59_48_PM logic gate_.ppt
6_2019_04_09!08_59_48_PM logic gate_.ppt6_2019_04_09!08_59_48_PM logic gate_.ppt
6_2019_04_09!08_59_48_PM logic gate_.pptnaghamallella
 
basic logic gate presentation date23.ppt
basic logic gate presentation date23.pptbasic logic gate presentation date23.ppt
basic logic gate presentation date23.pptnaghamallella
 

Similar to Digital Logic Gates and Combinational Circuits Explained (20)

Logic Minimization.pdf
Logic Minimization.pdfLogic Minimization.pdf
Logic Minimization.pdf
 
investagatory PHYSICS-LOGIC GATES
investagatory PHYSICS-LOGIC GATESinvestagatory PHYSICS-LOGIC GATES
investagatory PHYSICS-LOGIC GATES
 
chapter 3 Boolean algebra (2).pptx
chapter 3 Boolean algebra (2).pptxchapter 3 Boolean algebra (2).pptx
chapter 3 Boolean algebra (2).pptx
 
Logic gates (1)
Logic gates (1)Logic gates (1)
Logic gates (1)
 
Logic gates 12th standard ivestigatory project
Logic gates 12th standard ivestigatory projectLogic gates 12th standard ivestigatory project
Logic gates 12th standard ivestigatory project
 
Digital Electronics-Review of Logic Gates.pptx
Digital Electronics-Review of Logic Gates.pptxDigital Electronics-Review of Logic Gates.pptx
Digital Electronics-Review of Logic Gates.pptx
 
Deld lab manual
Deld lab manualDeld lab manual
Deld lab manual
 
Logic Gates
Logic GatesLogic Gates
Logic Gates
 
Digital logic
Digital logicDigital logic
Digital logic
 
logic gates
logic gates logic gates
logic gates
 
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates. Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
 
Logic gates 07 11-2014
Logic gates 07 11-2014Logic gates 07 11-2014
Logic gates 07 11-2014
 
Chapter 5 boolean algebra
Chapter 5 boolean algebraChapter 5 boolean algebra
Chapter 5 boolean algebra
 
Logic gatesrevised.ppt
Logic gatesrevised.pptLogic gatesrevised.ppt
Logic gatesrevised.ppt
 
LOGIC CKT.ppt
LOGIC CKT.pptLOGIC CKT.ppt
LOGIC CKT.ppt
 
Lecture 04-Digital logic gates.pptx
Lecture 04-Digital logic gates.pptxLecture 04-Digital logic gates.pptx
Lecture 04-Digital logic gates.pptx
 
Digital electronics lab
Digital electronics labDigital electronics lab
Digital electronics lab
 
logic gates.pptx
logic gates.pptxlogic gates.pptx
logic gates.pptx
 
6_2019_04_09!08_59_48_PM logic gate_.ppt
6_2019_04_09!08_59_48_PM logic gate_.ppt6_2019_04_09!08_59_48_PM logic gate_.ppt
6_2019_04_09!08_59_48_PM logic gate_.ppt
 
basic logic gate presentation date23.ppt
basic logic gate presentation date23.pptbasic logic gate presentation date23.ppt
basic logic gate presentation date23.ppt
 

More from Nazim Naeem

Cyclone 1970 : The Deadliest Disaster in the World
Cyclone 1970 : The Deadliest Disaster in the WorldCyclone 1970 : The Deadliest Disaster in the World
Cyclone 1970 : The Deadliest Disaster in the WorldNazim Naeem
 
Earthquake: The Unpredictable Hazard
Earthquake: The Unpredictable HazardEarthquake: The Unpredictable Hazard
Earthquake: The Unpredictable HazardNazim Naeem
 
Earthquake in Bangladesh
Earthquake in BangladeshEarthquake in Bangladesh
Earthquake in BangladeshNazim Naeem
 
River bank erosion, its migration, causes
River bank erosion, its migration, causesRiver bank erosion, its migration, causes
River bank erosion, its migration, causesNazim Naeem
 
An insight to petroleum generation of bangladesh
An insight to petroleum generation of bangladeshAn insight to petroleum generation of bangladesh
An insight to petroleum generation of bangladeshNazim Naeem
 
How to apply for spe student membership free
How to apply for spe student membership freeHow to apply for spe student membership free
How to apply for spe student membership freeNazim Naeem
 
Introduction to Crystallography
Introduction to CrystallographyIntroduction to Crystallography
Introduction to CrystallographyNazim Naeem
 
Mtm105 questions
Mtm105 questionsMtm105 questions
Mtm105 questionsNazim Naeem
 
Matlab Overviiew 2
Matlab Overviiew 2Matlab Overviiew 2
Matlab Overviiew 2Nazim Naeem
 
Matlab Overviiew
Matlab OverviiewMatlab Overviiew
Matlab OverviiewNazim Naeem
 

More from Nazim Naeem (12)

Cyclone 1970 : The Deadliest Disaster in the World
Cyclone 1970 : The Deadliest Disaster in the WorldCyclone 1970 : The Deadliest Disaster in the World
Cyclone 1970 : The Deadliest Disaster in the World
 
Earthquake: The Unpredictable Hazard
Earthquake: The Unpredictable HazardEarthquake: The Unpredictable Hazard
Earthquake: The Unpredictable Hazard
 
Earthquake in Bangladesh
Earthquake in BangladeshEarthquake in Bangladesh
Earthquake in Bangladesh
 
River bank erosion, its migration, causes
River bank erosion, its migration, causesRiver bank erosion, its migration, causes
River bank erosion, its migration, causes
 
An insight to petroleum generation of bangladesh
An insight to petroleum generation of bangladeshAn insight to petroleum generation of bangladesh
An insight to petroleum generation of bangladesh
 
Rajmahal Traps
Rajmahal TrapsRajmahal Traps
Rajmahal Traps
 
How to apply for spe student membership free
How to apply for spe student membership freeHow to apply for spe student membership free
How to apply for spe student membership free
 
Introduction to Crystallography
Introduction to CrystallographyIntroduction to Crystallography
Introduction to Crystallography
 
Mtm105 questions
Mtm105 questionsMtm105 questions
Mtm105 questions
 
Number System
Number SystemNumber System
Number System
 
Matlab Overviiew 2
Matlab Overviiew 2Matlab Overviiew 2
Matlab Overviiew 2
 
Matlab Overviiew
Matlab OverviiewMatlab Overviiew
Matlab Overviiew
 

Recently uploaded

Grant Readiness 101 TechSoup and Remy Consulting
Grant Readiness 101 TechSoup and Remy ConsultingGrant Readiness 101 TechSoup and Remy Consulting
Grant Readiness 101 TechSoup and Remy ConsultingTechSoup
 
POINT- BIOCHEMISTRY SEM 2 ENZYMES UNIT 5.pptx
POINT- BIOCHEMISTRY SEM 2 ENZYMES UNIT 5.pptxPOINT- BIOCHEMISTRY SEM 2 ENZYMES UNIT 5.pptx
POINT- BIOCHEMISTRY SEM 2 ENZYMES UNIT 5.pptxSayali Powar
 
Paris 2024 Olympic Geographies - an activity
Paris 2024 Olympic Geographies - an activityParis 2024 Olympic Geographies - an activity
Paris 2024 Olympic Geographies - an activityGeoBlogs
 
The byproduct of sericulture in different industries.pptx
The byproduct of sericulture in different industries.pptxThe byproduct of sericulture in different industries.pptx
The byproduct of sericulture in different industries.pptxShobhayan Kirtania
 
Call Girls in Dwarka Mor Delhi Contact Us 9654467111
Call Girls in Dwarka Mor Delhi Contact Us 9654467111Call Girls in Dwarka Mor Delhi Contact Us 9654467111
Call Girls in Dwarka Mor Delhi Contact Us 9654467111Sapana Sha
 
Beyond the EU: DORA and NIS 2 Directive's Global Impact
Beyond the EU: DORA and NIS 2 Directive's Global ImpactBeyond the EU: DORA and NIS 2 Directive's Global Impact
Beyond the EU: DORA and NIS 2 Directive's Global ImpactPECB
 
SOCIAL AND HISTORICAL CONTEXT - LFTVD.pptx
SOCIAL AND HISTORICAL CONTEXT - LFTVD.pptxSOCIAL AND HISTORICAL CONTEXT - LFTVD.pptx
SOCIAL AND HISTORICAL CONTEXT - LFTVD.pptxiammrhaywood
 
Measures of Dispersion and Variability: Range, QD, AD and SD
Measures of Dispersion and Variability: Range, QD, AD and SDMeasures of Dispersion and Variability: Range, QD, AD and SD
Measures of Dispersion and Variability: Range, QD, AD and SDThiyagu K
 
Separation of Lanthanides/ Lanthanides and Actinides
Separation of Lanthanides/ Lanthanides and ActinidesSeparation of Lanthanides/ Lanthanides and Actinides
Separation of Lanthanides/ Lanthanides and ActinidesFatimaKhan178732
 
Sanyam Choudhary Chemistry practical.pdf
Sanyam Choudhary Chemistry practical.pdfSanyam Choudhary Chemistry practical.pdf
Sanyam Choudhary Chemistry practical.pdfsanyamsingh5019
 
Mastering the Unannounced Regulatory Inspection
Mastering the Unannounced Regulatory InspectionMastering the Unannounced Regulatory Inspection
Mastering the Unannounced Regulatory InspectionSafetyChain Software
 
Q4-W6-Restating Informational Text Grade 3
Q4-W6-Restating Informational Text Grade 3Q4-W6-Restating Informational Text Grade 3
Q4-W6-Restating Informational Text Grade 3JemimahLaneBuaron
 
Software Engineering Methodologies (overview)
Software Engineering Methodologies (overview)Software Engineering Methodologies (overview)
Software Engineering Methodologies (overview)eniolaolutunde
 
Russian Call Girls in Andheri Airport Mumbai WhatsApp 9167673311 💞 Full Nigh...
Russian Call Girls in Andheri Airport Mumbai WhatsApp  9167673311 💞 Full Nigh...Russian Call Girls in Andheri Airport Mumbai WhatsApp  9167673311 💞 Full Nigh...
Russian Call Girls in Andheri Airport Mumbai WhatsApp 9167673311 💞 Full Nigh...Pooja Nehwal
 
BASLIQ CURRENT LOOKBOOK LOOKBOOK(1) (1).pdf
BASLIQ CURRENT LOOKBOOK  LOOKBOOK(1) (1).pdfBASLIQ CURRENT LOOKBOOK  LOOKBOOK(1) (1).pdf
BASLIQ CURRENT LOOKBOOK LOOKBOOK(1) (1).pdfSoniaTolstoy
 
Student login on Anyboli platform.helpin
Student login on Anyboli platform.helpinStudent login on Anyboli platform.helpin
Student login on Anyboli platform.helpinRaunakKeshri1
 
The Most Excellent Way | 1 Corinthians 13
The Most Excellent Way | 1 Corinthians 13The Most Excellent Way | 1 Corinthians 13
The Most Excellent Way | 1 Corinthians 13Steve Thomason
 
CARE OF CHILD IN INCUBATOR..........pptx
CARE OF CHILD IN INCUBATOR..........pptxCARE OF CHILD IN INCUBATOR..........pptx
CARE OF CHILD IN INCUBATOR..........pptxGaneshChakor2
 

Recently uploaded (20)

Grant Readiness 101 TechSoup and Remy Consulting
Grant Readiness 101 TechSoup and Remy ConsultingGrant Readiness 101 TechSoup and Remy Consulting
Grant Readiness 101 TechSoup and Remy Consulting
 
POINT- BIOCHEMISTRY SEM 2 ENZYMES UNIT 5.pptx
POINT- BIOCHEMISTRY SEM 2 ENZYMES UNIT 5.pptxPOINT- BIOCHEMISTRY SEM 2 ENZYMES UNIT 5.pptx
POINT- BIOCHEMISTRY SEM 2 ENZYMES UNIT 5.pptx
 
Paris 2024 Olympic Geographies - an activity
Paris 2024 Olympic Geographies - an activityParis 2024 Olympic Geographies - an activity
Paris 2024 Olympic Geographies - an activity
 
The byproduct of sericulture in different industries.pptx
The byproduct of sericulture in different industries.pptxThe byproduct of sericulture in different industries.pptx
The byproduct of sericulture in different industries.pptx
 
Call Girls in Dwarka Mor Delhi Contact Us 9654467111
Call Girls in Dwarka Mor Delhi Contact Us 9654467111Call Girls in Dwarka Mor Delhi Contact Us 9654467111
Call Girls in Dwarka Mor Delhi Contact Us 9654467111
 
Mattingly "AI & Prompt Design: Structured Data, Assistants, & RAG"
Mattingly "AI & Prompt Design: Structured Data, Assistants, & RAG"Mattingly "AI & Prompt Design: Structured Data, Assistants, & RAG"
Mattingly "AI & Prompt Design: Structured Data, Assistants, & RAG"
 
Beyond the EU: DORA and NIS 2 Directive's Global Impact
Beyond the EU: DORA and NIS 2 Directive's Global ImpactBeyond the EU: DORA and NIS 2 Directive's Global Impact
Beyond the EU: DORA and NIS 2 Directive's Global Impact
 
SOCIAL AND HISTORICAL CONTEXT - LFTVD.pptx
SOCIAL AND HISTORICAL CONTEXT - LFTVD.pptxSOCIAL AND HISTORICAL CONTEXT - LFTVD.pptx
SOCIAL AND HISTORICAL CONTEXT - LFTVD.pptx
 
Código Creativo y Arte de Software | Unidad 1
Código Creativo y Arte de Software | Unidad 1Código Creativo y Arte de Software | Unidad 1
Código Creativo y Arte de Software | Unidad 1
 
Measures of Dispersion and Variability: Range, QD, AD and SD
Measures of Dispersion and Variability: Range, QD, AD and SDMeasures of Dispersion and Variability: Range, QD, AD and SD
Measures of Dispersion and Variability: Range, QD, AD and SD
 
Separation of Lanthanides/ Lanthanides and Actinides
Separation of Lanthanides/ Lanthanides and ActinidesSeparation of Lanthanides/ Lanthanides and Actinides
Separation of Lanthanides/ Lanthanides and Actinides
 
Sanyam Choudhary Chemistry practical.pdf
Sanyam Choudhary Chemistry practical.pdfSanyam Choudhary Chemistry practical.pdf
Sanyam Choudhary Chemistry practical.pdf
 
Mastering the Unannounced Regulatory Inspection
Mastering the Unannounced Regulatory InspectionMastering the Unannounced Regulatory Inspection
Mastering the Unannounced Regulatory Inspection
 
Q4-W6-Restating Informational Text Grade 3
Q4-W6-Restating Informational Text Grade 3Q4-W6-Restating Informational Text Grade 3
Q4-W6-Restating Informational Text Grade 3
 
Software Engineering Methodologies (overview)
Software Engineering Methodologies (overview)Software Engineering Methodologies (overview)
Software Engineering Methodologies (overview)
 
Russian Call Girls in Andheri Airport Mumbai WhatsApp 9167673311 💞 Full Nigh...
Russian Call Girls in Andheri Airport Mumbai WhatsApp  9167673311 💞 Full Nigh...Russian Call Girls in Andheri Airport Mumbai WhatsApp  9167673311 💞 Full Nigh...
Russian Call Girls in Andheri Airport Mumbai WhatsApp 9167673311 💞 Full Nigh...
 
BASLIQ CURRENT LOOKBOOK LOOKBOOK(1) (1).pdf
BASLIQ CURRENT LOOKBOOK  LOOKBOOK(1) (1).pdfBASLIQ CURRENT LOOKBOOK  LOOKBOOK(1) (1).pdf
BASLIQ CURRENT LOOKBOOK LOOKBOOK(1) (1).pdf
 
Student login on Anyboli platform.helpin
Student login on Anyboli platform.helpinStudent login on Anyboli platform.helpin
Student login on Anyboli platform.helpin
 
The Most Excellent Way | 1 Corinthians 13
The Most Excellent Way | 1 Corinthians 13The Most Excellent Way | 1 Corinthians 13
The Most Excellent Way | 1 Corinthians 13
 
CARE OF CHILD IN INCUBATOR..........pptx
CARE OF CHILD IN INCUBATOR..........pptxCARE OF CHILD IN INCUBATOR..........pptx
CARE OF CHILD IN INCUBATOR..........pptx
 

Digital Logic Gates and Combinational Circuits Explained

  • 1. GHT 205 Department of Geology, University of Dhaka SMK Digital Circuit Data and control instructions move inside a computer by means of pulses of electricity. Certain components of computers combine these pulses following a set of rules. These components are logic elements.
  • 2. GHT 205 Department of Geology, University of Dhaka SMK Logic Gates • All digital computers for the past 50 years have been constructed using the same type of components. • These components are called logic gates. • Logic gates have been implemented in many different ways. • Currently, logic gates are most commonly implemented using electronic VLSI transistor logic.
  • 3. GHT 205 Department of Geology, University of Dhaka SMK Logic Gates • All basic logic gates have the ability to accept either one or two input signals (depending upon the type of gate) and generate one output signal.
  • 4. GHT 205 Department of Geology, University of Dhaka SMK Logic Gates • Input and Output signals are binary. • binary: – always in one of two possible states; – typically treated as: » On / Off (electrically) » 1 / 0 » True / False • There is a delay between when a change happens at a logic gates inputs and when the output changes, called gate switching time. • The True or False view is most useful for thinking about the meaning of the basic logic gates.
  • 5. GHT 205 Department of Geology, University of Dhaka SMK Logic Gates • The Three basic logic gates are: – AND – OR – NOT • Each of these gates may be drawn in either – A generic form; or – An electrical engineering form (more common in text books)
  • 6. GHT 205 Department of Geology, University of Dhaka SMK Logic Gates : AND The Output signal from an AND gate is True (on, 1) if and only if both Input signals are True (on, 1). The Output signal from an AND gate is False (off, 0), otherwise.
  • 7. GHT 205 Department of Geology, University of Dhaka SMK AND gate •The diagram of the AND gate looks like a capital letter D with two "prongs" on the left (the inputs) and one "prong" on the right (the output). •if either of the inputs is 0, then the output of the AND gate is 0. Thus, in order to get an AND gate to output 1, both inputs to it must be 1 Symbol Boolean Algebra BA Logic table/Truth table
  • 8. GHT 205 Department of Geology, University of Dhaka SMK AND Gate: Behaviour using a Truth Table analysis and an animation. Truth Table: The table shows that the AND gate responds with a high at the output if the signal applied to the input A and B are both high. 5v 5v 5v Input A Output X Input B AND Animation: In order to see how it works, the gate has been connected to 2 switches and LED. Continue to see the syste i actio … Logic 0 Logic 0 Logic 0 Logic 0 Logic 0 Logic 1 Logic 1 Logic 0 Logic 0 Logic 1 Logic 1 Logic 1 A B X 0 0 0 0 1 0 1 0 0 1 1 1
  • 9. GHT 205 Department of Geology, University of Dhaka SMK Logic Gate - OR The Output signal from an OR gate is True (on, 1) if either, or both, Input signals are True (on, 1). The Output signal from an OR gate is False (off, 0) if and only if both Input signals are False (off, 0).
  • 10. GHT 205 Department of Geology, University of Dhaka SMK OR gate •if either of the inputs is 1, then the output of the OR gate is 1. Thus, in order to get an OR gate to output 0, both inputs to it must be 0 Symbol Boolean Algebra BA Logic table
  • 11. GHT 205 Department of Geology, University of Dhaka SMK OR Gate Behaviour using a Truth Table analysis and an animation. Truth Table: The table shows that the OR gate responds with a high at the output if the signal applied to the input A or B is high. Input A Output X Input B OR 5v 5v 5v Animation: In order to see how it works, the gate has been connected to 2 switches and LED. Continue to see the syste i actio … Slide #11 Logic 0 Logic 0 Logic 0 Logic 0 Logic 1 Logic 1 Logic 1 Logic 1 Logic 0 Logic 1 Logic 1 Logic 1 A B X 0 0 0 0 1 1 1 0 1 1 1 1
  • 12. GHT 205 Department of Geology, University of Dhaka SMK Logic Gates - NOT • The Output signal from a NOT gate is True (on, 1) if and only if the Input signal is False. • The Output signal from a NOT gate is False (off, 0) if and only if the Input signal is True.
  • 13. GHT 205 Department of Geology, University of Dhaka SMK NOT gate •The operation of reversing the input state Symbol Boolean Algebra A Logic table
  • 14. GHT 205 Department of Geology, University of Dhaka SMK 5v NOT Gate (inverter) Input A Output X A X 0 1 1 0 Truth Table: Is a chart that lists the input condition on the left and the gate’s output response on the right. The table shows that the NOT gate responds at the output with the inverse of the signal applied to the input. Animation: In order to see how it works, the gate has been connected to a switch and LED. Continue to see the syste i actio … Slide #14 Logic 1 OFF Logic 0 ON Logic 1 OFF Logic 0 ON Logic 1 OFF Logic 0 ON
  • 15. GHT 205 Department of Geology, University of Dhaka SMK Esho Nije Kori … a) Draw a circuit : input XY , output X’Y b) Draw a circuit : input XY , output XY’ a) Draw a circuit : input XY , output X’+Y b) Draw a circuit : input XY , output X+Y’
  • 16. GHT 205 Department of Geology, University of Dhaka SMK Secondary-NAND gate •The output of the NAND gate is the negation, or reverse of the output of an AND gate with the same inputs (0 negated equals 1, and 1 negated equals 0). Symbol Boolean Algebra BA Logic table
  • 17. GHT 205 Department of Geology, University of Dhaka SMK Secondary - NOR gate •NOR stands for "Negated OR". Thus, the output of the NOR gate is the negation, or reverse of the output of an OR gate with the same inputs. Symbol Boolean Algebra BA Logic table
  • 18. GHT 205 Department of Geology, University of Dhaka SMK Secondary – XOR/EXOR gate •EOR stands for "Exclusive OR". The thing to remember about EOR gates is this: An EOR gate will output 1 only if one of the inputs is 1 and the other input 0. If both inputs are the same (1 and 1, or 0 and 0), then EOR outputs 0 Symbol Boolean Algebra BA Logic table
  • 19. GHT 205 Department of Geology, University of Dhaka SMK Boolean Theorem Boolean theorems are used to simplify or manipulate logic functions. OR A+0=A A+1=1 A+A=A A+A’= AND A.0=0 A.1=A A.A=A A.A’= NOT A+A’= A.A’= A’’=A DeMorgan’s Theorem A+B=A. B A.B= A+ B
  • 20. GHT 205 Department of Geology, University of Dhaka SMK Proof A+B=A. B
  • 21. GHT 205 Department of Geology, University of Dhaka SMK Proof A+B=A. B
  • 22. GHT 205 Department of Geology, University of Dhaka SMK Exercise =
  • 23. GHT 205 Department of Geology, University of Dhaka SMK Universality of NAND Gate Any Boolean function can be implemented using AND, OR and NOT gates. So if AND, OR and NOT gates can be implemented using NAND gates only, then the universality of NAND gate will be proved…..
  • 24. GHT 205 Department of Geology, University of Dhaka SMK Universality of NOR Gate
  • 25. GHT 205 Department of Geology, University of Dhaka SMK Combinational Logic Using Universal Gates X = (AB) (CD) X = (AB) + (CD) X = (AB) + (CD)
  • 26. GHT 205 Department of Geology, University of Dhaka SMK
  • 27. GHT 205 Department of Geology, University of Dhaka SMK Adders: Logical gates to add two numbers • We need to use a circuit with more than one output, which clearly more powerful than a Boolean expression.
  • 28. GHT 205 Department of Geology, University of Dhaka SMK How to add binary numbers • Consider adding two 1-bit binary numbers x and y  0+0 = 0  0+1 = 1  1+0 = 1  1+1 = 10 • Carry is x AND y • Sum is x XOR y • The circuit to compute this is called a half-adder x y Carry Sum 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0
  • 29. GHT 205 Department of Geology, University of Dhaka SMK x y s c 1 1 0 1 1 0 1 0 0 1 1 0 0 0 0 0 = s (sum) c (carry)
  • 30. GHT 205 Department of Geology, University of Dhaka SMK x 1 1 1 1 0 0 0 0 y 1 1 0 0 1 1 0 0 c 1 0 1 0 1 0 1 0 s (sum) 1 0 0 1 0 1 1 0 c (carry) 1 1 1 0 1 0 0 0 HAX Y S C HAX Y S C x y c c s HAX Y S C HAX Y S C x y c A full adder is a circuit that accepts as input thee bits x, y, and c, and produces as output the binary sum cs
  • 31. GHT 205 Department of Geology, University of Dhaka SMK • The full circuitry of the full adder x y s c c
  • 32. GHT 205 Department of Geology, University of Dhaka SMK • We can use a half-adder and full adders to compute the sum of two Boolean numbers 1 1 0 0 + 1 1 1 0 010? 001 Adding bigger binary numbers
  • 33. GHT 205 Department of Geology, University of Dhaka SMK Adding bigger binary numbers • Just chain one half adder and full adders together, e.g., to add x=x3x2x1x0 and y=y3y2y1y0 we need: HAX Y S C FAC Y X S C FAC Y X S C FAC Y X S C x1 y1 x2 y2 x3 y3 x0 y0 s0 s1 s2 s3 c
  • 34. GHT 205 Department of Geology, University of Dhaka SMK Adding bigger binary numbers • A half adder has 4 logic gates • A full adder has two half adders plus a OR gate – Total of 9 logic gates • To add n bit binary numbers, you need 1 HA and n-1 FAs • To add 32 bit binary numbers, you need 1 HA and 31 FAs – Total of 4+9*31 = 283 logic gates • To add 64 bit binary numbers, you need 1 HA and 63 FAs – Total of 4+9*63 = 571 logic gates
  • 35. GHT 205 Department of Geology, University of Dhaka SMK More about logic gates • To implement a logic gate in hardware, you use a transistor • Transistors are all enclosed in an IC , or integrated circuit • The current Intel Pentium IV processors have 55 million transistors!