Bhasker has over 5 years of experience in PCB layout design and engineering. He has designed boards with high speed signals like DDR3, PCIe, and USB. Some of his project experience includes designing a 26 layer board with a 1mm BGA and high speed interfaces, and boards using Intel and ARM processors. He is proficient in Cadence Allegro and has experience across the entire design flow from schematics to fabrication files.
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case StudyAltera Corporation
This presentation compares the impact of traditional FPGA engineering design flow to one employed with an SoC FPGA. The two approaches will be contrasted in terms of their impacts on system architecture design, debugging, risk mitigation, system integration, bring-up, feature enhancements, design obsolescence, and engineering effort. A case study is presented that explores these impacts within a video pipeline development effort.
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case StudyAltera Corporation
This presentation compares the impact of traditional FPGA engineering design flow to one employed with an SoC FPGA. The two approaches will be contrasted in terms of their impacts on system architecture design, debugging, risk mitigation, system integration, bring-up, feature enhancements, design obsolescence, and engineering effort. A case study is presented that explores these impacts within a video pipeline development effort.
In this presentation we described implementation of Digital Signal processing on FPGA. If you still have any query about Digital Signal processing on FPGA then feel free to contact us at:
http://www.siliconmentor.com/
A review of the history of digital design throughout the years until the era of programmable logic, and a detailed exploration of the architecture of FPGA chips, followed by an introduction to SoC FPGAs and some of their benefits.
In this presentation we described implementation of Digital Signal processing on FPGA. If you still have any query about Digital Signal processing on FPGA then feel free to contact us at:
http://www.siliconmentor.com/
A review of the history of digital design throughout the years until the era of programmable logic, and a detailed exploration of the architecture of FPGA chips, followed by an introduction to SoC FPGAs and some of their benefits.
The TMS320C6472 DSP is a six-core, fixed-point DSP from Texas instrument and two of these are integrated onto the Sundance EVP6472. Each DSP Core is a 700MHz DSP and can used for a many applications, requiring Embedded DSP Processing
1. BE in Electrical&Electronics with 5 Years 8Months Experience in PCB
Layout Design Engineer
Name: Bhasker
Mobile:+918904495584
Executive summary
∅ 5 years 8 months PCB Layout design
∅ Good design experience in High Speed Board PCB design and mixed signal PCB Design.
∅ Experience in schematic entry (Or Cad CIS,Concept HDL), PCB layout (Cadence Allegro).
∅ Good design experience in circuit boards containing FBGA’s (0.8mm, 1mm pitch BGA, DDr3),
DIMM, PCI, SATA and many more different types of components.
∅ Worked with digital, analog and mixed signal design concepts.
∅ Complete CAD design flow from Schematics, Library creation, Layout design and routing, CAM
generation.
Technical Skill
Schematic Design Tool Or CAD Capture 10.0,16.3,16.5,16.6,Concept HDL
PCB Design Tools Cadence Allegro PCB Designer 15.7,16.3,16.5,16.6
Library Tool LP Wizard
PCB Verification Tool CAM350, Gc Preview
Education details:
• Bachelor of Science Engineering Technology; 2007
Jntu - Hyderabad
• Diploma in Electrical @ Electronics Engineering; 2004
State Board of Technical Education – Hyderabad
• Secondary school Certificate; 2000
Harika public school - Bibinagar
Feb 2008 to Oct 2010:
COMPANY : APOLLO MICROSYSTEMS PVT.LTD
Hyderabad-500007
DESIGNATION : DESIGN ENGINEER
Role: Schematic design,Preparation BOM
Nov 2010 to Till Date:
COMPANY : SIART DESIGN SYSTEMS
Kasthurinagar, Bangalore-560043
DESIGNATION : PCB DESIGN ENGINEER
Role: Schematic design,foot print creation,layout design,Gerber creation and verification
2. Key Responsibilities:
- Responsible for planning and execution of Hardware PCB design according to the
specification (Mechanical inputs, Design inputs & Design constraints).
- Regularly coordinating with Design Engineers, gather requirements for the execution of
the PCB Layout.
- Designing from single layer to multi-layer PCB with SMD and through hole components.
- Having sound knowledge of schematic design and Net List extraction.
- Worked with high current boards up to 10Amp.
- Knowledge in EMI/EMC at PCB layout level.
- Adept at various technicalities viz. library creation as per IPC7351B, placement,
Constraint settings, routing, Length matching, Gerber generation.
o Major and Discrete components Placement.
o Probe point and ICT Test Point placement.
o Analysis of data sheets of component for specific requirements in product
development.
- Holds the credential of verifying the pre route and post route process to meet the signal
integrity requirement. Routing - Clock Signals, Critical signals, Bus & Single Ended
Traces.
- Delivering Fabrication and Assembly Packages to meet different manufacturing methods.
- Conducting Design Rule Checks and framing testability and manufacturability guidelines
- Development of the component library for layout & Schematic.
Highlights:
- Have designed multi-layer boards – Up to 26 Layers.
- High-speed design – Up to 10 GHz.
- Have Designed with Intel Rangeley chip,
- Have Designed with Bliend/Burried vias
- Designed 30Amps high current power supply board.
- Have designed complex PCB’s with the following high speed signals: DDR3, DDR2,
DIMM,SATA, XAUI, PCI Express, HDMI, USB differential pairs & PCI.
- Hands on experience with DDR star topology and Daisy chain Routing
- Handling the projects up to the fabrication files output.
Key Projects involved
Hendricks Cb
Software – Allegro 16.6
This is a 26 layer PCB (Size: 276mm x 180mm)
Components:2880,nets: 2200, Connections :10100
Designed with 1mm 2396 pins bga. This design contains high
speed interfaces like
- USB, Ethernet, PCI Express, Impact connector.
Role:Worked under the team leader
3. COEUS-CEMEZZ
Software – Allegro 16.6
This is a 16 layer Pcb (Size: 165mm x 144mm)
Components:1100,nets:960,connections:3800
This board uses Intel Rangeley processor, which has 0.7mm BGA
pitch, So-dimm 0.6mm pitch 244pin.the overall board thickness
80mils,
Role:Worked under the team leader
Altius-Mezz
Software – Allegro 16.6
This is a 18 Layer PCB (Size:161x114mm)
Components:1900,nets:1160,Connections:5500
This Board Uses 1mm 689 pins Bga and high Speed interfaces are
Ddr3 32 bit, It3 Connector.
Role:Worked under the team leader
ON BOARD PROCESSOR UNIT
Software – Allegro16.5
This is a 8 Layer PCB (Size:120x100mm)
Components:600,nets:450,connections:1500
This board uses ARM NS9360 Processor. This application mainly
used in GSM, GPS and vehicle tracking system (VTU). And this is
also used in GSM and GPS application .In this system we used one
Ethernet module, USB module also.
MXM(Marvell)
Software – Allegro16.5
This is a 8 Layer PCB (Size:140x120mm)
Components:800,nets:650,connections:2000
This system is a tiny and powerful Ethernet enable small module in
world on the new Marvell Scale PXA320 processor and runs at
806MHz.the computer optimized using the new wireless Intel Speed
step Technology.
It Includes 128MB of NAND Flash, and 64MB/128MB Mobile DDR
memory, two USB host interface, Ethernet interface, three RS232
interface, CF(compact flash)interface, IDE,PWM and SPI through a
242-pin MXM golden finger connector as interface.
Data Acquisition Processor
Software – Allegro16.3
This is a 6 Layer PCB (Size:120x120mm)
Components:600,nets:450,connections:1500
This system is Data Acquisition Processor has designed to monitor
the vehicle parameters such as Pressure and Temperature of tire,
Engine run status, fuel level and provides information to the driver in
the vehicle and also to the base station. Using Thread dx Real Time
Operation System (RTOS). It monitors the Digital Input connected to
the GPIO of the processor.
DTR (DIGITAL TAPE
RECORDER).
Software – Allegro16.3
This is a 4 Layer PCB (Size:100x100mm)
Components:500,nets:300,connections:1200
This System is Digital Tape Recorder it is used in Railway Engines.
This PCB placed in unit. Top of the cover is having Push buttons
(Switches) and station names. And D-SUB connector is used to give
the output power and Gnd connections.
PERSONNEL INFORMATION:
Father’s name:balraju
Date of Birth:25Jun1984
Languages known:Telugu,Hindi,English.