This document contains a resume for Prashantha summarizing his skills and experience as a printed circuit board designer. It outlines his objective of becoming a top PCB designer, over 5 years of experience designing boards with up to 20 layers and fine pitch components, expertise with Cadence Allegro and responsibility for independently designing over 30 boards. Recent projects include boards for radar signal processing and pulse digitization systems using processors like i.MX6 and layouts with DDR3, Ethernet, USB and differential signaling routes.

1. Prashantha
Phone.N0: 9535621424
Mail ID: Pacchu36@gmail.com
Job Objective:
 To become a top Professional Printed Circuit Designer in the fast growing EDA field.
 Focus on Total Customer Satisfaction.
Current Position: Senior Engineer, iWave Systems Technologies Pt. Ltd
Experience: July’2011- Till Date
Roles &Responsibilities:
 Layout footprint creation & Verification
 CamData (gerber)Generation
 Schematic Modification
 Independent multilayer PCBlayout design
 Provide guidanceby sharing the knowledgeto the team
 Layout/Gerber Reviews
 Upgrading knowledge as per the requirement
Summary of Skills & Experience
 Worked on designs with no. of layers varying from 2 to 20 Designs with Fine pitch
 Total 5+ years of Experience on Turnkey PCB Layout / Placement/ Routing of 1mm,
0.8mm, 0.65mm
 Till now designed around 30+ PCB layouts independently.
 Capability to Analyze the Mechanical Dimensions from Datasheets/assembly Case
While Designing the Symbol/board
 Hands of work experience on high speed layout designs like DDR3 ,Gigabit
Ethernet, USB3.0, SATA, ADC
 Experience in maintaining of signal integrity, power, and EMI/EMC compliance
 Active participation in layout review activity

2. Prashantha
 Involving in design & analysis of complex challenging layout designs
 Active participation in Cadence Community forum discussions.
Present JobDescription
 Presentlyworking as a Layout Designer (Senior Engineer) iniWave Systems
Technologies Pvt Ltd, Bangalore from July 2011 - Till Date
 Doing more Study on EMI/EMC/DFA/DFM embedded component design.
Major Layout Contributions
Till now completed around 10+ independent multilayer layout designs & 20+partialLayout
activity. Few Major layout Contributions are listed below.
1. Project : Radar Signal Processing System
Roles& Responsibilities:
 High speed optical signals(10Gbps)
 High speed optical signals(6Gbps)
 DDR3 Interface routing & delay tuning
 Analysis and implementation of SI/Thermal reports
 Routing and delay tuning Signals of single ended interfaces(Gb
Ethernet, NAND flash, CPLD,JTAG,VPX,FMC,RS232, CLOCK Signals)
 Routing and delay tuning Signals of Differential ended
interfaces(RS422,RS485,CLOCK Signals)
 Footprint Creation & verification
 Layout Review
2. Project : Pulse Digitizer
Roles & Responsibilities:
 ADC 100E Lvds signalsRouting
 DDR3 Interface routing&delaytuning
 Differential AmplifierRouting

3. Prashantha
 Clock SynthesizerRouting
 Optical Transceiver SignalsRouting
 EthernetSignalsRouting
 RoutinganddelaytuningSignalsof Differential andsingle endedinterfaces
 FootprintCreation&verification
 LayoutReview
3. Project : Free scale i.Mx6 Sololite processor based layout design
Roles& Responsibilities:
 EPDC (9 inch and 13.3 inch) Interface routing & delay tuning
 LPDDR2 Interface routing & delay tuning
 Layout Review
 DFM Review & Gerber generation
4. Project : Unified learning Kit Layout Design based on TI’OMAP3530 processor
Roles& Responsibilities:
 Test-Jig Board Layout design
 Layout design for add on modules: Bluetooth module ,Accelerometer
module, Camera Interface Module
 DFM Review & Gerber generation
5. Project : Free scale i.Mx6X processor based Q7 Module
Roles& Responsibilities:
 DDR3 Interface routing & delay tuning
 Routing of high speed interfaces like SATA ,PCie & LVDS
 Layout Review
 DFM Review & Gerber generation

4. Prashantha
6. Project : Free scale i.Mx53 based board layout design
Roles& Responsibilities:
 DDR2 Interface routing & delay tuning
 Footprint Creation & verification
 Layout Review
7. Project : Free scale i.MX SoloLite based board layout design
Roles& Responsibilities:
 EPDC Interface Interface routing & delay tuning
 1-Gbyte LPDDR2 memory Interface routing & delay tuning
 Layout Review
8. Project : Train Controller and Monitoring System (i.Mx6 Processor)
Roles & Responsibilities:
 PCIe - 100E Differential signalsRouting
 DDR3 memory Interface routing & delay tuning
 Gbit Ethernet – 100E Differential signals Routing
 USB- 90E Differential Nets Routing
 Routing and delay tuning Signals of Differential ended interfaces
 Footprint Creation & verification
 Layout Review

5. Prashantha
* Got “Pat On The Back Award“from present company for Vybrid
Carrier Boardcomplete layout design.
Knowledge on Tools & Applications
 Layout Tool (Expert) : Cadence Allegro SPB 16.3,16.6
 Schematic Tools (Expert ): Cadence Orcad design entry CIS 16.3
 Gerber & DFM analysis tool(Known): GC preview , ODB++,CAM350
 Layout Tools understudy(Studying): Altium
 Documentation tool: MS office Word, Excel & Power point
 Operating Systems : Windows XP/ Windows 7/ Windows 10
Educational Qualifications
 Bachelor of engineering in electronics and communication (Presently in 5th semester)
from B.M.S Evening College of Engineering (2015 to 2018)
 Diploma in Electronics & Communications from NRAM Polytechnic, Nitte
Karkala, 2011
Personal Profile
Date of Birth: 05th July 1990
Marital Status: Single
Mother Tongue: Tulu & Kannada
Languages Known: English, Hindi, Kannada, and Tulu
Strength: Self motivated, Team work, Quick learner
Hobby: Reading books, Music, Cricket