R. Saravanakumar is seeking a challenging position to enhance his technical skills. He has over 5 years of experience in FPGA design and verification using Verilog, VHDL and tools like ModelSim and Xilinx ISE. Some of his projects include designing an AHB compatible DDR SDRAM controller IP core, an ATLAS processor core, and implementing Ethernet and SRAM standards on Xilinx FPGAs. He holds a BE in ECE and has experience working with organizations like Wiztech Automation Solutions and Crisp System India.