Swapnil Deshmukh has an M-Tech in VLSI Design with 6 months of experience in validation testing of PCIe devices using various tools. He has experience designing and verifying architectures in Verilog and writing testbenches, monitors, and checkers. He is proficient in Verilog, Perl, Python, and various EDA tools like Cadence and Altera tools.

1. SWAPNIL DESHMUKH
96,Gopalkrishna Nagar, Wathoda Layout,Nandanvan,Nagpur-440009, India
 (India): +91-9595500275, +91-8682085108,  swapnil.dsh10@gmail.com
SUMMARY
M-tech VLSI Design with 6+ months professional experience as intern in validation domain (PCIe, Perl & Python Automation). Have an
experience of writing many basic & complex Verilog program for design, implementation & verification of Architectures as a part of academics.
SKILLS SUMMARY
• Experience of PCI express link testing with analyzer Exerciser for RC & EP Inbound Outbound read write.
• Detail understanding of PCI express IP Link Training state machine (LTSSM).
• Experience of conducting various link testing experiments like Eye plotting, BERT’s tool.
• Experience of writing Perl & Python script for automation purpose.
• Experience of writing many basic & complex Verilog program for design of architectures & implementation of it with FPGA.
• Experience of writing complete verification plan including Test cases, BFM, Monitor & Checker with the help of Verilog.
• Hands on experience of using various VLSI design lab tools (cadence- Virtuoso, Layout Editor, SoC Encounter, RTL compiler, NC-sim, Ng-
spice, Matlab, Modelsim, Quartus )
• Excellent project management skills, which include scheduling deliverables, clear communication with project partners, and consistently
delivering high-quality content on or ahead of schedule.
• Excellent presentation skills & Strong technical command of the English language.
TECHNICAL SKILLS
Category Tools
Validation tool PCIe Analyzer –Exerciser, BERT’s, Margin tool, Oscilloscope.
Design & layout tool Cadence- Virtuoso, Layout Editor, SoC Encounter, RTL compiler.
Compilation tool Altera – Modelsim, NC-sim, Matlab, Quratus, Win-AVR
Spice tool Ng-spice.
Programming language Verilog HDL, Perl, Embedded - C, Tcl, Python.
Operating Systems Windows, Linux
Others Microsoft office
PROFESSIONAL EXPERIENCE
Applied Micro Circuit Corporation (AMCC), India Pune, India
Research Intern Validation [PCI express] Dec 2014 - Present
• Testing PCI Express with analyzer Exerciser for RC & EP Inbound Outbound read write.
• Plotting Eye for each channel and analyzing the link.
• Using BERT test for link testing.
• Detail understanding of Link Training state machine (LTSSM).
• Perl Automation Script.
ACCADEMIC PROJECT EXPERIENCE
VIT University, Vellore Vellore, TN, India
Design of Configurable MBIST Techniques July 2014 – Oct 2014
Tools Used: ModelSim, Quartus II, RTL Compiler (Cadence),GDSII and SoC encounter.
Project Brief: In this project a configurable memory BIST [Built–in-Self-Test] architecture is designed, which can test different memories of
different size & configuration. It uses the MARCH C- and MATS+ Algorithm for detection of various faults in the memory. We consider a
memory module having (injected) stuck at faults (sa-0, sa-1) and Address decoding faults (Ad). By using both algorithms together 100% fault
coverage is achieved for static memories. The hardware logic required for MBIST Architecture is less than 8% of the total hardware required.
The work is carried out using 90nm CMOS technology. The core size of the chip (GDSII) is 1.27 square mm with gate count of 18030 and
operating frequency of 100MHz. The power dissipated is about 39mW.

2. VIT University, Vellore Vellore, TN, India
Design and Implementation of 16 bit Simple Processor on FPGA Board Jan 2014 – May 2014
Tools Used: ModelSim, Quartus II, Altera DE2 Board.
Project Brief: A 16 bit processor was developed with the help of RISC Architecture (Von Neumann) which could carry out 16 bit operations
like move, load, shift, addition, subtraction. Logical Operations like And, OR, Ex-or could be performed. The processor decodes the instruction,
process it and store the result accordingly in the register desired. The clock frequency was 16Mhz. For implementation & performance analysis
on FPGA Altera DE2 board (cyclone-II family) was used.
VIT University, Vellore Vellore, TN, India
Design of 45nm low power, High Speed Vedic Multiplier July 2013 – Dec 2013
Tools Used: ModelSim, Quartus II, RTL Compiler (Cadence).
Project Brief: With ever increasing need for faster clock frequency it becomes imperative to have faster arithmetic unit. A high speed
complex multiplier design using Vedic Mathematics formulas has been designed. Highly power efficient method of multiplication using Urdhva
Triyangam sutra -one out of sixteen vedic sutras was used. The multiplier was synthesized in 45nm technology node. A 64 bit Vedic Multiplier
was implemented which achieved a 28 % & 30% power reduction and 55% & 63% area reduction compared with the booth and conventional
multiplier respectively. Total gate count was 5717, power consumed 1.3mW working at frequency of 72MHz.
VIT University, Vellore Vellore, TN, India
Verification of Synchronous FIFO Controller Oct 2014 – Dec 2014
Tools Used: Modelsim, Cadence NC-sim
Project Brief: A FIFO DUT module was first designed according to the specifications. A verification environment consisting of monitor,
checker and BFM was developed using Verilog HDL. Multiple test cases were written to verify the different scenarios concerned the DUV.
W.C.E.M. Nagpur University, Nagpur Nagpur, MS, India
Design & Implementation of Obstacle detecting I-Bot June 2011 – Dec 2011
Tools Used: WinAVR
Project Brief: An I-Bot was developed, which could scan the complete path, detect the obstacle coming in its path & could deposit it at it
respective position. Algorithm design & programming was done on At-mega 16 Microcontroller IC. Programming language used was
Embedded-C.
ACHIEVEMENTS
• Worked as a Student General Secretary for 3 years in B.E.
EDUCATION
VIT University, Vellore, TN. Tamilnadu
M-Tech (VLSI Design ) 2013-2015
Marks Percentile: 6.48
Wainganga College Of Engg & Technology, Nagpur University, Nagpur, MS Maharashtra
BE (Electronics) 2008-2012
Marks Percentage: 59.14 %
ADDITIONAL INFORMATION
Interests: Reading (biography, novels), Travelling, Gardening, Tracking, playing Cricket.
Languages known: English, Marathi, Hindi, Telagu.
References: Available on request
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