1. GAUTHAM KALVA
5752 W Del Rio St. Chandler AZ 85226
Ph: 503.830.0044. E-mail:g_kalva@yahoo.com
Education
• MSECE, Portland State University, OR. (June 2006)
• BSEE, Madras University, India. (June 2004)
Computer Skills
• Hardware Description Languages: System Verilog, Verilog HDL, VHDL
• Verification methodologies: UVM, OVM
• Scripting: Perl, GNU Make, Tcl
• Programming Languages: C, C++, x86 assembly language
• EDA Tools: Mentor VStationPRO, ModelSim, LeonardoSpectrum, Novas
Verdi, Debussy, nLint, Cadence NC-Verilog, Palladium II,
Virtuoso, Synopsys Design Compiler and Specman.
• Operating Systems: UNIX, LINUX, Windows 2000/NT/XP, Sun Solaris
8/9
Work Experience
Engineer, Sr Staff: Broadcom Ltd, Chandler, AZ (Aug’10-present):
• Lead USB 3.0 Link/PHY Layer verification. Responsible for developing bench with
integration of PHY with Host/Device controller. Development of test cases (directed and
pseudo random) to cover all the arcs of LTSSM and multiple functions of PHY, covering
all device state transitions. Verification of multi-protocol Phys with PIPE 3/4 interface
covering PHY DFE logic for both Host and Device modes. Exhaustive coverage of Link
level low power & error injection scenarios. Verification Plan and Coverage Plan
development and coverage closure. Gate Level Simulations with zero-delay and with
SDF timing annotation. Integration of UVM based VIPs such as Cadence
Puresuite/Purespec environment.
• Verification of Combophy (Multi-Protocol) Verification (In-Progress). Developed a
standalone UVM based verification environment to support multi-protocol PHY that
supports PCIe (Gen1, 2, 3), USB (Gen1 &2), SATA (Gen1,2 & 3) with focus on USB.
Verified multiple PHY functions of USB Gen2. Preliminary setup made to integrate with
respective controllers.
• RDB (similar to IP-XACT) based register access to verify read/write and default values.
Covered features like test port, lane polarity, internal and external Bert loopback modes.
• Taped out multiple chips and worked closely with post silicon validation. Customer
support & work closely with Cadence VIP team.
• xHC3.0 certified by USB IF.
ASIC Design Verification Engineer: Nethra Imaging, Santa Clara, CA (Nov’08-Aug’10):
• Part of a team which developed full chip TB for I/O Bridge (IOB) SOC in System Verilog
using Open Verification Methodology (OVM) class library concepts like TLM, factory,
transaction components, sequencers and GNU Make utility.
Developed test cases for SATA, AHB, DDR3 SDRAM memory controller, Monitor and
RGB pipelines, GigE and JTAG blocks of the chip.
• Responsible for verifying Layer 3 module of 10 Gigabit eXtended Attachment Unit
Interface (XAUI) protocol at block level and sub module level (L3 MAC, L2, PCS and
PHY).
Created processes and put in place a test methodology which was used in the
development of the TB infrastructure.
The TB was architected and developed in System Verilog.

2. Work included writing synthesizable BFMs, implementing protocol checkers/monitors,
threads, inter process communication (IPC), scoreboard, coverage generation, assertions
(SVA), error injection/handling, constrained random stimulus generation, test plan
development and writing testcases.
• Module level verification for GigE glue logic, crop and borderpad blocks of monitor
pipeline module in a perl based environment.
• Responsible for the development of gate level simulation environment at chip-level for
zero delay, SDF annotation, debug timing violations and generate EVCD for ATE/power
analysis.
• Developed DDR3 memory controller model in system verilog along with wrapper to
support two agents using round robin arbitration scheme.
• Emulation (FPGA board and Cadence Palladium) and post silicon ASIC bring up and
validation support.
ASIC Design Verification Engineer: Server Engines Corporation, Sunnyvale, CA (Oct’06 –
Nov’08):
• Develop testbench/testcases in Verilog for verification of the following modules in a
server chipset:
Memory-
 1KB memory manager for a 128 KB frame buffer memory.
 64K 4-way set associative Unified Cache.
Storage-
Link, Transport layers of physical interface for:
 Serial Attached SCSI (SAS)
 Serial Advanced Technology Attachment 2(SATA2)
 Advanced Technology Attachment Packet Interface (ATAPI)
Endpoint Host Interface (PCIe 2.0 compliant)-
 Test features like Power management, Message Signaled Interrupt (MSI/MSI-X),
SRIOV Capability, Error Injection, Speed Change (GEN1/GEN2) and
Width Dynamic change (X1/X2/X4/X8) for endpoint Host interface and validate
PIPE (PHY Interface for the PCI Express Architecture) operational behavior.
• Top/Chip level validation environment using verilog, test cases in C using PLI,
Perl/Gmake scripts for automation, using Cadence NC-Verilog.
• Responsible for running lint at various units by enabling/disabling rules and analyze
reports using Design Rule Checker (DRC)-RTL Novas-nLint.
• Generate code coverage using Cadence NC-Verilog.
• Design an AHB bus slave model in Verilog to generate traffic for reads and writes and
related test bench.
• Debug issues on AXI/AHB, memory controller for DDR2 SDRAM, DMA, ARM11 cores
and Host (PCIe 1.1 compliant) interfaces.
• Source gen related documentation for the data structures and register interface of the
chipset.
Graduate Technical Intern: Intel Corporation-Hillsboro, OR (Oct’05-Sep’06):
• Build and verify emulation models in Verilog for chipsets.
• Design and simulate digital functional modules using Modelsim (Mentor Graphics),
Novas Verdi and work with hardware equipment like VStationPRO, Palladium II
Emulators, logic analyzers, oscilloscopes and validation test cards.
• Successfully completed verification of 25+ register files and cam models
involving 500+ vcd files using Perl and shell script automation.
• Synthesis and Place-and-Route for chipset on Mentor VStationPRO and Cadence
Palladium II emulators.
• Capture traces on FSB and debug issues on PCIE interface.