Hardware description languages (HDLs) like VHDL and Verilog allow designers to model digital circuits and systems. HDLs enable increased productivity through design reuse, faster design changes, and exploration of alternative architectures. VHDL is a popular, industry standard HDL that supports modeling designs hierarchically at different levels of abstraction from behavioral to structural. VHDL models can be simulated and synthesized, facilitating early verification of a design's functionality before implementation.

1. INTRODUCTIO
N
TO
VL & H S
SI DL
Sreejeesh S.G

2. Course Contents

3. Course Contents
 What are HDLs ?
 Are they really required ?.
 VHDL
 Verilog
 Advantages/Disadvantages

4. VLSI Realization Process
4
Customer’s need
Determine requirements Design
Write specifications
Design synthesis and Verification
Test development
Fabrication
Manufacturing test
Manufacture
Chips to customer
SSG, VLSI DESIGN GROUP ,NIELIT

5. Hardware Description Language
HDL is any language from a class of computer
languages and/or programming languages for
formal description of electronic circuits. It can
describe the circuit's operation, its design and
organization, and tests to verify its operation
by means of simulation.
HDLs are used to write executable specifications
of some piece of hardware.
Sreejeesh VLSI DESIGN GROUP. NIELIT

6. HDLs - Motivation
 Increased productivity
 shorter development cycles, more features,
but........still shorter time-to-market, 10-20K
gates/day/engineer
 Flexible modeling capabilities.
 can represent designs of gates or systems
description can be very abstract or very
structural
Sreejeesh VLSI DESIGN GROUP. NIELIT

7.  Design reuse is enabled.
 packages, libraries, support reusable, portable
code
 Design changes are fast and easily done
 convert a 8-bit register to 64-bits........four key
strokes, and its done!
 exploration of alternative architectures can be
done quickly
Sreejeesh VLSI DESIGN GROUP. NIELIT

8.  Use of various design methodologies.
 top-down, bottom-up, complexity hiding
(abstraction)
 Technology and vendor independence.
 same code can be targeted to CMOS, ECL,
GaAs
 same code for: TI, NEC, LSI, TMSC
 same code for: .5um, .35um, .25um, .18um
Sreejeesh VLSI DESIGN GROUP. NIELIT

9.  Enables use of logic synthesis which allows a
investigation of the area and timing space.
 Using a standard language promotes clear
communication of ideas and designs.
Sreejeesh VLSI DESIGN GROUP. NIELIT

10. DO WE REALLY NEED HDL’S ??
Before Emergence of HDL’s
How was Designing Field ??
We where designing systems
using Boolean equations…isn't ?

11. SCHEMATIC REPRESENTATION
Sreejeesh VLSI DESIGN GROUP. NIELIT

12. DRAWBACKS OF TRADITIONAL
DESIGNING METHODS
System will be specified as interconnected blocks and this
is not how specification of system is given to you or
created.
 System spec is always given as behavior of a system.
 Handling of large complex system is not feasible.
 Analyzing thousands of Boolean equations is not possible.
We all know that over six thousand gates the schematic
become incomprehensible.
 We in modern world deal with millions of gates.
Sreejeesh VLSI DESIGN GROUP. NIELIT

13. So We go for HDL’s …
 What are these HDL’s ??

“ H ardware D escription L anguage”.
 What they do ??
 Describe digital circuits.
 HDLs allowed the designers to model the concurrency of
processes found in hardware elements.
 HDLs such as Verilog HDL and VHDL became popular.
Sreejeesh VLSI DESIGN GROUP. NIELIT

14. COMPARISON B/W TRADITIONAL APPROACH AND HDL
APPROACH.
Sreejeesh VLSI DESIGN GROUP. NIELIT

15. Design Flow
Design Entry
Simulation
Modelsim VHDL ModelSim
Logic Synthesis Xilinx ISE
Place and Route
FPGA
Hardware
Logic Analyzer

16. Sreejeesh VLSI DESIGN GROUP. NIELIT

17. ORIGIN OF VHDL
Initiated by US Government’s Dept of Defense VHSIC
•
Program in 1980.
IBM, TI and Intermetrics started the development of VHDL in
•
1983
VHDL Ver. 7.2 released in 1985.
•
IEEE standard 1076-1987 in 1987.
•
IEEE 1076-1993 - revision in 1993
•
Sreejeesh VLSI DESIGN GROUP. NIELIT

18. V HDL
Very High Speed Integrated Circuit Hardware
Description Language
VHDL is an industry standard HDL for the Description, Modeling and
Synthesis of digital circuits and systems.
Sreejeesh VLSI DESIGN GROUP. NIELIT

19. V HDL
It is the most popular HDL , worldwide.
System specification can be done structural or/and in behavioral levels.
Good VHDL simulation tools are available in market at reasonable price.
Synthesis with VHDL is available with all most all EDA vendors .
It is a universal modeling language, i.e. it can be used to model electromechanical
systems, hydraulics, chemical and other system. It is not restricted only to
electronics.

20. BASICFEATURES OF VHDL
 CONCURRENCY.
 SUPPORTS SEQUENTIAL STATEMENTS.
 SUPPORTS FOR TEST & SIMULATION.
 STRONGLY TYPED LANGUAGE.
 SUPPORTS HIERARCHIES.
 SUPPORTS FOR VENDOR DEFINED
LIBRARIES.
 SUPPORTS MULTIVALUED LOGIC.
Sreejeesh VLSI DESIGN GROUP. NIELIT

21. CONCURRENCY
VHDL is a concurrent language.
HDL differs with Software languages with respect
to Concurrency only.
VHDL executes statements at the same time in
parallel, as in Hardware.
Sreejeesh VLSI DESIGN GROUP. NIELIT

22. Sreejeesh VLSI DESIGN GROUP. NIELIT

23. DESIGN PROCESS OF A DIGITAL SYSTEM
Design process of a digital system has 4
phases
- Requirement Analysis &
Specification.
- Design .
- Implementation & Testing.
- Manufacturing .
In 1st phase, Function, Performance and
interface requirements are determined and
specified.
Sreejeesh VLSI DESIGN GROUP. NIELIT

24. DESIGN PROCESS OF A DIGITAL SYSTEM..
In 2nd phase , system is partitioned into different levels of
decomposition such as
- System Design : System is decomposed several
subsystems and the communication protocol among them is also
defined.
- Architectural Design : Architectural style and performance of
each subsystem is determined.

25. DESIGN PROCESS OF A DIGITAL SYSTEM…
RTL Design : Architecture is translated into an interconnection of RTL Modules.
- Logic design: RTL Modules are constructed using logic
gates.
In 3rd phase, subsystems are implemented and tested including partitioning,
placement and routing to produce a layout of circuit.
In final phase , process is to prototype , manufacture the design.

27. ADVANTAGES OF VHDL
Can verify design functionality early in the design process and
simulate a design written as a VH description.
DL
Logic Synthesis and optimization converts a VH description
DL
to a gate level implementation in a given technology.
Reduces circuit design time and errors.
VHDL descriptions provide technology independent
documentation for a design and its functionality.

28. ADVANTAGES OF VHDL..
Powerful constructs to write complex logic.
It has multiples levels of design descriptions.
It supports design libraries and the creation of reusable
components.
It provides for design hierarchies to create module design.

29. ADVANTAGES OF VHDL….
Device independent design

VHDL permits to create a design without first choosing
the device for implementation
Portability

VHDL is an IEEE standard.
Libraries of VHDL models of components can be
shared across platforms, tools organization and
technical group
ASIC Migration

Quick time to market and low cost


30. CAPABILITIES
 VHDL supports design hierarchies
A digital system can be modeled as a set of
interconnected components
It supports flexible design methodologies
Top-down , Bottom-up or mixed.
VHDL is not technology specific.
It can support various hardware technologies
It supports both synchronous and asynchronous timing
models
NIELIT

31. CAPABILITIES…
Various modeling techniques such as FSM, algorithmic and Boolean
equations can be modeled using VHDL.
 Any large design can be modeled using VHDL
 No limitation imposed by the size of a design
 Test benches can be written in VHDL to test other models.
Sreejeesh VLSI DESIGN GROUP.
NIELIT

32. CAPABILITIES…
 Propagation delays, set-up and hold time timing constraints can be described
in VHDL
 Generics and attributes are useful in describing parameterized design
 Models written in VHDL can be verified by Simulation
 Behavioral models are capable of being synthesized to gate- level description
Sreejeesh VLSI DESIGN GROUP.
NIELIT

33. Sreejeesh VLSI DESIGN GROUP. NIELIT

34. DISADVANTAGES
 Less control of defining gate level implementation.
 The implementation created by synthesis tool is
inefficient.
 The quality of synthesis varies from tool to tool.

35. SUMMARY
VHDL modeling can be used to model
hardware at multiples levels of abstraction.
VHDL is independent of technology and
design methodologies and promotes portable
descriptions, rapid prototyping and free
exchange of models among organizations and
individuals.

36. ANY QUESTIONS ??
ANYBODY ??
COMMENTS ??
Thanks.
Sreejeesh S.G