Theory of Time 2024 (Universal Theory for Everything)
Report
1. List of figures
S.No. Name of the figure Page no
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2. List of contents
S.No. Name of the content Page no
1 Certificate
2 Acknowledgement
3 Abstract
4 VLSI – very large integrated circuit
History
Developments
VLSI Design overview
5 Introduction of 7-segment decoder
What is 7-segment decoder
Truth table of 7-segment decoder
6 Tool used in the project : cadence tool
7 RTL description of seven segment decoder
7-segment module in HDL
Testbench for 7- segment decoder
8 Functional verification and testing
9 Logical synthesis/ timing verification
10 Gate level netlist
11 Floor planning
12 Automated place and route design
13 Physical layeout
14 Result
15 conclusion
16 reference
3. 1. VLSI (Very large scale integration)
1.1 HISTORY
The development of microelectronics spans a time which is even lesser than the average life
expectancy of a human, and yet it has seen as many as four generations. Early 60’s saw the
low density fabrication processes classified under Small Scale Integration (SSI) in which
transistor count was limited to about 10. This rapidly gave way to Medium Scale Integration
in the late 60’s when around 100 transistors could be placed on a single chip.
It was the time when the cost of research began to decline and private firms started entering
the competition in contrast to the earlier years where the main burden was borne by the
military. Transistor-Transistor logic (TTL) offering higher integration densities outlasted
other IC families like ECL and became the basis of the first integrated circuit revolution. It
was the production of this family that gave impetus to semiconductor giants like Texas
Instruments, Fairchild and National Semiconductors. Early seventies marked the growth of
transistor count to about 1000 per chip called the Large Scale Integration.
By mid eighties, the transistor count on a single chip had already exceeded 1000 and hence
came the age of Very Large Scale Integration or VLSI. Though many improvements have
been made and the transistor count is still rising, further names of generations like ULSI are
generally avoided. It was during this time when TTL lost the battle to MOS family owing to
the same problems that had pushed vacuum tubes into negligence, power dissipation and the
limit it imposed on the number of gates that could be placed on a single die.
The second age of Integrated Circuits revolution started with the introduction of the first
microprocessor, the 4004 by Intel in 1972 and the 8080 in 1974. Today many companies like
Texas Instruments, Infineon, Alliance Semiconductors, Cadence, Synopsys, Celox Networks,
Cisco, Micron Tech, National Semiconductors, ST Microelectronics, Qualcomm, Lucent,
Mentor Graphics, Analog Devices, Intel, Philips, Motorola and many other firms have been
established and are dedicated to the various fields in "VLSI" like Programmable Logic
Devices, Hardware Descriptive Languages, Design tools, Embedded Systems etc.
4. 1.2 DEVELOPMENTS
The first semiconductor chips held two transistors each. Subsequent advances added more
transistors, and as a consequence, more individual functions or systems were integrated over
time. The first integrated circuits held only a few devices, perhaps as many as ten diodes,
transistors, resistors and capacitors, making it possible to fabricate one or more logic gates on
a single device. Now known retrospectively as small-scale integration (SSI), improvements in
technique led to devices with hundreds of logic gates, known as medium-scale integration
(MSI). Further improvements led to large-scale integration (LSI), i.e. systems with at least a
thousand logic gates. Current technology has moved far past this mark and today's
microprocessors have many millions of gates and billions of individual transistors.
At one time, there was an effort to name and calibrate various levels of large-scale integration
above VLSI. Terms like ultra-large-scale integration (ULSI) were used. But the huge number
of gates and transistors available on common devices has rendered such fine distinctions
moot. Terms suggesting greater than VLSI levels of integration are no longer in widespread
use.
As of early 2008, billion-transistor processors are commercially available. This became more
commonplace as semiconductor fabrication advanced from the then-current generation of 65
nm processes. Current designs, unlike the earliest devices, use extensive design automation
and automated logic synthesis to lay out the transistors, enabling higher levels of complexity
in the resulting logic functionality. Certain high-performance logic blocks like the SRAM
(static random-access memory) cell, are still designed by hand to ensure the highest
efficiency.
1.3 VLSI DESIGN OVERVIEW
VLSI design involves translating the given specifications into geometrical patterns that are
used in fabrication chips.
This translation task is very complex and cannot be accomplished in one step. It is
accomplished through a succession of translation steps of manageable complexity. Each
translation step translates more abstract (less detailed) design description into less abstract
(more detailed) design representation. Abstractions are the means of representing various
views of the design with varying amounts of details.
5. Different Design Representation levels are called different abstraction levels. The different
abstraction levels for representing the behavioral, structural and physical aspects of a design
are shown along the corresponding three axes in the Gajski’s Y-Chart.
The Gajski’s Y-Chart graphically represents the three domains and the popular abstraction
level used in each of the domains.
(Figure no 1) Gajski-Kuhn Y-chart
1.4 STEPS IN VLSI DESIGN FLOW
Design Specification
Specifications comes first, they describe abstractly the functionality, interface and the
architecture of the digital IC circuit to be designed.
The specification needs to be comprehended and captured through suitable level of
abstraction.
6. Architecture Design
In Architectural Design, Behavioural Description is created to analyse the design in terms of
functionality, performance, compliance to given standards and other specifications.
It also includes rough estimation of speed/throughput, area and power of each architecture
alternatives to decide on an architectural course to be taken i.e. selection of an optimal
architecture best suited for the application.
Register- Transfer Level Design
Further refinement of the design is done at Register- Transfer Level (RTL)/ data flow level
description. RTL description is done using HDLs. RTL description is simulated to test
functionality.
For a complex processing specification, rarely one can put enough on a chip that would
realize the full processing in one step. Therefore, all complex processing is invariable
realized via a sequence of simpler processing steps repeatedly using this limited processing
hardware and storing the intermediate results that are used in subsequent processing steps i.e.
all the complex processing is realized through the use of sequential hardware.
The design issue thus boils down the optimal choice of processing circuitry (one or more
processing elements) to be incorporated on the chip, the storage elements, the
intercommunication path between the storage elements (both on-chip and off chip) and the
processing elements, and the associated sequenci9ng circuitry to the sequencing of processing
steps and the actual processing done at each step.
In general, the more complex the processing on the chip, the fewer the processing steps and
storage required to achieve full processing.
Architecture Exploration and RTL Description
Architecture Exploration involves choosing the number and type of processing elements and
implementing/realizing the behaviour of the chip using these processing elements.
All the transformation/ operations on the operands contained in the behavioural description
can be implemented by routing the operands through the processing elements available in the
architecture over a series of steps of transformation/ partial transformations and storage of
intermediate results. A HDL description describing/ capturing the above is called an RTL
description.
Architecture exploration and the associated design translation from behavioural to RTL level
abstraction has traditionally been done manually.
7. High- level synthesis tool (transformation of behavioural description to RTL description
while exploring different architectures) has begun to help the designers in selected
application areas (such as application specific digital signal processing elements).
Gate Level Design
Each of the processing elements, the storage elements and the control part is translated into
detailed logic gate level description or the blocks of the logic functions.
Transistor Level Design
A logic function can be realized with the help of transistor circuits of various kinds (with
different topologies).
Stick Level Design
Transistor level diagrams are not directly translated into layouts. Stick diagram captures the
layer information and topology of the layers that are to be used in the layout.
Physical Design and Layout
Stick diagrams are converted to detailed geometric design (layout) with the appropriate
widths, length, separations, overlaps between the layers etc. in view of the design rules and
electrical considerations.
Design rules represent the constraints on geometrical patterns on different layers imposed by
the considerations of reliable manufacturability of the circuit in a given manufacturing setup
(foundry).
8. The design flow of physical layout of any digital circuit
(Figure no. 2) Design flow for physical layout
Design specification
Behavioural description
RTL description (HDL)
Functional verificationandtesting
Logical synthesis/ timing
verification
Gate level net list
Logical verification and testing
Floorplanning & automatic place
and route
Physical layout
Physical layout verification
Implementation
9. 2. Introduction of 7-segment Decoder
2.1 What is 7- segment?
We will be implementing a Binary Coded Decimal (BCD) to 7-Segment decoder. These
decoders are commonly used when using a 7-segment display as seen in Figure. Each LED,
labelled a-g, takes a high or a low value. Using these LEDs, We can create numbers that are
easily readable. For this lab, we will be taking a BCD input and outputting the 7-segment
equivalent to our LEDs.
(Figure no. 3) 7-segment display
Here is the truth table for the decoder for an active high device. The display column
represents what number it would appear as on a 7-segment display. The outputs a-g
corresponds to the same values in Figure 1.
While this device can be implemented using combination logic, it is far easier to implement
using a case statement. We have used these before, but here is an example:
Case input is
When '0' => output <= '1';
When '1' => output <= '0';
end case;
This would simply check the value of a one bit input, and set the output to be the inverse of
the input. Using the case statement, you can check the input and set the output accordingly.
11. ( Figure no. 4) BCD to seven segment decoder
Here is a simple example. If I wanted to display 4 on the seven segment display, the first
thing I would do is check the truth table. Four 4 corresponds to the value “0110011” on an
active high device. Since we are using active low, it is inverted to “0110011”. I would set my
output to this value, so a = 0, b = 1, and so on.
12. 3. Tool used in project : Cadence tool
3.1 About CAD tool
Cadence tool is used to simulate the HDL programme and synthesize it Cadence Design
Systems is an American electronic design automation (EDA) software. This tool provides
physical layout of electronic chips as well as gate level description of any digital circuit. This
is generally called as CAD tool.
i. System level verification
For effective system-level verification, we require a high-performance environment that
allows access to hardware and software debuggers while running various system-level
scenarios using firmware, drivers, operating systems, and application software. Offering
higher throughput, superior hardware/software debug, and fast compilation, the Cadence
System Development Suite allow software developers to run and debug their designs on top
of a set of open, connected, and scalable platforms.
ii. Functional verification
Achieving a predictable path to verification closure requires automated planning and metrics
management with comprehensive coverage at block, chip, and system levels. Cadence
technology tracks the progress of an evolving design against its functional, performance, and
schedule objectives simultaneously.
iii. Gate level design
Decisions made during the architectural phase of the IC design cycle have a major impact on
the ultimate size, power consumption, performance, and cost of the final chip. Cadence chip
planning solutions enable design teams to balance these often conflicting goals by performing
rapid what-if analysis and optimizing design specifications to achieve an optimal chip plan.
iv. Digital implementation
To create a design layout that fulfils the often-conflicting objectives of performance, power,
and cost, engineers must perform comprehensive physical design space exploration and
feasibility analysis up front. And with the complexity and size of today’s designs, there is
need of a system with the capacity to handle 100M instances and more.
13. Cadence Giga Flex technology adapts to analyze complex giga-scale designs. Encounter
digital implementation is used to demonstrate tha physical layout of chip. It also includes the
latest low-power design and yield enhancement capabilities to support advanced node
designs.
14. 1. RTL description of 7-segment decoder
To get the RTL description of 7-segment decoder first we have to start the terminal. We need
h destination where we have to save all data regarding to our 7-segment. So a directory
named with work directory or say workdir. There is a sequential process for HDL description
of 7-segment decoder. (Enter the following steps at terminal window)
Step 1:- csh //to clear the window
Step 2:- source cshrc // to get in the cadence tool
Step 3:- cd workdir // to get in the work directory
Step 4:- gedit segment.v & // to open a new file named as “segment”
7- Segment code in Verilog
(Figure no 5) Verilog code of 7-segment decoder
Step 5:- ncvlog segment.v –mess // to run the file segment.v
15. Step 6:- gedit test_segment.v & // to create a new file that is testbench of segment.v
Step 7:- ncvlog –mess segment.v test_segment.v // to run both files parallel
Testbench for 7-segment decoder
(Figure no 6) Verilog code of test_segment.v
2. Functional verification and testing
Step 8:- ncelab –mess –access +rwc worklib.test_segment
16. (Figure no 7) execution of Verilog codes
Step 9:- ncsim –gui worklib.test_segment:module
17. (Figure no 8) waveform for 7-segment decoder
Now create a new folder according to the following path..
My computer >> workdir >> rclabs >> Decoder
A new folder is made named Decoder in rclabs. All the files regarding 7-segment design will
be stored in this folder. Now paste the HDL files segment.v and test_segment.v in the folder
named as Decoder.
Again work on the terminal window in workdir. To change the designation of file execution
from workdir to folder Decoder and to provide the storage path to Decoder, we have to enter
in the Decoder folder through rclabs. Now follow the steps as below...
Step 10:- cd rclabs
Step 11:- cd Decoder
18. Step 12:- rc
Step 13:- set_attribute lib_search_path ../library
Step 14:- set_attribute hdl_search_path ../rtl
Step 15:- set_attribute library slow_normal.lib
Step 16:- read_hdl –v2001 segment.v // here we have segment.v is my project file. If we
have more than a single file in a single project than we have to write “ read_hdl{file1.v
file2.v ..... file(n).v}
Step 17:-elaborate // or elab
Step 18:- gui_show
( Figure no 9) gate level diagram of 7-segment decoder
Instance:
ctl_BCD_17_7
Net bundle:
BN_12
Data path
20. ( Figure no 11 ) zoom view of instance: ctl_BCD_17_7
Step 20:- synthesize –to _mapped –effort medium
Step 21:- write_design –encounter –base Decoder/edi
Step 22:- exit
Step 23:- encounter // encounter tool window will be opened
Step 24:- file import
a. First select the file Decoder/edi.v
b. Select the all lef files (lef/all.lef)
c. Add power net Vdd
d. Add ground net Vss
e. Now have to analysis MMIC by adding the file Decoder/edi.mmode.tcl
f. Press ok to save all the specification
Step 24:- press F to fit the shape in the encounter window.
Step 25:- floor planning
a. Go to the option floor planning
21. b. Select specify floor plan
C.L=10
C.R=10
C.T=10
C.B=10
c. Press ok to save above specification
(Figure no 12) Floorplanning
Step 26:- power planning
a. Select the option power
b. Select power planning
c. Select add ring
1. Add the nets Vdd and Vss
2. Select vertical metal stripes :- metal 5H metal 5H
3. Select horizontal metal stripes:- metal 6V metal 6V
22. 4. Press ok to save above specification
Step 27:- now again select the option power and go through following..
a. Select power planning
b. Select add stripes
c. Add nets Vdd and Vss
d. Select horizontal metal layer metal 3
e. Change the set to set distance by 20
f. Press ok to save above specification
Step 28:- again select the option power and go through following
a. Select power planning
b. Select add stripes
c. Add power nets Vdd and Vss
d. Add vertical metal layer i.e. metal 4
e. Change set to set distance by 20
f. Press ok to save the above specification
Now move to the terminal window to place the design in encounter window.
(Figure no 13) powerplanning of layout
23. Step 29:- placeDesign
PlaceDesign will set the cells in the frame of metals. These cells can be individually checked.
There is a button “Q” which shows every detail of cell and metal strip. When button Q is
pressed, it gets activated and shows details about route and cells by clicking on that route and
cell. There are some additional commands like “checkPlace” and “refinePlace”.
Step 30:- now move to the encounter window and select option tools and then design
browser. Design browser will open a file which contains details related to the design.
(Figure no 14) design browser file
24. (Figure no. 15) layout of seven segment decoder
Step 31:- saveDesign <DesignName>.enc
This command will save the design in .enc or encounter file. Saved design can be called back
as per our requirement.
Step 32:- freeDesign
This command will free the encounter window from the design.
25. (Figure no 16) encounter window after freeDesign
Step 33:- sourceDesign <saved_file_name>.enc
This command is used to open the saved design. Here I have saved the design named as
segment.enc. Free design will close the design but when I have requirement of segment.enc
design, I can reopen this design file using “sourceDesign segment.enc”.
26. (Figure no 17) encounter window after sourceDesign
(Figure no 18) design without metal lines
Step 33:- gedit <design_name>.enc/viewDefinition.tcl &
27. This command will open a file in we have to overwrite constrains_top.g. Now save the file by
ctrl+s.
(Figure no 19) file viewDefinition.tcl
Step 34:- optDesign –preCTS
This command will optimize the design. Optimization in any design process is very
important. This will reduce the area as well as complexity of the design.
Step 35:- report_timing
28. This command will show how the input is processed to get the output. Each and every time is
recorded using this command. The whole timing process will be listed out after this
command.
Now move to the encounter window.
If there is a sequential circuit which we have to design then a clock tree is synthesized using
option synthesize clock tree. After selecting synthesize clock tree, select generate clock tree.
There will be a no of CLKBUF (clock buffers). Add all the clock buffers in the clock tree.
This will generate a file named as clock.ctsch and press ok. All the selected clockbuffers will
be added into design file.
Now move to the terminal window and open the file clock.ctstch &. Let the file opened and
move towards the encounter. We see that clock buffers are added in the design layout. But
here we have a combinational circuit so there is no need to add clock buffers in the design
layout.
Now move to the terminal window.
Step 34:- routeDesign
This command is used to make route of all the unconnected wires. Routing will provide us a
continuous path to flow current from one end to another. It provides a uninterrupted path till
input reaches to the output.
29. (Figure no 20) rounted physical layout
Now move to the encounter tool window.
Step 35:- select option verify and then select verify geometry then press ok.
Verify geometry will check all the connections, timing of input and output, routing etc. To
extract the GDSII file go to
click ok to generate.
30. Result
There is no error and warning occurred in the compilation process of Verilog code.
Both the codes i.e. main module and 7-segment testbench code are right to work.
Waveform for 7-segment decoder is correct as per our input in the testbench.
Gate level circuit is successfully generated.
Front end is completed at this gate level circuit without any error.
Starting with the backend using encounter tool window, 7-segment physical layout is
obtained as followed picture.
(Figure no 21) final routed and verified physical layout
there are 21 leaf cells, 11 terms, 25 Nets, 19 Std cells are included.
