Rems final
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The document discusses a new algorithm called REMS (Re modified Enhanced Merger Sorter Network) for implementing encryption algorithms in hardware. REMS improves upon previous algorithms like MEMS by providing richer encryption, consuming less power, and better representing the underlying GRP algorithm. It divides the data into left and right datapaths with different control words for different stages, preserving most significant bits to avoid loss of information. Simulation results show REMS reduces the number of multiplexers and delay compared to previous approaches.
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stays valid with a remarkable hit rate of 95%!
SMART AS A CRYPTOGRAPHIC PROCESSOR
SMaRT is a 16-bit 2.5-address RISC-type single-cycle processor, which was recently designed and successfully mapped into a FPGA chip in our ECE department. In this paper, we use SMaRT to run the well-known encryption algorithm, Data Encryption Standard. For information security purposes, encryption is a must in today’s sophisticated and ever-increasing computer communications such as ATM machines and SIM cards. For comparison and evaluation purposes, we also map the same algorithm on the HC12, a same-size but CISC-type off-the-shelf microcontroller, Our results show that compared to HC12, SMaRT code is only 14% longer in terms of the static number of instructions but about 10 times faster in terms of the number of clock cycles, and 7% smaller in terms of code size. Our results also show that 2.5- address instructions, a SMaRT selling point, amount to 45% of the whole R-type instructions resulting in significant improvement in static number of instructions hence code size as well as performance. Additionally, we see that the SMaRT short-branch range is sufficiently wide in 90% of cases in the SMaRT code. Our results also reveal that the SMaRT novel concept of locality of reference in using the MSBs of the registers in non-subroutine branch instructions stays valid with a remarkable hit rate of 95%!
An Energy-Efficient Lut-Log-Bcjr Architecture Using Constant Log Bcjr Algorithm
Error correcting codes are used to correct the data from the corrupted signal due to noise and interference. There
are many error correcting codes. Among them turbo codes is considered to be the best because it is very close to
the Shannon theoretical limit. The MAP algorithm is commonly used in the turbo decoder. Among the different
versions of the MAP algorithm Constant log BCJR algorithm have less complexity and good error performance.
The Constant log BCJR algorithm can be easily designed using look up table which reduces the memory
consumption. The proposed Constant log BCJR decoder is designed to decode two blocks of data at a time, this
increases the throughput. The complexity of the decoder is further reduced by the use of the add compare select
(ACS) units and registers. The proposed decoder is simulated using Xilinx ISE and synthesized using Sparten3
FPGA and found out that Constant log BCJR decoder utilized less amount of memory and power than the LUT
log BCJR decoder.
Fpga based efficient multiplier for image processing applications using recur...
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etc., rely on multipliers to improve the quality of image. However, existing multiplication techniques
introduce errors in the output with consumption of more time, hence error free high speed multipliers has
to be designed. In this paper we propose FPGA based Recursive Error Free Mitchell Log Multiplier
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introducing error correction term is used in higher order Karastuba-Ofman Multiplier (KOM)
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using radix 2 till basic multiplier block of order 2x2 which is designed by error free Mitchell log multiplier.
The 8x8 REFMLM is tested for Gaussian filter to remove noise in fingerprint image. The Multiplier is
synthesized using Spartan 3 FPGA family device XC3S1500-5fg320. It is observed that the performance
parameters such as area utilization, speed, error and PSNR are better in the case of proposed architecture
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- 1. Mr. Gaurav Bansod Mtech (Embedded Systems) Symbiosis Institute Of Technology
- 8. CODE WORD GENERATION Gaurav Bansod
- 17. REMS LEFTDATAPATH TRANSMITTER Gaurav Bansod
- 19. REMS LEFTDATAPATH RECEIVER Gaurav Bansod
- 23. RIGHTDATAPATH Tx AND Rx Gaurav Bansod
- 25. Results and Analysis Gaurav Bansod
- 27. DELAY CALCULATION Gaurav Bansod