This document summarizes several research papers on low-density parity-check (LDPC) coding for wireless data transmission using Raspberry Pi modules. Specifically:
(1) It discusses implementations of LDPC encoding and decoding of text data using Raspberry Pi modules connected over Wi-Fi, with decoding using sum-product algorithms.
(2) It mentions other research on minimizing bit error rate using specific LDPC parity matrix structures and efficient encoding/decoding techniques.
(3) The document reviews various approaches to LDPC coding implementation including using FPGAs, ZigBee modules, and novel decoding algorithms.
FPGA Implementation of LDPC Encoder for Terrestrial TelevisionAI Publications
The increasing data rates in digital television networks increase the demands on data capacity of the current transmission channels. Through new standards, the capacity of existing channels is increased with new methods of error correction coding and modulation. In this work, Low Density Parity Check (LDPC) codes are implemented for their error correcting capability. LDPC is a linear error correcting code. These linear error correcting codes are used for transmitting a message over a noisy transmission channel. LDPC codes are finding increasing use in applications requiring reliable and highly efficient information transfer over noisy channels. These codes are capable of performing near to Shannon limit performance and have low decoding complexity. LDPC uses parity check matrix for its encoding and decoding purpose. The main advantage of the parity check matrix is that it helps in detecting and correcting errors which is a very important advantage against noisy channels. This work presents the design and implementation of a LDPC encoder for transmission of digital terrestrial television according to the Chinese DTMB standard. The system is written in Verilog and is implemented on FPGA. The whole work is then verified with the help of Matlab modelling.
FPGA Implementation of Efficient Viterbi Decoder for Multi-Carrier SystemsIJMER
In this paper, we concern with designing and implementing a Convolutional encoder and
Adaptive Viterbi Decoder (AVD) which are the essential blocks in digital communication system using
FPGA technology. Convolutional coding is a coding scheme used in communication systems for error
correction employed in applications like deep space communications and wireless communications. It
provides an alternative approach to block codes for transmission over a noisy channel. The block
codes can be applied only for the blocks of data where as the Convolutional coding has an advantage
that it can be applied to both continuous data stream and blocks of data. The Viterbi decoder with
PNPH (Permutation Network based Path History) management unit which is a special path
management unit for faster decoding speed with less routing area. The proposed architecture can be
realized by an Adaptive Viterbi Decoder having constraint length, K of 3 and a code rate (k/n) of 1/2
using Verilog HDL. Simulation is done using Xilinx ISE 12.4i design software and it is targeted into
Xilinx Virtex-5, XC5VLX110T FPGA
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
An efficient transcoding algorithm for G.723.1 and G.729A ...Videoguy
This document proposes an efficient transcoding algorithm to translate between the G.723.1 and G.729A speech coding standards. The algorithm has four main steps: 1) converting line spectral pair parameters between the two codecs, 2) converting pitch intervals using a smoothing technique, 3) performing a fast adaptive codebook search, and 4) performing a fast fixed codebook search. Objective and subjective tests show the algorithm achieves comparable speech quality to tandem encoding/decoding with 26-38% lower complexity and shorter delay.
1) The document discusses a Max Log MAP algorithm for decoding turbo codes used in LTE systems. Max Log MAP reduces complexity compared to the Log MAP algorithm while maintaining similar decoding performance.
2) Turbo codes achieve error correction close to the Shannon limit through iterative decoding between two soft-input soft-output decoders using extrinsic information.
3) The Max Log MAP algorithm approximates the logarithm calculation in turbo decoding to reduce complexity, maintaining performance close to but slightly worse than the standard Log MAP algorithm.
The document discusses a study that implemented low density parity check (LDPC) decoding using a min sum algorithm with reduced complexity compared to existing methods. It used quadrature phase-shift keying (QPSK) modulation to improve bit error rate over previous approaches that used binary phase-shift keying (BPSK) modulation. The proposed method was able to achieve a lower bit error rate than other existing techniques using fewer iterations, improving performance flexibility by varying the code size. It implemented LDPC decoding on an irregular parity check matrix using a split row technique to reduce interconnect complexity and increase parallelism in the row processing stage compared to standard decoding algorithms.
Design and Implementation of an Embedded System for Software Defined RadioIJECEIAES
In this paper, developing high performance software for demanding real-time embed- ded systems is proposed. This software-based design will enable the software engineers and system architects in emerging technology areas like 5G Wireless and Software Defined Networking (SDN) to build their algorithms. An ADSP-21364 floating point SHARC Digital Signal Processor (DSP) running at 333 MHz is adopted as a platform for an embedded system. To evaluate the proposed embedded system, an implementation of frame, symbol and carrier phase synchronization is presented as an application. Its performance is investigated with an on line Quadrature Phase Shift keying (QPSK) receiver. Obtained results show that the designed software is implemented successfully based on the SHARC DSP which can utilized efficiently for such algorithms. In addition, it is proven that the proposed embedded system is pragmatic and capable of dealing with the memory constraints and critical time issue due to a long length interleaved coded data utilized for channel coding.
This document describes the implementation of a Viterbi decoder using VHDL. It begins with background on convolutional encoding, the Viterbi algorithm for decoding convolutional codes, and the basic structure of a Viterbi decoder. It then discusses the design and simulation of a rate 1/2 constraint length 3 Viterbi decoder in VHDL targeting the Spartan-3A FPGA. Simulation results and comparisons to other FPGA devices are presented.
FPGA Implementation of LDPC Encoder for Terrestrial TelevisionAI Publications
The increasing data rates in digital television networks increase the demands on data capacity of the current transmission channels. Through new standards, the capacity of existing channels is increased with new methods of error correction coding and modulation. In this work, Low Density Parity Check (LDPC) codes are implemented for their error correcting capability. LDPC is a linear error correcting code. These linear error correcting codes are used for transmitting a message over a noisy transmission channel. LDPC codes are finding increasing use in applications requiring reliable and highly efficient information transfer over noisy channels. These codes are capable of performing near to Shannon limit performance and have low decoding complexity. LDPC uses parity check matrix for its encoding and decoding purpose. The main advantage of the parity check matrix is that it helps in detecting and correcting errors which is a very important advantage against noisy channels. This work presents the design and implementation of a LDPC encoder for transmission of digital terrestrial television according to the Chinese DTMB standard. The system is written in Verilog and is implemented on FPGA. The whole work is then verified with the help of Matlab modelling.
FPGA Implementation of Efficient Viterbi Decoder for Multi-Carrier SystemsIJMER
In this paper, we concern with designing and implementing a Convolutional encoder and
Adaptive Viterbi Decoder (AVD) which are the essential blocks in digital communication system using
FPGA technology. Convolutional coding is a coding scheme used in communication systems for error
correction employed in applications like deep space communications and wireless communications. It
provides an alternative approach to block codes for transmission over a noisy channel. The block
codes can be applied only for the blocks of data where as the Convolutional coding has an advantage
that it can be applied to both continuous data stream and blocks of data. The Viterbi decoder with
PNPH (Permutation Network based Path History) management unit which is a special path
management unit for faster decoding speed with less routing area. The proposed architecture can be
realized by an Adaptive Viterbi Decoder having constraint length, K of 3 and a code rate (k/n) of 1/2
using Verilog HDL. Simulation is done using Xilinx ISE 12.4i design software and it is targeted into
Xilinx Virtex-5, XC5VLX110T FPGA
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
An efficient transcoding algorithm for G.723.1 and G.729A ...Videoguy
This document proposes an efficient transcoding algorithm to translate between the G.723.1 and G.729A speech coding standards. The algorithm has four main steps: 1) converting line spectral pair parameters between the two codecs, 2) converting pitch intervals using a smoothing technique, 3) performing a fast adaptive codebook search, and 4) performing a fast fixed codebook search. Objective and subjective tests show the algorithm achieves comparable speech quality to tandem encoding/decoding with 26-38% lower complexity and shorter delay.
1) The document discusses a Max Log MAP algorithm for decoding turbo codes used in LTE systems. Max Log MAP reduces complexity compared to the Log MAP algorithm while maintaining similar decoding performance.
2) Turbo codes achieve error correction close to the Shannon limit through iterative decoding between two soft-input soft-output decoders using extrinsic information.
3) The Max Log MAP algorithm approximates the logarithm calculation in turbo decoding to reduce complexity, maintaining performance close to but slightly worse than the standard Log MAP algorithm.
The document discusses a study that implemented low density parity check (LDPC) decoding using a min sum algorithm with reduced complexity compared to existing methods. It used quadrature phase-shift keying (QPSK) modulation to improve bit error rate over previous approaches that used binary phase-shift keying (BPSK) modulation. The proposed method was able to achieve a lower bit error rate than other existing techniques using fewer iterations, improving performance flexibility by varying the code size. It implemented LDPC decoding on an irregular parity check matrix using a split row technique to reduce interconnect complexity and increase parallelism in the row processing stage compared to standard decoding algorithms.
Design and Implementation of an Embedded System for Software Defined RadioIJECEIAES
In this paper, developing high performance software for demanding real-time embed- ded systems is proposed. This software-based design will enable the software engineers and system architects in emerging technology areas like 5G Wireless and Software Defined Networking (SDN) to build their algorithms. An ADSP-21364 floating point SHARC Digital Signal Processor (DSP) running at 333 MHz is adopted as a platform for an embedded system. To evaluate the proposed embedded system, an implementation of frame, symbol and carrier phase synchronization is presented as an application. Its performance is investigated with an on line Quadrature Phase Shift keying (QPSK) receiver. Obtained results show that the designed software is implemented successfully based on the SHARC DSP which can utilized efficiently for such algorithms. In addition, it is proven that the proposed embedded system is pragmatic and capable of dealing with the memory constraints and critical time issue due to a long length interleaved coded data utilized for channel coding.
This document describes the implementation of a Viterbi decoder using VHDL. It begins with background on convolutional encoding, the Viterbi algorithm for decoding convolutional codes, and the basic structure of a Viterbi decoder. It then discusses the design and simulation of a rate 1/2 constraint length 3 Viterbi decoder in VHDL targeting the Spartan-3A FPGA. Simulation results and comparisons to other FPGA devices are presented.
Transfer of ut information from fpga through ethernet interfaceeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A new channel coding technique to approach the channel capacityijwmn
After Shannon’s 1948 channel coding theorem, we have witnessed many channel coding techniques developed to achieve the Shannon limit. A wide range of channel codes is available with different complexity levels and error correction performance. Many powerful coding schemes have been deployed in the power-limited Additive White Gaussian Noise (AWGN) channel. However, it seems like we have arrived at an end of advancement path, for most of the existing channel codes. This article introduces a new coding technique that can either be used as the last coding stage of concatenated coding scheme or in parallel configuration with other powerful channel codes to achieve reliable error performance with moderately complex decoding. We will go through an example to understand the overall approach of the proposed coding technique, and finally we will look at some simulation results over an AWGN channel to demonstrate its potential.
Chaos Encryption and Coding for Image Transmission over Noisy Channelsiosrjce
IOSR Journal of Computer Engineering (IOSR-JCE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of computer engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in computer technology. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This document discusses using low density generator matrix (LDGM) codes for source coding and joint source-channel coding of correlated sources. Key points:
- LDGM codes can achieve near-Shannon limit performance for channel coding with lower complexity than LDPC codes. Serial and parallel concatenated LDGM codes are proposed.
- LDGM codes are applied to source coding of correlated sources modeled by a hidden Markov model. Simulation results show the codes achieve rates close to the theoretical limits.
- LDGM codes are also used for joint source-channel coding of correlated sources over independent noisy channels. Different decoding schedules are evaluated. Results show the codes perform well for both AWGN and Rayleigh fading channels.
This document discusses the Argon2id cryptographic hash function. Argon2id is designed to be memory-hard to resist password cracking attacks. It is composed of two variants, Argon2d and Argon2i. Argon2d maximizes resistance to GPU attacks by accessing memory in a password-dependent order, while Argon2i accesses memory independently of the password to resist side-channel attacks. The document describes the specification, operation, and implementation of Argon2id using the Blake2b hash function. Argon2id takes inputs like a password, salt, and parameters and iterates the Blake2b compression function over a memory array to produce the output hash.
FPGA Implementation of Mixed Radix CORDIC FFTIJSRD
In this Paper, the architecture and FPGA implementation of a Coordinate Rotation Digital Computer (CORDIC) pipeline Fast Fourier Transform (FFT) processor is presented. Fast Fourier Transforms (FFT) is highly efficient algorithm which uses Divide and Conquer approach for speedy calculation of Discrete Fourier transform (DFT) to obtain the frequency spectrum. CORDIC algorithm which is hardware efficient and avoids the use of conventional multiplication and accumulation (MAC) units but evaluates the trigonometric functions by the rotation of a complex vector by means of only add and shift operations. We have developed Fixed point FFT processors using VHDL language for implementation on Field Programmable Gate Array. A Mixed Radix 8 point DIF FFT/IFFT architecture with CORDIC Twiddle factor generation unit with use of pipeline implementation FFT processor has been developed using Xilinx XC3S500E Spartan-3E FPGA and simulated with maximum frequency of 157.359 MHz for 16 bit length 8 point FFT. Results show that the processor uses less number of LUTs and achieves Maximum Frequency.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
Hardware implementation of (63, 51) bch encoder and decoder for wban using lf...ijitjournal
Error Correcting Codes are required to have a reliable communication through a medium that has an
unacceptable bit error rate and low signal to noise ratio. In IEEE 802.15.6 2.4GHz Wireless Body Area
Network (WBAN), data gets corrupted during the transmission and reception due to noises and
interferences. Ultra low power operation is crucial to prolong the life of implantable devices. Hence simple
block codes like BCH (63, 51, 2) can be employed in the transceiver design of 802.15.6 Narrowband PHY.
In this paper, implementation of BCH (63, 51, t = 2) Encoder and Decoder using VHDL is discussed. The
incoming 51 bits are encoded into 63 bit code word using (63, 51) BCH encoder. It can detect and correct
up to 2 random errors. The design of an encoder is implemented using Linear Feed Back Shift Register
(LFSR) for polynomial division and the decoder design is based on syndrome calculator, inversion-less
Berlekamp-Massey algorithm (BMA) and Chien search algorithm. Synthesis and simulation were carried
out using Xilinx ISE 14.2 and ModelSim 10.1c. The codes are implemented over Virtex 4 FPGA device and
tested on DN8000K10PCIE Logic Emulation Board. To the best of our knowledge, it is the first time an
implementation of (63, 51) BCH encoder and decoder carried out.
Performance Evaluation of IPv4 Vs Ipv6 and Tunnelling Techniques Using Optimi...IOSR Journals
This document compares the performance of IPv4, IPv6, and tunneling (6to4) networks using computer simulations in OPNET 17.5. The simulation analyzed delay, throughput, and packet loss over 1 hour. The results showed that IPv6 had higher delay than IPv4 due to its larger header, while tunneling had the highest delay. Throughput was highest for IPv6 and lowest for IPv4. Packet loss was lowest for IPv4 and highest for IPv6. In conclusion, the network performance varied between the different addressing schemes and tunneling in terms of delay, throughput, and packet loss.
Turbo codes are a type of error correcting code that can achieve performance close to the theoretical maximum allowed by Shannon's limit. Turbo codes use an iterative decoding process between two recursive systematic convolutional encoders separated by an interleaver. This iterative decoding allows turbo codes to correct errors very efficiently. Turbo codes are used in applications like deep space communications and mobile phone networks due to their ability to operate reliably at low signal-to-noise ratios.
A 12-Bit High Speed Analog To Digital Convertor Using μp 8085IJERA Editor
The need constantly exists for converters with higher resolution, faster conversion speeds and lower power dissipation. High-speed analog to digital converters (ADC’s) have been based on flash architecture, because all comparators sample the analog input voltage simultaneously, this ADC is thus inherently fast. Unfortunately, flash ADC requires 2N - 1 comparators to convert N bit digital code from an analog sample. This makes flash ADC’s unsuitable for high-resolution applications. This paper demonstrates a simple technique to enhance resolution of flash ADC’s that require as few as 256 comparators for 12-bit conversion. In this approach, the analog input range is partitioned into 256 quantization cells, separated by 255 boundary points. An 8-bit binary code 00000000 to 11111111 is assigned to each cell. A 12-bit flash converter requires 4096 comparators, while proposed technique reduces number of comparator requirements to only 256 for 12- bit conversion. Therefore, this technique is best suitable when high speed combined with high resolution is required. Result of 12-bit prototype is presented.
This document summarizes the porting and optimization of the ITU-T G.729.1 speech coding algorithm to the SC3850 DSP core. The authors modified the reference G.729.1 code to fix-point C and optimized it for the SC3850 architecture through techniques like replacing functions with intrinsics, inlining small functions, and restructuring loops and memory accesses. They achieved over 90% improvement in cycles per second (MCPS) through these optimizations while maintaining bit-exact accuracy against the ITU test vectors. The G.729.1 codec is an 8-32 kbps scalable wideband speech codec standardized by ITU, useful for applications like VoIP, audio conferencing, and
IRJET - Design of RISC-V Bit Manipulation Instruction IP using Bluespec S...IRJET Journal
This document describes the design of a bit manipulation instruction IP using Bluespec SystemVerilog for the RISC-V architecture. The IP implements 106 bit manipulation instructions proposed as an extension to the RISC-V instruction set. The design is a combinational logic block that takes instruction encoding and source operands as input and produces a result register in a single clock cycle. The IP was optimized to reduce logic gates and LUT count. Simulation results showed that all instructions executed correctly in a single cycle. Area analysis showed a reduction in LUT usage from optimizing common functions and reducing decoder multiplexer inputs.
-Study of the functionality of 2MB mother board, providing E1 data interfaces
-CMS LAB,TEST EQUIPMENT, QUALITY CONTROL. - ABOUT BEL,ROTATIONAL PROGRAM.-FPGA,ADSP,DSO,VHDL.
-E1 EUROPEAN DATA FORMAT , LINK, SPECIFICATION
ENCODING TECHNIQUES- HDB3, AMI
Performance analysis and implementation for nonbinary quasi cyclic ldpc decod...ijwmn
Non-binary low-density parity check (NB-LDPC) codes are an extension of binary LDPC codes with
significantly better performance. Although various kinds of low-complexity iterative decoding algorithms
have been proposed, there is a big challenge for VLSI implementation of NBLDPC decoders due to its high
complexity and long latency. In this brief, highly efficient check node processing scheme, which the
processing delay greatly reduced, including Min-Max decoding algorithm and check node unit are
proposed. Compare with previous works, less than 52% could be reduced for the latency of check node
unit. In addition, the efficiency of the presented techniques is design to demonstrate for the (620, 310) NBQC-
LDPC decoder.
LDPC BASED ERROR CORRECTION WITH BIT LEVEL AND SYMBOL LEVEL SYNCHRONIZATION USING MARKER CODE OPTIMIZATION
Low-density parity check code with error-correction capabilities and Marker code for synchronization purposes are used
The marker code structures offer the ultimate achievable rate when standard bit-level synchronization are performed
Symbol-level synchronization algorithm works on group of bits and show how it improves the achievable rate along with the error rate performance
When multiple pass decoding is performed the extrinsic information transfer (EXIT) charts are used to analyze the receiver
Performance Analysis of DRA Based OFDM Data Transmission With Respect to Nove...IJERA Editor
In this paper, we have analyzed the performance characteristics of OFDM data transmission with regard to a new high speed RS decoding algorithm. The various characteristics identified are mainly speed and accuracy of the transmission irrespective of channel behaviour. We consider two cases viz. data transmission without error control and data transmission with error control. Each of these cases are duly analyzed and it is proven that high speed RS decoding algorithms can actually benefit OFDM data transmission for advanced communication systems only if implemented at the hardware (VLSI) level because of significant processing overhead involved in software based implementation even though the algorithm may have lower computational complexity.
Polar codes are one of the best linear block codes that are capacity achieving and incorporating along with it a simplified encoding and decoding routines. Successive cancellation (SC) algorithm is one of the predominantly used decoding algorithms due to its low complexity. It has broad scopes for hardware architecture design and reformulation. For polar code, the trade-off among the long latency and the silicon area of the SC algorithm is a bottleneck for the design of a high throughput polar decoder. The available prior SC polar decoder designs have higher area requirements for higher block length. This paper introduces a unique reformulation of the processing element (PE) block of SC decoding. The proposed reformulation leads to two benefits: firstly, critical path and hardware complexity of the PE are meaningfully reduced by using a unified adder block. Secondly, the silicon area requirement and the power consumption were also reduced considerably without any loss in performance. The proposed PE is used to build the decoder for various block lengths. Moreover, a Gate-level analysis of the proposed decoder has revealed that the design attains an 18% area reduction and 38% reduction in power consumption over the conventional one with similar performance.
Design and Implementation of Low Power High Speed Symmetric Decoder Structure...Dr. Amarjeet Singh
The key objective of this project is to design a
decoder which can be used for hardware purposes.
Hardware, here accompanies with software which is more
we can discuss as a Software Defined Radio application. The
decoder implemented here offers to new radio equipment
(SDR), the flexibility of a programmable system. Nowadays,
the behavior of a communication system can be modified by
simply changing its software. Large tree decoder is made by
reusing smaller similar sub-modules. Thus the structure is
symmetric. The symmetric and regular structure of tree
decoder makes the system a less complexity one. The
structure obeys regularity and modularity concepts of VLSI
circuit, thus is easy to fabricate using cell library elements.
Design a Tree Decoder proposed architecture for SDR
application on FPGA. The Structures made here are
hardware synthesizable on FPGA board and are done in a
respective manner. The design to be implementing by using
Verilog-HDL language. The Simulation and Synthesis by
using Xilinx Vivado design suite.
Turbo codes are error-correcting codes with performance that is close to the
Shannon theoretical limit (SHA). The motivation for using turbo codes is
that the codes are an appealing mix of a random appearance on the channel
and a physically realizable decoding structure. The communication systems
have the problem of latency, fast switching, and reliable data transfer. The
objective of the research paper is to design and turbo encoder and decoder
hardware chip and analyze its performance. Two convolutional codes are
concatenated concurrently and detached by an interleaver or permuter in the
turbo encoder. The expected data from the channel is interpreted iteratively
using the two related decoders. The soft (probabilistic) data about an
individual bit of the decoded structure is passed in each cycle from one
elementary decoder to the next, and this information is updated regularly.
The performance of the chip is also verified using the maximum a posteriori
(MAP) method in the decoder chip. The performance of field-programmable
gate array (FPGA) hardware is evaluated using hardware and timing
parameters extracted from Xilinx ISE 14.7. The parallel concatenation offers
a better global rate for the same component code performance, and reduced
delay, low hardware complexity, and higher frequency support.
Transfer of ut information from fpga through ethernet interfaceeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A new channel coding technique to approach the channel capacityijwmn
After Shannon’s 1948 channel coding theorem, we have witnessed many channel coding techniques developed to achieve the Shannon limit. A wide range of channel codes is available with different complexity levels and error correction performance. Many powerful coding schemes have been deployed in the power-limited Additive White Gaussian Noise (AWGN) channel. However, it seems like we have arrived at an end of advancement path, for most of the existing channel codes. This article introduces a new coding technique that can either be used as the last coding stage of concatenated coding scheme or in parallel configuration with other powerful channel codes to achieve reliable error performance with moderately complex decoding. We will go through an example to understand the overall approach of the proposed coding technique, and finally we will look at some simulation results over an AWGN channel to demonstrate its potential.
Chaos Encryption and Coding for Image Transmission over Noisy Channelsiosrjce
IOSR Journal of Computer Engineering (IOSR-JCE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of computer engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in computer technology. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This document discusses using low density generator matrix (LDGM) codes for source coding and joint source-channel coding of correlated sources. Key points:
- LDGM codes can achieve near-Shannon limit performance for channel coding with lower complexity than LDPC codes. Serial and parallel concatenated LDGM codes are proposed.
- LDGM codes are applied to source coding of correlated sources modeled by a hidden Markov model. Simulation results show the codes achieve rates close to the theoretical limits.
- LDGM codes are also used for joint source-channel coding of correlated sources over independent noisy channels. Different decoding schedules are evaluated. Results show the codes perform well for both AWGN and Rayleigh fading channels.
This document discusses the Argon2id cryptographic hash function. Argon2id is designed to be memory-hard to resist password cracking attacks. It is composed of two variants, Argon2d and Argon2i. Argon2d maximizes resistance to GPU attacks by accessing memory in a password-dependent order, while Argon2i accesses memory independently of the password to resist side-channel attacks. The document describes the specification, operation, and implementation of Argon2id using the Blake2b hash function. Argon2id takes inputs like a password, salt, and parameters and iterates the Blake2b compression function over a memory array to produce the output hash.
FPGA Implementation of Mixed Radix CORDIC FFTIJSRD
In this Paper, the architecture and FPGA implementation of a Coordinate Rotation Digital Computer (CORDIC) pipeline Fast Fourier Transform (FFT) processor is presented. Fast Fourier Transforms (FFT) is highly efficient algorithm which uses Divide and Conquer approach for speedy calculation of Discrete Fourier transform (DFT) to obtain the frequency spectrum. CORDIC algorithm which is hardware efficient and avoids the use of conventional multiplication and accumulation (MAC) units but evaluates the trigonometric functions by the rotation of a complex vector by means of only add and shift operations. We have developed Fixed point FFT processors using VHDL language for implementation on Field Programmable Gate Array. A Mixed Radix 8 point DIF FFT/IFFT architecture with CORDIC Twiddle factor generation unit with use of pipeline implementation FFT processor has been developed using Xilinx XC3S500E Spartan-3E FPGA and simulated with maximum frequency of 157.359 MHz for 16 bit length 8 point FFT. Results show that the processor uses less number of LUTs and achieves Maximum Frequency.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
Hardware implementation of (63, 51) bch encoder and decoder for wban using lf...ijitjournal
Error Correcting Codes are required to have a reliable communication through a medium that has an
unacceptable bit error rate and low signal to noise ratio. In IEEE 802.15.6 2.4GHz Wireless Body Area
Network (WBAN), data gets corrupted during the transmission and reception due to noises and
interferences. Ultra low power operation is crucial to prolong the life of implantable devices. Hence simple
block codes like BCH (63, 51, 2) can be employed in the transceiver design of 802.15.6 Narrowband PHY.
In this paper, implementation of BCH (63, 51, t = 2) Encoder and Decoder using VHDL is discussed. The
incoming 51 bits are encoded into 63 bit code word using (63, 51) BCH encoder. It can detect and correct
up to 2 random errors. The design of an encoder is implemented using Linear Feed Back Shift Register
(LFSR) for polynomial division and the decoder design is based on syndrome calculator, inversion-less
Berlekamp-Massey algorithm (BMA) and Chien search algorithm. Synthesis and simulation were carried
out using Xilinx ISE 14.2 and ModelSim 10.1c. The codes are implemented over Virtex 4 FPGA device and
tested on DN8000K10PCIE Logic Emulation Board. To the best of our knowledge, it is the first time an
implementation of (63, 51) BCH encoder and decoder carried out.
Performance Evaluation of IPv4 Vs Ipv6 and Tunnelling Techniques Using Optimi...IOSR Journals
This document compares the performance of IPv4, IPv6, and tunneling (6to4) networks using computer simulations in OPNET 17.5. The simulation analyzed delay, throughput, and packet loss over 1 hour. The results showed that IPv6 had higher delay than IPv4 due to its larger header, while tunneling had the highest delay. Throughput was highest for IPv6 and lowest for IPv4. Packet loss was lowest for IPv4 and highest for IPv6. In conclusion, the network performance varied between the different addressing schemes and tunneling in terms of delay, throughput, and packet loss.
Turbo codes are a type of error correcting code that can achieve performance close to the theoretical maximum allowed by Shannon's limit. Turbo codes use an iterative decoding process between two recursive systematic convolutional encoders separated by an interleaver. This iterative decoding allows turbo codes to correct errors very efficiently. Turbo codes are used in applications like deep space communications and mobile phone networks due to their ability to operate reliably at low signal-to-noise ratios.
A 12-Bit High Speed Analog To Digital Convertor Using μp 8085IJERA Editor
The need constantly exists for converters with higher resolution, faster conversion speeds and lower power dissipation. High-speed analog to digital converters (ADC’s) have been based on flash architecture, because all comparators sample the analog input voltage simultaneously, this ADC is thus inherently fast. Unfortunately, flash ADC requires 2N - 1 comparators to convert N bit digital code from an analog sample. This makes flash ADC’s unsuitable for high-resolution applications. This paper demonstrates a simple technique to enhance resolution of flash ADC’s that require as few as 256 comparators for 12-bit conversion. In this approach, the analog input range is partitioned into 256 quantization cells, separated by 255 boundary points. An 8-bit binary code 00000000 to 11111111 is assigned to each cell. A 12-bit flash converter requires 4096 comparators, while proposed technique reduces number of comparator requirements to only 256 for 12- bit conversion. Therefore, this technique is best suitable when high speed combined with high resolution is required. Result of 12-bit prototype is presented.
This document summarizes the porting and optimization of the ITU-T G.729.1 speech coding algorithm to the SC3850 DSP core. The authors modified the reference G.729.1 code to fix-point C and optimized it for the SC3850 architecture through techniques like replacing functions with intrinsics, inlining small functions, and restructuring loops and memory accesses. They achieved over 90% improvement in cycles per second (MCPS) through these optimizations while maintaining bit-exact accuracy against the ITU test vectors. The G.729.1 codec is an 8-32 kbps scalable wideband speech codec standardized by ITU, useful for applications like VoIP, audio conferencing, and
IRJET - Design of RISC-V Bit Manipulation Instruction IP using Bluespec S...IRJET Journal
This document describes the design of a bit manipulation instruction IP using Bluespec SystemVerilog for the RISC-V architecture. The IP implements 106 bit manipulation instructions proposed as an extension to the RISC-V instruction set. The design is a combinational logic block that takes instruction encoding and source operands as input and produces a result register in a single clock cycle. The IP was optimized to reduce logic gates and LUT count. Simulation results showed that all instructions executed correctly in a single cycle. Area analysis showed a reduction in LUT usage from optimizing common functions and reducing decoder multiplexer inputs.
-Study of the functionality of 2MB mother board, providing E1 data interfaces
-CMS LAB,TEST EQUIPMENT, QUALITY CONTROL. - ABOUT BEL,ROTATIONAL PROGRAM.-FPGA,ADSP,DSO,VHDL.
-E1 EUROPEAN DATA FORMAT , LINK, SPECIFICATION
ENCODING TECHNIQUES- HDB3, AMI
Performance analysis and implementation for nonbinary quasi cyclic ldpc decod...ijwmn
Non-binary low-density parity check (NB-LDPC) codes are an extension of binary LDPC codes with
significantly better performance. Although various kinds of low-complexity iterative decoding algorithms
have been proposed, there is a big challenge for VLSI implementation of NBLDPC decoders due to its high
complexity and long latency. In this brief, highly efficient check node processing scheme, which the
processing delay greatly reduced, including Min-Max decoding algorithm and check node unit are
proposed. Compare with previous works, less than 52% could be reduced for the latency of check node
unit. In addition, the efficiency of the presented techniques is design to demonstrate for the (620, 310) NBQC-
LDPC decoder.
LDPC BASED ERROR CORRECTION WITH BIT LEVEL AND SYMBOL LEVEL SYNCHRONIZATION USING MARKER CODE OPTIMIZATION
Low-density parity check code with error-correction capabilities and Marker code for synchronization purposes are used
The marker code structures offer the ultimate achievable rate when standard bit-level synchronization are performed
Symbol-level synchronization algorithm works on group of bits and show how it improves the achievable rate along with the error rate performance
When multiple pass decoding is performed the extrinsic information transfer (EXIT) charts are used to analyze the receiver
Performance Analysis of DRA Based OFDM Data Transmission With Respect to Nove...IJERA Editor
In this paper, we have analyzed the performance characteristics of OFDM data transmission with regard to a new high speed RS decoding algorithm. The various characteristics identified are mainly speed and accuracy of the transmission irrespective of channel behaviour. We consider two cases viz. data transmission without error control and data transmission with error control. Each of these cases are duly analyzed and it is proven that high speed RS decoding algorithms can actually benefit OFDM data transmission for advanced communication systems only if implemented at the hardware (VLSI) level because of significant processing overhead involved in software based implementation even though the algorithm may have lower computational complexity.
Polar codes are one of the best linear block codes that are capacity achieving and incorporating along with it a simplified encoding and decoding routines. Successive cancellation (SC) algorithm is one of the predominantly used decoding algorithms due to its low complexity. It has broad scopes for hardware architecture design and reformulation. For polar code, the trade-off among the long latency and the silicon area of the SC algorithm is a bottleneck for the design of a high throughput polar decoder. The available prior SC polar decoder designs have higher area requirements for higher block length. This paper introduces a unique reformulation of the processing element (PE) block of SC decoding. The proposed reformulation leads to two benefits: firstly, critical path and hardware complexity of the PE are meaningfully reduced by using a unified adder block. Secondly, the silicon area requirement and the power consumption were also reduced considerably without any loss in performance. The proposed PE is used to build the decoder for various block lengths. Moreover, a Gate-level analysis of the proposed decoder has revealed that the design attains an 18% area reduction and 38% reduction in power consumption over the conventional one with similar performance.
Design and Implementation of Low Power High Speed Symmetric Decoder Structure...Dr. Amarjeet Singh
The key objective of this project is to design a
decoder which can be used for hardware purposes.
Hardware, here accompanies with software which is more
we can discuss as a Software Defined Radio application. The
decoder implemented here offers to new radio equipment
(SDR), the flexibility of a programmable system. Nowadays,
the behavior of a communication system can be modified by
simply changing its software. Large tree decoder is made by
reusing smaller similar sub-modules. Thus the structure is
symmetric. The symmetric and regular structure of tree
decoder makes the system a less complexity one. The
structure obeys regularity and modularity concepts of VLSI
circuit, thus is easy to fabricate using cell library elements.
Design a Tree Decoder proposed architecture for SDR
application on FPGA. The Structures made here are
hardware synthesizable on FPGA board and are done in a
respective manner. The design to be implementing by using
Verilog-HDL language. The Simulation and Synthesis by
using Xilinx Vivado design suite.
Turbo codes are error-correcting codes with performance that is close to the
Shannon theoretical limit (SHA). The motivation for using turbo codes is
that the codes are an appealing mix of a random appearance on the channel
and a physically realizable decoding structure. The communication systems
have the problem of latency, fast switching, and reliable data transfer. The
objective of the research paper is to design and turbo encoder and decoder
hardware chip and analyze its performance. Two convolutional codes are
concatenated concurrently and detached by an interleaver or permuter in the
turbo encoder. The expected data from the channel is interpreted iteratively
using the two related decoders. The soft (probabilistic) data about an
individual bit of the decoded structure is passed in each cycle from one
elementary decoder to the next, and this information is updated regularly.
The performance of the chip is also verified using the maximum a posteriori
(MAP) method in the decoder chip. The performance of field-programmable
gate array (FPGA) hardware is evaluated using hardware and timing
parameters extracted from Xilinx ISE 14.7. The parallel concatenation offers
a better global rate for the same component code performance, and reduced
delay, low hardware complexity, and higher frequency support.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
1. The document presents a simulation of a low power analog channel decoder for error correction implemented in 65nm CMOS technology.
2. The decoder uses analog circuitry operating in the sub-threshold region to perform decoding, allowing for ultra-low power operation below 40uW for throughput up to 2.5Mbps.
3. The decoder architecture includes an analog decoding core that implements the sum-product algorithm, digital interfaces for input and output, and a digital controller to manage timing.
In this paper, a novel reduced instruction set computer (RISC)-
communication processor (RCP) has been designed with 32-bit operations
which access 64-bit instruction format and implemented using field
programmable gate array (FPGA). The design of the RISC processor is
facilitated with communication operations like basic signals sine, cosine, and
square, and modulation schemes like amplitude modulation, amplitude shift
keying, analog, and digital quadrature amplitude modulation. Additionally,
application-oriented operations like a traffic light, digital clock, and linear
feedback shift register are included in the design. The pipeline mechanism is
incorporated in the design to enhance the performance characteristics of the
processor, hence allowing the execution of the instructions more effectively.
Also, the design is implemented with Xilinx Virtex 7 family FPGA. The
device utilization analysis of the proposed FPGA along with different FPGA
families is evaluated and compared.
Communication Protocols Augmentation in VLSI Design ApplicationsIJERA Editor
With the advancement in communication System, the use of various protocols got a sharp rise in the different applications. Especially in the VLSI design for FPGAs, ASICS, CPLDs, the application areas got expanded to FPGA based technologies. Today, it has moved from commercial application to the defence sectors like missiles & aerospace controls. In this paper the use of FPGAs and its interface with various application circuits in the communication field for data (textual & visual) & control transfer is discussed. To be specific, the paper discusses the use of FPGA in various communication protocols like SPI, I2C, and TMDS in synchronous mode in Digital System Design using VHDL/Verilog.
Design and Implementation of FPGA Based Signal Processing Card VLSICS Design
This paper describes the design of FPGA based signal processing card. An on board real time digital signal processing system is designed using FPGA. The platform can decode process of various kinds of digital and analog signals simultaneously. The design trend in this card is towards small size, high integration and fast real time processing. For the optimum performance a 16 bit 1 MSPS ADC is used which is interfaced with FPGA to make all the data processing onboard in real time. This card can be used in many signal processing based applications like audio signal processing, audio compression, digital image processing, video compression, speech processing, speech recognition, digital communications by interfacing several separate board using inbuilt I/O’s, each with a number of input channels that will communicate with each other in real time over a high speed communication link. The resulting images can be displayed directly on LCD or OLED panel displays using I/O’s peripherals. The project introduces many challenging issues, which are being addressed in turn with different prototype designs. These issues are the ADC performance, interfacing the ADCs to the FPGA, implementing the flexible processing algorithms and high speed interconnection between the boards.
Research Inventy : International Journal of Engineering and Science is publis...researchinventy
This document summarizes a research paper that presents a flexible LDPC decoder design implemented on an FPGA. The decoder uses a partially parallel approach that allows it to support different code rates and block sizes. It consists of processing blocks, a message permutation block, and control logic. The processing blocks perform variable and check node operations in parallel. The message permutation block connects the blocks according to the parity check matrix. This provides flexibility to implement different codes. The control logic stores the code configuration and manages the decoding process. Simulation results showed the decoder runs at 89.29MHz on a Spartan 6 FPGA, using 765 slices and providing a better throughput to area ratio than previous designs.
Implementation of Algorithms For Multi-Channel Digital Monitoring ReceiverIOSR Journals
Abstract: Monitoring Receivers form an important constituent of the Electronic support. In Monitoring
Receiver we can monitor, demodulate or scan the multiple channels.
In this project, the Implementation of algorithm for multi channel digital monitoring receiver. The
implementation will carry out the channelization by the way of Digital down Converters (DDCs) and Digital
Base band Demodulation. The Intermediate Frequency (IF) at 10.7 MHz will be digitalized using Analog to
Digital Converter (ADC) with sampling frequency 52.5 MHz and further converted to Base band using DDCs.
Virtually all the digital receivers perform channel access using a DDC. The Base band data will be streamed to
the appropriate demodulators. Matlab Simulink will be used to simulate the logic modules before the
implementation. This system will be prototyped on an FPGA based COTS (Commercial-off-the-shelf)
development board. Xilinx System Generator will be used for the implementation of the algorithms.
Keywords: DDC, ADC, Digital Base band demodulation, IF, Monitoring Receiver.
IJCER (www.ijceronline.com) International Journal of computational Engineerin...ijceronline
This document describes an area optimized and pipelined FPGA implementation of the AES encryption and decryption algorithm. The AES algorithm is divided into four 32-bit units that are processed sequentially with a clock. This reduces the chip size compared to previous implementations that processed the full 128-bit blocks. Pipelining is used to increase throughput. The implementation is tested on a Spartan 3 FPGA using VHDL. It aims to achieve both high throughput and reduced hardware usage compared to prior designs.
IRJET- Performance Analysis of IP Over Optical CDMA System based on RD CodeIRJET Journal
This document presents a performance analysis of an IP over optical CDMA network system based on a random diagonal (RD) code. It proposes using spectral amplitude coding OCDMA to directly connect the IP layer to the optical layer, eliminating intermediate layers and reducing overhead. The system architecture, design steps, and simulation setup are described. Simulation results using OptiSystem show that bit error rate increases with the number of simultaneous users and data transmission capacity decreases with transmission distance as expected. The RD code OCDMA system provides a potential solution for next-generation networks by enabling intelligent functions and advanced services at the optical layer.
Plan_design and FPGA implement of MIMO OFDM SDM systemsTan Vo
The document describes the design and FPGA implementation of MIMO OFDM SDM systems for high speed data transmission. It discusses using MIMO and OFDM techniques together to provide increased transmission speed and spectrum efficiency. The author presents their own design of MIMO OFDM SDM systems in Matlab and implementation on an FPGA development kit. They evaluate the bit error rate performance and resource usage of their design. The document includes sections on related work, the proposed project plan and timeline, and conclusions from their implementation results.
Basic signal processing system design on fpga using lms based adaptive filtereSAT Journals
Abstract
Adaptive digital filter based on LMS algorithms widely used in the area of digital signal processing to iteratively estimate the
statistics of an unknown signal. Design of an adaptive filter is based on three major computing elements namely multiplier, adder
and delay unit torealize the Finite Impulse Response (FIR) filter. The filter weights( coefficient) of the FIR filter are adjusted
automatically by Least Mean Square of the error so as to match the adapted output to the desired input. This paper explains the
design of adaptive filter by two approaches. One is model based approach and other is Field Programmable Gate Arrays
(FPGAs). The model based design approach is developed around MATLAB, SIMULINK and SYSTEM GENERATOR tools, which
provide a virtual FPGA platform. Modern FPGA include the resources needed to design efficient filtering structures. The LMS
algorithm has been implemented on CYCLONE II EP2C35F672C8 FPGA device, using ALTERA QUARTUS II development
platform. The three major demonstrable applications cited in the present work are System Identification, Noise reduction and
Echo cancellation.
Keywords – Signal Processing; FPGA; Adaptive Filter; DE2KIT
1. The document describes a digital beamforming system based on an FPGA for phased array radar. It discusses using an FPGA to implement high-speed data sampling, storage, and multi-beam formation.
2. The system architecture involves using ADCs to convert analog signals to digital data which is sent to an FPGA via LVDS interfaces. The FPGA then packages the data using Ethernet protocols for transmission to a processing system.
3. A realization of the system is described using a Kintex-7 FPGA to sample data from 2 ADC channels at 20 MS/s and transmit the formatted data over a 1000 Mbps Ethernet network to a PC for processing.
A LIGHT WEIGHT VLSI FRAME WORK FOR HIGHT CIPHER ON FPGAIRJET Journal
This document discusses the implementation of a lightweight VLSI design for the HIGHT cipher on an FPGA. It begins with an introduction to lightweight VLSI architecture and its applications in low-resource devices. It then provides background on the HIGHT cipher and discusses prior work implementing cryptographic algorithms on FPGAs. The document goes on to describe the proposed VLSI design for the HIGHT cipher, which is optimized for size, power, and speed. It achieves a throughput of 25 Mbps with an encryption/decryption delay of 0.64 ms. Evaluation results demonstrate the effectiveness and suitability of the design for low-power applications.
FPGA based Efficient Interpolator design using DALUT Algorithmcscpconf
The document describes the design and implementation of an efficient interpolator for wireless communication systems using FPGA. It proposes a multiplier-less technique using distributed arithmetic look-up tables (DALUT) that replaces multiply-accumulate operations with LUT accesses. A 66th-order half-band polyphase FIR structure is implemented using the DALUT approach on Spartan-3E and Virtex2Pro FPGAs. Results show the proposed design achieves maximum frequencies of 92.859MHz on Virtex Pro and 61.6MHz on Spartan 3E while consuming fewer resources than a traditional MAC-based design.
FPGA based Efficient Interpolator design using DALUT Algorithmcscpconf
Interpolator is an important sampling device used for multirate filtering to
provide signal processing in wireless communication system. There are many
applications in which sampling rate must be changed. Interpolators and decimators are
utilized to increase or decrease the sampling rate. In this paper an efficient method has
been presented to implement high speed and area efficient interpolator for wireless
communication systems. A multiplier less technique is used which substitutes multiplyand-accumulate
operations with look up table (LUT) accesses. Interpolator has been
implemented using Partitioned distributed arithmetic look up table (DALUT)
technique. This technique has been used to take an optimal advantage of embedded
LUTs of the target FPGA. This method is useful to enhance the system performance in
terms of speed and area. The proposed interpolator has been designed using half band
poly phase FIR structure with Matlab, simulated with ISE, synthesized with Xilinx
Synthesis Tools (XST) and implemented on Spartan-3E and Virtex2pro device. The
proposed LUT based multiplier less approach has shown a maximum operating
frequency of 92.859 MHz with Virtex Pro and 61.6 MHz with Spartan 3E by
consuming considerably less resources to provide cost effective solution for wireless
communication systems.
High Speed Low-Power Viterbi Decoder Using Trellis Code ModulationMangaiK4
Abstract - High speed low power viterbi decoders for trellis code modulation is well known for the delay consumption in underwater communication. In transmission system wireless communication is the transfer of information between two or more points that are not connected by an electrical conductor. WiMAX is the wireless communication standard designed to provide 30 to 40 Mega bits per second data rates. WiMAX as a standards based technology enabling the delivery of last mile wireless broadband access as an alternative to cable and DSL. WiMAX can provide at home or mobile internet access across whole cities or countries. The address generation of WiMAX is carried out by interleaver and deinterleaver. Interleaving is used to overcome correlated channel noise such as burst error or fading. The interleaver/deinterleaver rearranges input data such that consecutive data are spaced apart. The interleaved memory is to improve the speed of access to memory. The viterbi technique reduces the bit error rate and delay using wimax.
Similar to IRJET - Wireless Transmission of Data using LDPC Codes based on Raspberry Pi (20)
TUNNELING IN HIMALAYAS WITH NATM METHOD: A SPECIAL REFERENCES TO SUNGAL TUNNE...IRJET Journal
1) The document discusses the Sungal Tunnel project in Jammu and Kashmir, India, which is being constructed using the New Austrian Tunneling Method (NATM).
2) NATM involves continuous monitoring during construction to adapt to changing ground conditions, and makes extensive use of shotcrete for temporary tunnel support.
3) The methodology section outlines the systematic geotechnical design process for tunnels according to Austrian guidelines, and describes the various steps of NATM tunnel construction including initial and secondary tunnel support.
STUDY THE EFFECT OF RESPONSE REDUCTION FACTOR ON RC FRAMED STRUCTUREIRJET Journal
This study examines the effect of response reduction factors (R factors) on reinforced concrete (RC) framed structures through nonlinear dynamic analysis. Three RC frame models with varying heights (4, 8, and 12 stories) were analyzed in ETABS software under different R factors ranging from 1 to 5. The results showed that displacement increased as the R factor decreased, indicating less linear behavior for lower R factors. Drift also decreased proportionally with increasing R factors from 1 to 5. Shear forces in the frames decreased with higher R factors. In general, R factors of 3 to 5 produced more satisfactory performance with less displacement and drift. The displacement variations between different building heights were consistent at different R factors. This study evaluated how R factors influence
A COMPARATIVE ANALYSIS OF RCC ELEMENT OF SLAB WITH STARK STEEL (HYSD STEEL) A...IRJET Journal
This study compares the use of Stark Steel and TMT Steel as reinforcement materials in a two-way reinforced concrete slab. Mechanical testing is conducted to determine the tensile strength, yield strength, and other properties of each material. A two-way slab design adhering to codes and standards is executed with both materials. The performance is analyzed in terms of deflection, stability under loads, and displacement. Cost analyses accounting for material, durability, maintenance, and life cycle costs are also conducted. The findings provide insights into the economic and structural implications of each material for reinforcement selection and recommendations on the most suitable material based on the analysis.
Effect of Camber and Angles of Attack on Airfoil CharacteristicsIRJET Journal
This document discusses a study analyzing the effect of camber, position of camber, and angle of attack on the aerodynamic characteristics of airfoils. Sixteen modified asymmetric NACA airfoils were analyzed using computational fluid dynamics (CFD) by varying the camber, camber position, and angle of attack. The results showed the relationship between these parameters and the lift coefficient, drag coefficient, and lift to drag ratio. This provides insight into how changes in airfoil geometry impact aerodynamic performance.
A Review on the Progress and Challenges of Aluminum-Based Metal Matrix Compos...IRJET Journal
This document reviews the progress and challenges of aluminum-based metal matrix composites (MMCs), focusing on their fabrication processes and applications. It discusses how various aluminum MMCs have been developed using reinforcements like borides, carbides, oxides, and nitrides to improve mechanical and wear properties. These composites have gained prominence for their lightweight, high-strength and corrosion resistance properties. The document also examines recent advancements in fabrication techniques for aluminum MMCs and their growing applications in industries such as aerospace and automotive. However, it notes that challenges remain around issues like improper mixing of reinforcements and reducing reinforcement agglomeration.
Dynamic Urban Transit Optimization: A Graph Neural Network Approach for Real-...IRJET Journal
This document discusses research on using graph neural networks (GNNs) for dynamic optimization of public transportation networks in real-time. GNNs represent transit networks as graphs with nodes as stops and edges as connections. The GNN model aims to optimize networks using real-time data on vehicle locations, arrival times, and passenger loads. This helps increase mobility, decrease traffic, and improve efficiency. The system continuously trains and infers to adapt to changing transit conditions, providing decision support tools. While research has focused on performance, more work is needed on security, socio-economic impacts, contextual generalization of models, continuous learning approaches, and effective real-time visualization.
Structural Analysis and Design of Multi-Storey Symmetric and Asymmetric Shape...IRJET Journal
This document summarizes a research project that aims to compare the structural performance of conventional slab and grid slab systems in multi-story buildings using ETABS software. The study will analyze both symmetric and asymmetric building models under various loading conditions. Parameters like deflections, moments, shears, and stresses will be examined to evaluate the structural effectiveness of each slab type. The results will provide insights into the comparative behavior of conventional and grid slabs to help engineers and architects select appropriate slab systems based on building layouts and design requirements.
A Review of “Seismic Response of RC Structures Having Plan and Vertical Irreg...IRJET Journal
This document summarizes and reviews a research paper on the seismic response of reinforced concrete (RC) structures with plan and vertical irregularities, with and without infill walls. It discusses how infill walls can improve or reduce the seismic performance of RC buildings, depending on factors like wall layout, height distribution, connection to the frame, and relative stiffness of walls and frames. The reviewed research paper analyzes the behavior of infill walls, effects of vertical irregularities, and seismic performance of high-rise structures under linear static and dynamic analysis. It studies response characteristics like story drift, deflection and shear. The document also provides literature on similar research investigating the effects of infill walls, soft stories, plan irregularities, and different
This document provides a review of machine learning techniques used in Advanced Driver Assistance Systems (ADAS). It begins with an abstract that summarizes key applications of machine learning in ADAS, including object detection, recognition, and decision-making. The introduction discusses the integration of machine learning in ADAS and how it is transforming vehicle safety. The literature review then examines several research papers on topics like lightweight deep learning models for object detection and lane detection models using image processing. It concludes by discussing challenges and opportunities in the field, such as improving algorithm robustness and adaptability.
Long Term Trend Analysis of Precipitation and Temperature for Asosa district,...IRJET Journal
The document analyzes temperature and precipitation trends in Asosa District, Benishangul Gumuz Region, Ethiopia from 1993 to 2022 based on data from the local meteorological station. The results show:
1) The average maximum and minimum annual temperatures have generally decreased over time, with maximum temperatures decreasing by a factor of -0.0341 and minimum by -0.0152.
2) Mann-Kendall tests found the decreasing temperature trends to be statistically significant for annual maximum temperatures but not for annual minimum temperatures.
3) Annual precipitation in Asosa District showed a statistically significant increasing trend.
The conclusions recommend development planners account for rising summer precipitation and declining temperatures in
P.E.B. Framed Structure Design and Analysis Using STAAD ProIRJET Journal
This document discusses the design and analysis of pre-engineered building (PEB) framed structures using STAAD Pro software. It provides an overview of PEBs, including that they are designed off-site with building trusses and beams produced in a factory. STAAD Pro is identified as a key tool for modeling, analyzing, and designing PEBs to ensure their performance and safety under various load scenarios. The document outlines modeling structural parts in STAAD Pro, evaluating structural reactions, assigning loads, and following international design codes and standards. In summary, STAAD Pro is used to design and analyze PEB framed structures to ensure safety and code compliance.
A Review on Innovative Fiber Integration for Enhanced Reinforcement of Concre...IRJET Journal
This document provides a review of research on innovative fiber integration methods for reinforcing concrete structures. It discusses studies that have explored using carbon fiber reinforced polymer (CFRP) composites with recycled plastic aggregates to develop more sustainable strengthening techniques. It also examines using ultra-high performance fiber reinforced concrete to improve shear strength in beams. Additional topics covered include the dynamic responses of FRP-strengthened beams under static and impact loads, and the performance of preloaded CFRP-strengthened fiber reinforced concrete beams. The review highlights the potential of fiber composites to enable more sustainable and resilient construction practices.
Survey Paper on Cloud-Based Secured Healthcare SystemIRJET Journal
This document summarizes a survey on securing patient healthcare data in cloud-based systems. It discusses using technologies like facial recognition, smart cards, and cloud computing combined with strong encryption to securely store patient data. The survey found that healthcare professionals believe digitizing patient records and storing them in a centralized cloud system would improve access during emergencies and enable more efficient care compared to paper-based systems. However, ensuring privacy and security of patient data is paramount as healthcare incorporates these digital technologies.
Review on studies and research on widening of existing concrete bridgesIRJET Journal
This document summarizes several studies that have been conducted on widening existing concrete bridges. It describes a study from China that examined load distribution factors for a bridge widened with composite steel-concrete girders. It also outlines challenges and solutions for widening a bridge in the UAE, including replacing bearings and stitching the new and existing structures. Additionally, it discusses two bridge widening projects in New Zealand that involved adding precast beams and stitching to connect structures. Finally, safety measures and challenges for strengthening a historic bridge in Switzerland under live traffic are presented.
React based fullstack edtech web applicationIRJET Journal
The document describes the architecture of an educational technology web application built using the MERN stack. It discusses the frontend developed with ReactJS, backend with NodeJS and ExpressJS, and MongoDB database. The frontend provides dynamic user interfaces, while the backend offers APIs for authentication, course management, and other functions. MongoDB enables flexible data storage. The architecture aims to provide a scalable, responsive platform for online learning.
A Comprehensive Review of Integrating IoT and Blockchain Technologies in the ...IRJET Journal
This paper proposes integrating Internet of Things (IoT) and blockchain technologies to help implement objectives of India's National Education Policy (NEP) in the education sector. The paper discusses how blockchain could be used for secure student data management, credential verification, and decentralized learning platforms. IoT devices could create smart classrooms, automate attendance tracking, and enable real-time monitoring. Blockchain would ensure integrity of exam processes and resource allocation, while smart contracts automate agreements. The paper argues this integration has potential to revolutionize education by making it more secure, transparent and efficient, in alignment with NEP goals. However, challenges like infrastructure needs, data privacy, and collaborative efforts are also discussed.
A REVIEW ON THE PERFORMANCE OF COCONUT FIBRE REINFORCED CONCRETE.IRJET Journal
This document provides a review of research on the performance of coconut fibre reinforced concrete. It summarizes several studies that tested different volume fractions and lengths of coconut fibres in concrete mixtures with varying compressive strengths. The studies found that coconut fibre improved properties like tensile strength, toughness, crack resistance, and spalling resistance compared to plain concrete. Volume fractions of 2-5% and fibre lengths of 20-50mm produced the best results. The document concludes that using a 4-5% volume fraction of coconut fibres 30-40mm in length with M30-M60 grade concrete would provide benefits based on previous research.
Optimizing Business Management Process Workflows: The Dynamic Influence of Mi...IRJET Journal
The document discusses optimizing business management processes through automation using Microsoft Power Automate and artificial intelligence. It provides an overview of Power Automate's key components and features for automating workflows across various apps and services. The document then presents several scenarios applying automation solutions to common business processes like data entry, monitoring, HR, finance, customer support, and more. It estimates the potential time and cost savings from implementing automation for each scenario. Finally, the conclusion emphasizes the transformative impact of AI and automation tools on business processes and the need for ongoing optimization.
Multistoried and Multi Bay Steel Building Frame by using Seismic DesignIRJET Journal
The document describes the seismic design of a G+5 steel building frame located in Roorkee, India according to Indian codes IS 1893-2002 and IS 800. The frame was analyzed using the equivalent static load method and response spectrum method, and its response in terms of displacements and shear forces were compared. Based on the analysis, the frame was designed as a seismic-resistant steel structure according to IS 800:2007. The software STAAD Pro was used for the analysis and design.
Cost Optimization of Construction Using Plastic Waste as a Sustainable Constr...IRJET Journal
This research paper explores using plastic waste as a sustainable and cost-effective construction material. The study focuses on manufacturing pavers and bricks using recycled plastic and partially replacing concrete with plastic alternatives. Initial results found that pavers and bricks made from recycled plastic demonstrate comparable strength and durability to traditional materials while providing environmental and cost benefits. Additionally, preliminary research indicates incorporating plastic waste as a partial concrete replacement significantly reduces construction costs without compromising structural integrity. The outcomes suggest adopting plastic waste in construction can address plastic pollution while optimizing costs, promoting more sustainable building practices.
Use PyCharm for remote debugging of WSL on a Windo cf5c162d672e4e58b4dde5d797...shadow0702a
This document serves as a comprehensive step-by-step guide on how to effectively use PyCharm for remote debugging of the Windows Subsystem for Linux (WSL) on a local Windows machine. It meticulously outlines several critical steps in the process, starting with the crucial task of enabling permissions, followed by the installation and configuration of WSL.
The guide then proceeds to explain how to set up the SSH service within the WSL environment, an integral part of the process. Alongside this, it also provides detailed instructions on how to modify the inbound rules of the Windows firewall to facilitate the process, ensuring that there are no connectivity issues that could potentially hinder the debugging process.
The document further emphasizes on the importance of checking the connection between the Windows and WSL environments, providing instructions on how to ensure that the connection is optimal and ready for remote debugging.
It also offers an in-depth guide on how to configure the WSL interpreter and files within the PyCharm environment. This is essential for ensuring that the debugging process is set up correctly and that the program can be run effectively within the WSL terminal.
Additionally, the document provides guidance on how to set up breakpoints for debugging, a fundamental aspect of the debugging process which allows the developer to stop the execution of their code at certain points and inspect their program at those stages.
Finally, the document concludes by providing a link to a reference blog. This blog offers additional information and guidance on configuring the remote Python interpreter in PyCharm, providing the reader with a well-rounded understanding of the process.
Comparative analysis between traditional aquaponics and reconstructed aquapon...bijceesjournal
The aquaponic system of planting is a method that does not require soil usage. It is a method that only needs water, fish, lava rocks (a substitute for soil), and plants. Aquaponic systems are sustainable and environmentally friendly. Its use not only helps to plant in small spaces but also helps reduce artificial chemical use and minimizes excess water use, as aquaponics consumes 90% less water than soil-based gardening. The study applied a descriptive and experimental design to assess and compare conventional and reconstructed aquaponic methods for reproducing tomatoes. The researchers created an observation checklist to determine the significant factors of the study. The study aims to determine the significant difference between traditional aquaponics and reconstructed aquaponics systems propagating tomatoes in terms of height, weight, girth, and number of fruits. The reconstructed aquaponics system’s higher growth yield results in a much more nourished crop than the traditional aquaponics system. It is superior in its number of fruits, height, weight, and girth measurement. Moreover, the reconstructed aquaponics system is proven to eliminate all the hindrances present in the traditional aquaponics system, which are overcrowding of fish, algae growth, pest problems, contaminated water, and dead fish.
Embedded machine learning-based road conditions and driving behavior monitoringIJECEIAES
Car accident rates have increased in recent years, resulting in losses in human lives, properties, and other financial costs. An embedded machine learning-based system is developed to address this critical issue. The system can monitor road conditions, detect driving patterns, and identify aggressive driving behaviors. The system is based on neural networks trained on a comprehensive dataset of driving events, driving styles, and road conditions. The system effectively detects potential risks and helps mitigate the frequency and impact of accidents. The primary goal is to ensure the safety of drivers and vehicles. Collecting data involved gathering information on three key road events: normal street and normal drive, speed bumps, circular yellow speed bumps, and three aggressive driving actions: sudden start, sudden stop, and sudden entry. The gathered data is processed and analyzed using a machine learning system designed for limited power and memory devices. The developed system resulted in 91.9% accuracy, 93.6% precision, and 92% recall. The achieved inference time on an Arduino Nano 33 BLE Sense with a 32-bit CPU running at 64 MHz is 34 ms and requires 2.6 kB peak RAM and 139.9 kB program flash memory, making it suitable for resource-constrained embedded systems.
CHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECTjpsjournal1
The rivalry between prominent international actors for dominance over Central Asia's hydrocarbon
reserves and the ancient silk trade route, along with China's diplomatic endeavours in the area, has been
referred to as the "New Great Game." This research centres on the power struggle, considering
geopolitical, geostrategic, and geoeconomic variables. Topics including trade, political hegemony, oil
politics, and conventional and nontraditional security are all explored and explained by the researcher.
Using Mackinder's Heartland, Spykman Rimland, and Hegemonic Stability theories, examines China's role
in Central Asia. This study adheres to the empirical epistemological method and has taken care of
objectivity. This study analyze primary and secondary research documents critically to elaborate role of
china’s geo economic outreach in central Asian countries and its future prospect. China is thriving in trade,
pipeline politics, and winning states, according to this study, thanks to important instruments like the
Shanghai Cooperation Organisation and the Belt and Road Economic Initiative. According to this study,
China is seeing significant success in commerce, pipeline politics, and gaining influence on other
governments. This success may be attributed to the effective utilisation of key tools such as the Shanghai
Cooperation Organisation and the Belt and Road Economic Initiative.
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsVictor Morales
K8sGPT is a tool that analyzes and diagnoses Kubernetes clusters. This presentation was used to share the requirements and dependencies to deploy K8sGPT in a local environment.
Optimizing Gradle Builds - Gradle DPE Tour Berlin 2024Sinan KOZAK
Sinan from the Delivery Hero mobile infrastructure engineering team shares a deep dive into performance acceleration with Gradle build cache optimizations. Sinan shares their journey into solving complex build-cache problems that affect Gradle builds. By understanding the challenges and solutions found in our journey, we aim to demonstrate the possibilities for faster builds. The case study reveals how overlapping outputs and cache misconfigurations led to significant increases in build times, especially as the project scaled up with numerous modules using Paparazzi tests. The journey from diagnosing to defeating cache issues offers invaluable lessons on maintaining cache integrity without sacrificing functionality.