SlideShare a Scribd company logo
Instructor
Prof. Waleed Anjum
Group
Members
• Irum Gul
• Adnan Hussain
• Abdul Khaliq
• Ahsin Yousaf
• S1F17MSCT005-
• S1F17MSCT0051
• S1F17MSCT0018
• S1F17MSCT0047
3
Register Transfer
Register
• Flip-flop is a 1 bit memory cell which can
be used for storing the digital data.
• To increase the storage capacity in terms
of number of bits, we have to use a group
of flip-flop. “Such a group of flip-flop is
known as a Register.”
5
Working
• The n-bit register will consist of n number of flip-flop and
it is capable of storing an n-bit word.
• The binary data in a register can be moved within the
register from one flip-flop to another.
• Register can be constructed with D-type flip-flop and a
common clock pulse input.
6
Working… conti…
• The clock pulse input, pulse input, CP, enables all flip
flops so that the information presently available at the four
inputs can be transferred into the 4-bits register.
• The four outputs can be sampled to obtain the information
presently stored in the register.
7
8
Types of
Register
◦ Serial Input Serial Output
◦ Serial Input Parallel Output
◦ Parallel Input Serial Output
◦ Parallel Input Parallel Output
9
SISO
• SISO stands for Serial Input Serial Output.
• Let all the flip-flop be initially in the reset
condition i.e. Q3 = Q2 = Q1 = Q0 = 0.
• If an entry of a four bit binary number 1 1 1 1 is
made into the register, this number should be
applied to Din bit with the LSB bit applied first.
• The D input of FF-3 i.e. D3 is connected to serial
data input Din.
• Output of FF-3 i.e. Q3 is connected to the input of
the next flip-flop i.e. D2 and so on.
10
11
SIPO
• SIPO stands for Serial Input Parallel Output.
• In such types of operations, the data is entered serially
and taken out in parallel fashion.
• Data is loaded bit by bit. The outputs are disabled as
long as the data is loading.
• As soon as the data loading gets completed, all the
flip-flops contain their required data, the outputs are
enabled so that all the loaded data is made available
over all the output lines at the same time.
• 4 clock cycles are required to load a four bit word.
Hence the speed of operation of SIPO mode is same
as that of SISO mode.
12
13
PISO
• Parallel Input Serial Output (PISO).
• Data bits are entered in parallel fashion.
• The circuit shown below is a four bit parallel input
serial output register.
• Output of previous Flip Flop is connected to the input
of the next one via a combinational circuit.
• The binary input word B0, B1, B2, B3 is applied
though the same combinational circuit.
• There are two modes in which this circuit can work
namely - shift mode or load mode.
14
15
PIPO
• PIPO stands for Parallel Input Parallel Output.
• In this mode, the 4 bit binary input B0, B1, B2, B3 is
applied to the data inputs D0, D1, D2, D3 respectively
of the four flip-flops.
• As soon as a negative clock edge is applied, the input
binary bits will be loaded into the flip-flops
simultaneously.
• The loaded bits will appear simultaneously to the
output side.
• Only clock pulse is essential to load all the bits.
16
17
18

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Register Dld project

  • 1.
  • 3. Group Members • Irum Gul • Adnan Hussain • Abdul Khaliq • Ahsin Yousaf • S1F17MSCT005- • S1F17MSCT0051 • S1F17MSCT0018 • S1F17MSCT0047 3
  • 5. Register • Flip-flop is a 1 bit memory cell which can be used for storing the digital data. • To increase the storage capacity in terms of number of bits, we have to use a group of flip-flop. “Such a group of flip-flop is known as a Register.” 5
  • 6. Working • The n-bit register will consist of n number of flip-flop and it is capable of storing an n-bit word. • The binary data in a register can be moved within the register from one flip-flop to another. • Register can be constructed with D-type flip-flop and a common clock pulse input. 6
  • 7. Working… conti… • The clock pulse input, pulse input, CP, enables all flip flops so that the information presently available at the four inputs can be transferred into the 4-bits register. • The four outputs can be sampled to obtain the information presently stored in the register. 7
  • 8. 8
  • 9. Types of Register ◦ Serial Input Serial Output ◦ Serial Input Parallel Output ◦ Parallel Input Serial Output ◦ Parallel Input Parallel Output 9
  • 10. SISO • SISO stands for Serial Input Serial Output. • Let all the flip-flop be initially in the reset condition i.e. Q3 = Q2 = Q1 = Q0 = 0. • If an entry of a four bit binary number 1 1 1 1 is made into the register, this number should be applied to Din bit with the LSB bit applied first. • The D input of FF-3 i.e. D3 is connected to serial data input Din. • Output of FF-3 i.e. Q3 is connected to the input of the next flip-flop i.e. D2 and so on. 10
  • 11. 11
  • 12. SIPO • SIPO stands for Serial Input Parallel Output. • In such types of operations, the data is entered serially and taken out in parallel fashion. • Data is loaded bit by bit. The outputs are disabled as long as the data is loading. • As soon as the data loading gets completed, all the flip-flops contain their required data, the outputs are enabled so that all the loaded data is made available over all the output lines at the same time. • 4 clock cycles are required to load a four bit word. Hence the speed of operation of SIPO mode is same as that of SISO mode. 12
  • 13. 13
  • 14. PISO • Parallel Input Serial Output (PISO). • Data bits are entered in parallel fashion. • The circuit shown below is a four bit parallel input serial output register. • Output of previous Flip Flop is connected to the input of the next one via a combinational circuit. • The binary input word B0, B1, B2, B3 is applied though the same combinational circuit. • There are two modes in which this circuit can work namely - shift mode or load mode. 14
  • 15. 15
  • 16. PIPO • PIPO stands for Parallel Input Parallel Output. • In this mode, the 4 bit binary input B0, B1, B2, B3 is applied to the data inputs D0, D1, D2, D3 respectively of the four flip-flops. • As soon as a negative clock edge is applied, the input binary bits will be loaded into the flip-flops simultaneously. • The loaded bits will appear simultaneously to the output side. • Only clock pulse is essential to load all the bits. 16
  • 17. 17
  • 18. 18