Independent Solar-Powered Electric Vehicle Charging Station
60928603-f15b-489b-b037-8ce97a839e8f-.pptx
1. Module 1
Ref 1: LOW-VOLTAGE, LOW-POWER VLSI SUBSYTEMS- KIAT-SENG YEO,
KAUSHIK ROY
Ref 2: LOW-POWER CMOS VLSI CIRCUIT DESIGN, KAUSHIK ROY, SHARAT
C. PRASAD
Ref 3: Low-Voltage CMOS VLSI Circuits- James V Kuo, Jea-Hong Lou
2. Need for low power circuit design, MIS Structure, Short channel
effects-surface scattering, punch through, velocity saturation,
impact ionization - Hot electron effects- Drain Induced Barrier
Lowering- Deep submicron transistor design issues.
syllabus
3.
4. ⮚Practical reasons: reduce power requirement
of high through- put , potable application
⮚ Financial reasons:- reduce packaging cost
⮚Technological reasons:- heating prevents higher-
density chips and limits functionality
⮚Environmental reasons:- green computers
Need for low power circuit design
5. Advantages of MOSFET
⮚ Ease of fabrication
⮚ Good noise margin
⮚Robust
⮚Lower switching activity
⮚Good I/O coupling
⮚Availability of matured synthesis
tools
6. MIS structure
When the insulator is an oxide layer (typically thermal oxide) then this becomes a
MOS structure
MOS
MIS
O- oxide
I- insulator
The semiconductor can be of p or n type
Ref.2
7. IN UNBIASED (V=0)
Flat band is the condition where the energy band (Ec and Ev) of the
substrate is flat at the Si–SiO2 interface
9. When V =small positive
Depletion mode
Band diagram under depletion mode
10. When V is more positive
Strong inversion
Band diagram under strong inversion
11. Short channel effects
⮚The main drives for reducing the size of the transistors, i.e.,
their lengths, is increasing speed and reducing cost
⮚When you make circuits smaller, their capacitance reduces,
thereby increasing operating speed
Short channel effects
Ref.1
12. ⮚ surface scattering
⮚ punch through
⮚ Velocity saturation
⮚ impact ionization
⮚ Hot electron effects
⮚ drain induced barrier lowering
⮚ narrow width effects
Short channel effects
13. surface scattering
⮚The velocity of the charge carriers is defined by the mobility
of that carrier times the electric field along the channel
vd =με
⮚When the carriers travel along the channel, they are
attracted to the surface by the electric field created by the
gate voltage
⮚ As a result, they keep crashing and bouncing against the
surface, during their travel, following a zig-zagging path
⮚This effectively reduces the surface mobility of the carriers,
in comparison with their bulk mobility
⮚The change in carrier mobility impacts the current-voltage
relationship of the transistor
14. As the electron travels through the channel,
it is attracted to the Si−SiO2 interface
and bounces against it. This effect reduces its mobility.
15. ⮚As the length of the channel becomes shorter, the lateral
electric field created by VDS becomes stronger.
⮚To compensate that, the vertical electric field created by
the gate voltage needs to increase proportionally, which
can be achieved by reducing the oxide thickness.
⮚As a side effect, surface scattering becomes heavier,
reducing the effective mobility in comparison with longer
channel technology nodes
16. punch through
⮚ The punch through mechanism is described as reverse bias applied to
drain, which results into extended depletion region.
⮚ The two depletion regions of drain and source therefore are intersection
with each other, and this results into "one" depletion region, and flow of
leakage current and consequently breakdown of MOSFET
⮚ The field underneath the gate then becomes strongly dependent on the
drain-source voltage, as is the drain current.
⮚ Punch through causes a rapidly increasing current with increasing
drain-source voltage.
⮚ This effect is undesirable as it increases the output conductance and
limits the maximum operating voltage of the device
17.
18. Velocity saturation
⮚The velocity of charge carriers, such as electrons or
holes, is proportional to the electric field that drives
them, but that is only valid for small fields. As the field
gets stronger, their velocity tends to saturate.
⮚That means that above a critical electric field, they tend
to stabilize their speed and eventually cannot move
faster.
⮚Velocity saturation is specially seen in short-channel
MOSFET transistors, because they have higher electric
fields.
19. As a first-order approximation, the carrier velocity is defined as
⮚ where μ is the carrier mobility, E is the electric field and Ec is the critical
electric field (the point at which the velocity tends to saturate).
⮚ The velocity saturates when
E≫Ec and it becomes
Vd = μ Ec =vsat
(when E ≪ Ec, vd=μ E as expected).
20. Impact ionization
⮚ Short-channel transistors create strong lateral electric fields, since the
distance between source and drain is very small.
⮚ This electric field endows the charge carriers with high velocity, and
therefore, high energy.
⮚ The carriers that have high enough energy to cause troubles are
called "hot" carriers
⮚ Since they are traveling through a Silicon lattice, there is a possibility that
they collide with an atom of the structure.
⮚ Given enough energy, the energy passed to the atom upon collision can
knock out an electron out of the valence band to the conduction band.
⮚ This originates an electron-hole pair: the hole is attracted to the bulk while
the generated electron moves on to the drain.
⮚ The substrate current is a good way to measure the impact ionization
effect.
21. ⮚ The generation of electron-hole pairs is very aggressive, two catastrophic
effects can happen
⮚ The parasitic bipolar transistor that is formed by the junctions between source-
bulk-drain.
⮚ This transistor is normally turned off because the bulk is biased at the lowest
voltage of the circuit.
⮚ However, when holes are flowing through the bulk, they are causing a voltage
drop at the parasitic resistance of the bulk itself.
⮚ This, in turn, can active the BJT if the base-emitter (bulk-source) voltage
exceeds 0.6-0.7 V.
⮚ With the transistor on, electrons start flowing from the source to the bulk and
drain, which can lead to even more generation of electron-hole pairs
First effects
22. ⮚ The most catastrophic case happens when the newly generated electrons
become themselves hot carriers and knock out other atoms of the lattice.
⮚ This in turn can create an avalanche effect, eventually leading to an overrun
current that the gate voltage cannot control.
23.
24. Hot Carrier Injection (HCI)
⮚ The hot carrier accelerated by the high electric field can have a different rate
as well.
⮚ The energy it contains may be sufficient to enter the oxide and get trapped
in it.
⮚ The trapped electrons alter the transistor response to the gate voltage in the
form of increased threshold voltage.
⮚ Over time, the accumulation of electrons in the oxide causes the so called
"ageing" of transistors
⮚ To reduce the formation of "hot" carriers and their negative effects, the
electric field is artificially weakened with the implantation of lightly-doped
drains, beside the heavily-doped drains
25. A "hot" electron manages to enter the oxide
and gets trapped in it.
26. Drain induced barrier lowering
⮚Any increase in drain voltage beyond it requires to establish
punch through lowers the potential barrier for the majority
carriers in the source
⮚Large no. of carriers thus come to have enough energy to
cross over and enter the substrate
⮚Some of them was collected by drain
⮚The net effect is the increases of sub threshold current
29. Sources of power dissipation in CMOS-Dynamic Power
Dissipation: Charging and Discharging capacitance power
dissipation , Short Circuit Power: Short Circuit Current of
Inverter , Short circuit current dependency with input and
output load , Glitching Power, Static Power Dissipation,
Leakage Power Dissipation, Gate level power analysis :
Capacitive, internal and Static power dissipation of gate level
circuit.
Module 2
https://youtu.be/TFOO1JAll2Y
30. Power dissipation :A critical problems ?
⮚To make the vision of the inexpensive and portable
multimedia terminal a reality
⮚ To reduce cost and volume of the cooling subsystems
31. Need to estimate power dissipation
Power dissipation affects
• Performance
• Reliability
• Packaging
• Cost
• Portability
34. MOSFET--Sources of power dissipation
(dynamic + static)
⮚ Switching power dissipation
Logic transition------
parasitic capacitance charging and discharging
⮚ Glitching power dissipation
⮚Short Circuit current
⮚Static power dissipation--leakage current dissipation---
As the supply voltage scales down---------Vth Reduces
dynamic power
Static power
Dynamic power dissipation
35. * The repeated charging and discharging of the output capacitance
is necessary to transmit information in CMOS circuits.
* This charging and discharging causes for the switched power
dissipation
.
39. ⮚ The power dissipated can be reduced by reducing either the clock frequency, or the load
capacitance, or the rail voltage. Reducing the clock frequency is the easiest thing to do, but
it seriously affects the performance of the chip
⮚ To lower the load capacitance, conscientious system design needed
⮚ Power dissipation can also be reduced by reducing the rail voltage. But this can be done
only through device technology.
40. Paulo Moreira Inverter 40
• The dynamic power dissipation is a function of:
– Frequency
– Capacitive loading
– Voltage swing
• To reduce dynamic power dissipation
– Reduce: CL
– Reduce: f
– Reduce: Vdd ⇐ The most effective action
41. Glitch Power Dissipation
⮚ Glitches are temporary changes in the value of the output – unnecessary
transitions
⮚ They are caused due to the skew in the input signals to a gate
⮚ Glitch power dissipation accounts for 15% – 20 % of the global power
⮚ Glitches are dependent on signal transitions and more glitches results in
higher power dissipation
⮚ Basic contributes of hazards to power dissipation are
⮚ Hazard generation
⮚ Hazard propagation
P = 1/2 .CL.Vdd . (Vdd – Vmin) ;
Vmin : min voltage swing at the output Glitch power dissipation is dependent on
Output load, Input pattern, Input slope
glitch is an unwanted pulse that may occur
in a circuit with a hazard.
42. ⮚ Hazard generation can be reduced by gate sizing and
path balancing techniques
⮚ Hazard propagation can be reduced by using less number
of inverters which tend to amplify and propagate glitches
44. Short Circuit Power Dissipation
• Short circuit current occurs during signal transitions when both the NMOS
and PMOS are ON and there is a direct path between Vdd and GND
• Also called crowbar current
• Accounts for more than 20% of total power dissipation
• As clock frequency increases transitions increase consequently short circuit
power dissipation increases
• Can be reduced :
– faster input and slower output
– Vdd <= Vtn + |Vtp|
• So both NMOS and PMOS are not on at the same
time
45. Short Circuit Power Consumption
in a inverter
Finite slope of the input signal causes a direct
current path between VDD and GND for a short
period of time during switching when both the
NMOS and PMOS transistors are conducting.
Vin Vout
CL
Isc
50. ⮚ Peak current determined by MOSFET saturation current, so directly proportional to
device sizes
⮚ Peak current also strong function of ratio between input and output slopes
⮚ For individual gate, minimize short circuit current by making output rise/fall time
much bigger than input rise/fall time – Slows down circuit
51. ➔ shows that this dissipation component is also proportional to the
frequency of switching, Because VDD and VT are process-
determined, the only design parameters that affect Power are
1. the input rise and fall times of the inverter.
2. Beta
53. Short-circuit current as a function of different inverter load capacitances
● The figure shows the short-circuit current behavior, during a time interval t1 –
t3, as a function of the load capacitance CL, for input rise and fall times of 5
ns.
54. ❖ Curve(1) shows the behavior of the inverter without load. At any time this
current is the maximum short-circuit current that can occur. This means that
all other current characteristics for different load capacitances must be
within this curve. Curve (4) shows the short-circuit current behavior of the
inverter when it is loaded with a characteristic capacitance CL of 500 fF. In
this case the rise and fall times on the output node are equal to the rise and
fall times on the input.
57. ● The dashed line shows the dynamic dissipation (~= 10 MHz), while the
solid lines show the actual inverter dissipation (dynamic plus short-circuit
dissipation). T
From these characteristics we can conclude that if the operation of the inverter is
such that the output signal and input signal have equal rise and fall times, the
short-circuit dissipation will be only a fraction ( <20 percent) of the total
dissipation. However, if the inverter is more lightly loaded, causing output rise and
fall times that are relatively short as compared to the input rise and fall times, then
the short-circuit dissipation will increase to the same order of magnitude as the
dynamic dissipation. Therefore, to minimize dissipation, an inverter used as part of
a buffer should be designed in such a way that the input rise and fall times are less
than or about equal to the output rise and fall times in order to guarantee a
relatively small short-circuit dissipation.
58. Static power dissipation
Consider the complementary CMOS gate
⮚ where Ileakage is the leakage current that
flows between VDD and ground in the
absence of switching activity.
⮚ The leakage current of the CMOS inverter
is equal to zero in ideal case, since the
pMOS and nMOS devices never ON
simultaneously in steady state operation.
⮚ But the leakage current is flowing
through the reverse biased diode junctions
of the transistors located between sources
or drain and substrate.
⮚ This contribution of current is very small
and can be neglected.
62. Why Leakage Power Reduction?
Dynamic Power Dissipation is given By
Static Power Dissipation is given by(Leakage power dissipation
)
In fig It is shows V th has to decrease in order
to get high performance
When Vth <0.1v ,leakage power Domination
63. Component --SOURCES OF LEAKAGE
POWER
1.p-n junction reverse bias current
2. weak inversion
3. Gate oxide leakage
4. Gate current due to hot carrier
5. GIDL
6. Channel current punch through
Transistor leakage mechanisms of deep submicron transistors
64.
65. ⮚I1 is the reverse bias pn junction leakage;
⮚I2 is the subthreshold leakage;
⮚I3 is the oxide tunneling current;
⮚I4 is the gate current due to hot carrier injection
⮚I5 is the Gate Induced Drain Leakage (GIDL)
⮚I6 is the channel punch through current.
⮚Currents I2,I5, I6 are off-state leakage mechanisms while I1
and I3 occur in both ON and OFF states.
⮚I4 can occur in the off-state, but more typically occurs during
the transistor bias states in transition
66.
67. PN Junction Reverse Bias Current (I1)
Drain and source to well junctions are typically reverse biased
causing pn junction leakage current
A reverse bias pn junction leakage (I1) has two main
components:
1.minority carrier diffusion/drift near the edge of the depletion
region
2.is due to electron hole pair generation in the depletion
region of the reverse biased junction
● Function of : Junction area, doping concentration , strongly
depends on temperature
68. Sub threshold Leakage (I2)
⮚When gate voltage is below Vth
The weak inversion current is given by
m- sub threshold swing coeiffient
Ref 1: LOW-VOLTAGE, LOW-POWER VLSI SUBSYTEMS- KIAT-SENG YEO, KAUSHIK ROY
71. The inverse of the slope of the log10(Ids) versus Vgs
characteristic called the sub threshold slope
72. Tunneling in to and through gate oxide
Gate oxide tunneling current -----
As Tox Eox
⮚ electron tunneling from substrate to gate
⮚ from gate to substrate
I3
73. Tunneling into and through gate oxide
Electron tunneling through
the
MOS capacitor
a. Energy band at flatland condition
b. Energy band at positive
gate showing tunneling of electron
from
substrate to gate.
c. Energy band diagram at negative
bias
showing tunneling of electron from
gate to
substrate
75. Fowler-Nordheim tunneling
⮚ e tunnels through a triangular potential barrier
⮚ conduction band of oxide layer
⮚Valid Vox> φox
Vox -oxide voltage
drop
For short channel
Vox <
φox
Thus negligible
81. Mechanisms of direct tunneling
NMOS
ECB
EVB
ECB-electron
conduction band
EVB-electron
valance band
1.Gate to
channel current
in inversion
2.Gate to body
tunneling in
accumulation
Gate to body tunneling
in
depletion-inversion
83. Component of gate tunneling
current
Igso and Igdo –parasitic leakage current(due to
overlap )
Igb-substrate leakage current
Igc-inverted channel current
84. (I4)-Injection of hot carrier
⮚As feature size decreases , Electric field in channel region
increases which leads to gain high kinetic energy by holes &
electron (Hot carrier)
⮚E or holes can gain sufficient energy to cross the interface
potential barrier and enter in to oxide field
⮚The energy of the hot carriers depends mainly on the
electric field in the pinch-off region
⮚ Hot-carrier injection is one of the mechanisms that
adversely affects the reliability of semiconductors of solid-
state devices
85. Different type of Hot carrier Injection
• Drain Avalanche Hot carrier (DAHC) Injection
• Channel Hot Electron (CHE) Injection
• Substrate Hot Electron (SHE) Injection
• Secondary generated hot electron (SGHE) injection
86. Drain Avalanche Hot carrier (DAHC) Injection
• When VD>VG , the
acceleration of channel
carrier causes Impact
Ionization .
• The generated electron –
holes pair gain energy to
break the barrier in Si-
SiO2 interface
87. Channel Hot Electron (CHE) Injection
• When both VG & VD very
higher than source
voltage , some electrons
driven towards gate oxide
.
88. Substrate Hot Electron (SHE) Injection
• Occurs when the substrate
back bias is very positive or
very negative
• Carriers of one type in the
substrate are driven by the
substrate field toward the Si-
SiO2 interface.
• Gain high kinetic energy from
and injected to SiO2.
89. GIDL
⮚ due to high field in the drain junction
⮚Accumulation ------------Si surface has the same
potential as the p-substrate
⮚ surface with more heavily doped than
substrate
⮚ surface depletion layer is more narrower
Field crowding effects
Field near drain increased
1.
I5
90. When Vgs is Vds-=VDD
&
Field crowding
effects
2.
⮚Result-minority carriers get emitted in the
drain region underneath the gate
⮚Swept to the substrate
91. I6-punch through
● In SCE if the doping is constant ,the separation between
depletion region of drain and source decreases
● With increase in VDS ,causes the boundaries nearer to
each other
● Thus depletion region merge each other
92. Punch Through
• Electrons can flow from source to drain (no
more back to back junctions) (n-channel
enhancement mode)
• ID α VD
2
• Drain current no longer controlled by gate
• Transistors won’t “turn off”
93. ⮚In long channel devices, the sub threshold current is independent
of the drain voltage for VDS larger than few vT
⮚ The threshold voltage and consequently the sub threshold
current of short channel devices vary with the drain bias
DIBL
Occurs at higher drain ,lower Leff
DIBL
94. A .long channel mosfets
b. Short channel mosfets
c. Short channel with high
drain bias
104. Gate level power analysis : Capacitive, internal and Static power dissipation of
gate level circuit
● Most efforts to controlling power dissipation of digital circuits
to be focused on hardware design
● hardware is the physical means by which power is converted
into useful computation
● It would be unwise to ignore the influence of software on
power dissipation
● Circuit simulators such as SPICE attain excellent accuracy but
cannot be applied to full chip analysis.
Software power dissipation
105. ➔ The designer start with a simulation at the hardware behavior
level to obtain an initial power dissipation estimate
➔ When the gate gate-level design is available, a gate level
simulation is performed to refine the initial estimate
➔ If the initial estimate turns out to be inaccurate and the design
fails the specification, the design is modified and verified again
➔ The iteration continues until the gate level estimate is within
specification
➔ The design is then taken to the transistor or circuit level
analysis to further verify the gate level estimates
➔ The refinement and verification steps continue until the
completion of the design process, when the chip is suitable for
mass production
106. Gate-level Logic Simulation
➔ Simulation based gate level timing analysis has been a very
mature technique in today’s VLSI design
➔ component abstraction at this level is logic gates and nets
➔ Today, many gate-level logic simulators are available, most
of which can perform full-chip simulation up to several million
gates
107. The most popular gate-level analysis is based on the so called
event-driven logic simulation. Events are zero-one logic
switching of nets in a circuit at a particular simulation time point
108. Capacitive Power Dissipation
❖ The basic principle of Gate level power analysis tools is to
perform a logic simulation of the gate level circuit to obtain
the switching activity information
❖ The information is then used to derive the power
dissipation of the circuit
● The capacitive power dissipation of the circuit is 𝑃𝑐𝑎𝑝 =
∑ 𝐶𝑖𝑉 2 𝑛𝑒𝑡 𝑖 𝑓𝑖 .
109. Internal Switching Energy
● The dynamic power dissipation inside the logic cell is called
the internal power, which consists of short circuit power and
charging or discharging of internal nodes
110. Static State Power
● The leakage power is primarily determined by the sub threshold and
reverse biased leakage of MOS transistors
111. Power Reduction Techniques :Supply voltage Scaling Approaches: Multi VDD and
Dynamic VDD, leakage power reduction Techniques – Transistor stacking,
VTCMOS,MTCMOS, DTCMOS, Power gating, Clock gating for Dynamic power
dissipation, Transistor and Gate Sizing for Dynamic and Leakage Power Reduction.
Module 3
Ref. 1. James B. Kuo, Jea-Hong Lou, Low-Voltage CMOS VLSI Circuits-Wiley-
Interscience (1999)
Ref 2: LOW-VOLTAGE, LOW-POWER VLSI SUBSYTEMS- KIAT-SENG YEO,
KAUSHIK ROY
Ref3. low-power cmos vlsi circuit design- KAUSHIK ROY
112. Supply Voltage Reduction Strategy
➔ lowering supply voltage offers many tradeoffs
➔ Depending on applications, there are two strategies in the reduction of supply voltage—high
performance and low power approaches
➔ high-performance approach, lowering supply voltage is targeted to raise system reliability—the
electromigration reliability, the hot-carrier reliability, the oxide stress reliability, and other
reliabilities related to high electric field and temperature.
113. ● high- performance approach, power supply voltage is not scaled
down aggressively, Instead, under the scaled supply voltage,
circuit performance is optimized
● low-power approach, it is for mobile systems, which emphasize
lengthening battery life
● The degraded performance of the circuits at a reduced supply
voltage can be compensated by using advanced technology
● can also be made up by adopting system parallelism and
pipelining
114. ➔ When gate length is shrunk, threshold voltage cannot be scaled down
accordingly due to subthreshold leakage consideration
➔ At a reduced supply voltage, downscaling of devices may lead to degradation of
the device performance
In the industry, a relationship between minimum supply voltage and minimum
threshold voltage has been found
minimum supply voltage is set to about three times the minimum threshold
voltage
115. ❖ the minimum supply voltage can be determined by the minimum threshold
voltage voltage. The minimum threshold voltage is determined by three factors:
❖ threshold voltage variation due to process fluctuation, (2) threshold voltage
variation due to temperature effect, and (3) on-off current ratio of the device.
116. Why Leakage Power Reduction?
Dynamic Power Dissipation is
given By
Static Power Dissipation is given by(Leakage power
dissipation )
⮚ In fig It is shows Vth has to decrease in order
to get high performance
When Vth < 0.1v ,leakage power Domination
For low voltage, supply voltage reduce, so as
to Vth also
117. Techniques to reduce Leakage
Power
⮚Transistor Stack (Self reverse bias )
⮚Multiple Vth Techniques
⮚Dynamic Vth Technique
⮚Supply Voltage Scaling Technique
⮚Leakage reduction techniques for
cache(SRAM)
Ref 1: LOW-VOLTAGE, LOW-POWER VLSI SUBSYTEMS- KIAT-SENG YEO,
KAUSHIK ROY
118. 1.Transistor Stack (Self reverse bias )
⮚ Stacking Effect- Sub threshold leakage current flowing through
a stack of series connected transistors reduces when more than
one transistor of the stack is turned off.
Consider a two input NAND gate
119. ⮚ The leakage of a two-transistor stack is an order of magnitude
less than the leakage in a single transistor
⮚Due to Stacking effect -------------- subthreshlod current
depends on ---------input vector
⮚ Due to the positive source potential VM, gate to source voltage (VGS1) of
transistor M1 becomes negative; hence, the sub-threshold current reduces
substantially.
⮚ Due to VM > 0, body to source potential (VBS1) of transistor M1 becomes
negative, which results in an increase in the threshold voltage (larger body effect)
of M1, and thus reducing the sub-threshold leakage.
⮚ Due to VM> 0, the drain to source potential (VDS1) of transistor M1 decreases,
which results in an increase in the threshold voltage (less DIBL) of M1, and thus
reducing the sub-threshold leakage.
120. 2.Multiple Vth Technique
⮚ both high and low Vth transistors with in a
single chip
high Vth
Suppress the sub
threshold leakage current
low
Vth
High
performance
121. s
It can achieved by
1.Multiple Channel doping
2.Mutilple oxide CMOS (MOXCMOS)
3.Mutiple Channel Length
4.Multiple body bias
5.Multithreshold –voltage CMOS (MTCMOS)
6.Dual threshold CMOS
7.Variable Threshold CMOS(VTMOS)
8.Dynamic Threshold CMOS (DTMOS)double gate
9. Double gate Dynamic threshold SOI CMOS (DGDT-
MOS)
122. Multi threshold –voltage CMOS(MTCMOS)
Inserting high threshold devices in
series into low V th circuitry
123. Variable Threshold CMOS(VTMOS)
⮚ To achieve different threshold voltages ,a self
–substrate bias circuit is used to control body
bias
⮚ active mode-no body bias
⮚Stand-by mode –deeper reverse bias is
applied
Variable threshold
CMOS
124. Dynamic Threshold CMOS (DTMOS)double gate
⮚Achieved by tying the gate and body
together
.
DTMOS inverter
High Vth ----standby mode
–low leakage current
Low Vth--- higher current –
active mode
⮚ Suitable for ultra –low voltage circuits(0.6v or below)
126. 9. Double gate Dynamic threshold SOI CMOS
(DGDT-MOS
Advantages of -------DTMOS+ double
gate fully depleted SOI MOSFETs
DGDT SOI MOSFET
structure
Back gate
oxide is thick
127. Dynamic Vth
technique
⮚ It utilizes dynamic adjustment of frequency through
back-gate bias control depending on the workload of a
system
1.Vth –Hopping Scheme 2.Dyamnic Vth
Scaling Scheme(DVTS)
