This document analyzes and compares the power consumption of different adiabatic logic circuits implemented in 45nm technology, including ECRL, PFAL, and 2N-2N2P. Combinational circuits like NAND, NOR, XOR, and 2:1 multiplexer were designed using these techniques in Cadence Virtuoso. Simulation results found that PFAL was the most energy efficient at mid-frequencies, while ECRL had the lowest energy consumption overall. However, adiabatic logic circuits use more transistors than equivalent CMOS designs.

1. Proceedings of the International Conference on Emerging Trends in Engineering and Management (ICETEM14)
30 – 31, December 2014, Ernakulam, India
230
POWER EVALUATION OF ADIABATIC LOGIC
CIRCUITS IN 45NM TECHNOLOGY
Simranjeet Singh Puaar1
, Sandeep Singh Gill2
1, 2
(ECE, Guru Nanak Dev Engineering College, Ludhiana, India)
ABSTRACT
Adiabatic logic technique can become an answer to the problem of power dissipation. This technique is capable
of recycling the energy from the load and sends it back to the power supply. In this paper various adiabatic logic
techniques like Efficient Charge Recovery Logic (ECRL), Positive Feedback Adiabatic Logic (PFAL), 2N-2N2P are
analyzed. Combinational circuits like Nand, Nor, Exor, 2:1Mux are implemented using above mentioned techniques.
Effect of frequency on energy consumption is analyzed and compared with the results of standard CMOS. Energy saving
factor (ESF) of all above said adiabatic techniques is determined at 1 MHz . After analysis it was found out that PFAL is
most efficient. Design and simulations is done using CADENCE VIRTUOSO tool, in 45nm technology node.
Keywords: Cadence Virtuoso, ECRL, ESF, PFAL, 2N-2N2P.
1. INTRODUCTION
CMOS device is fast moving towards pinnacle of miniaturization, thus causing the increase in sophistication of
applications in embedded computing. Interest of the researchers has grown towards reducing energy dissipation as cost of
power dissipation has become derisory. Results obtained using custom low power techniques are sometimes inadequate
hence different concepts of physics are being explored to optimize the power equation. Adiabatic logic technique is one
such concept. In this paper various combinational circuits are implemented using semi adiabatic ECRL[1], PFAL[2][3],
2N-2N2P[3] techniques and comparison is made with traditional CMOS.
2. ADIABATIC PROCESS
Adiabatic literally is a thermodynamic process which involves no energy exchange with the surrounding thus no
loss of energy due to dissipation but in microelectronics charge transfer between nodes of a circuit is considered as a
process.Basic rules for adiabatic circuits:
1. Never turn on a transistor if it has a non zero voltage across it because it will cause ½ CVDD
2
dissipation.
2. Never suddenly change voltage across any On transistor [4].
Where C is a load capacitance and VDD is maximum amplitude of applied voltage. To satisfy above rules
adiabatic switching is used. Adiabatic switching is technique which causes the nodes to charge/discharge at constant
current to minimize energy dissipation.Adiabatic Switching requires Constant current source power supply [5]. For
adiabatic switching trapezoidal power supply voltage is used.
INTERNATIONAL JOURNAL OF ELECTRONICS AND
COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)
ISSN 0976 – 6464(Print)
ISSN 0976 – 6472(Online)
Volume 5, Issue 12, December (2014), pp. 230-237
© IAEME: http://www.iaeme.com/IJECET.asp
Journal Impact Factor (2014): 7.2836 (Calculated by GISI)
www.jifactor.com
IJECET
© I A E M E

2. Proceedings of the International Conference on Emerging Trends in Engineering and Management (ICETEM14)
30 – 31, December 2014, Ernakulam, India
231
2.1 Power clock
Trapezoidal voltage is used as a power clock which acts as a constant current source power supply. Power clock
has four intervals, these are Evaluate(E), Hold(H), Recovery(R), Wait(W). In E interval, the outputs are evaluated from
the stable input signal. During H interval, output is kept stable to provide input to next stage. Energy is recovered during
R interval and W interval is added for the purpose of symmetry as shown in the fig. 1.
Fig.1: One cycle of power clock used in adiabatic logic
2.2 Lossmechanism in adiabatic logic
Adiabatic logic energy loss (EAL), Leakage loss (Eleak) and Non-adiabatic loss (Enon-adia) are the losses that occur
in adiabatic circuits as shown in Fig. 2 [6].
Fig. 2: Variation in energy of adiabatic logics with frequency [6]
From the graph it can be seen that EAL increases with frequency, Eleak is inversely proportional to frequency and
Enon-adia is independent of the frequency. Thus for adiabatic circuit consumption at low frequency high due to
leakage.power. consumption decreases as frequency increases and is minimum at a particular frequency and it start
increasing after wards basically due to EAL[6].
2.3 Energy saving factor
It is measure for how much more energy is consumed in a static CMOS gate or system with respect to an
Adiabatic Logic counterpart [6]. General definition for ESF is given by (1).
ESF =
∑ ୉ి౉ో౏
∑ ୉ఽై
(1)
3. CIRCUIT IMPLEMENTATION
Nand, Nor, Exor and 2:1Mux are the combinational circuits that are implemented using semi adiabatic ECRL,
PFAL, 2N-2N2P techniques. Implementation is done using cadence virtuoso 45nm technology node. Supply voltage
applied to run the circuits is trapezoidal in nature which has maximum amplitude of 1.8V. Length of both the MOS

3. Proceedings of the International Conference on Emerging Trends in Engineering and Management (ICETEM14)
30 – 31, December 2014, Ernakulam, India
232
devices is kept at minimum value i.e. 45 nm. Width of NMOS is set to 120nm and that of PMOS is set to 240nm. Load
capacitance value is set to 1pf considering the fact that as gate width is decreased parasitic capacitance increases.
3.1 ECRL
This adiabatic logic family has same structure as cascode voltage switch logic. This structure has two cross
coupled PMOS devices that are used to provide complementary out. The latch is driven by nMOS network that could be
viewed as a complementary switching block.Combinational circuits implemented using ECRL are shown in Fig. 3.
Fig. 3: ECRL Implementation of a) Nand gate b) Nor gate c) Exor gate d) 2:1 Mux
3.2 PFAL
In case of PFAL, latch is a combination of two pMOSFETs and two nMOSFETs, and the functional tree is
connected in parallel with the pMOSFETs.As functional tree is parallel withpMOSFETs it causes the reduction of
equivalent resistance of the charging path of the capacitor. During the recovery phase,the loaded capacitance gives back
energy to the power supply , thus reducing overall power consumption [7].Combinational circuits implemented using
PFAL are shown inFig 4.

4. Proceedings of the International Conference on Emerging Trends in Engineering and Management (ICETEM14)
30 – 31, December 2014, Ernakulam, India
233
Fig. 4 PFAL Implementation of a) Nand gate b) Nor gate c) Exor gate d) 2:1 Mux
3.3 2N-2N2P
This logic family is derived from ECRL to reduce coupling effect that was a drawback of ECRL.In case of 2N-
2N2P latch is a combination of two pMOSFETs and two nMOSFETs, and the functional tree is connected in parallel
with the nMOSFETs. These cross coupled nMOS's result's in non-floating output as shown in Fig. 5.

5. Proceedings of the International Conference on Emerging Trends in Engineering and Management (ICETEM14)
30 – 31, December 2014, Ernakulam, India
234
Fig. 5: 2N-2N2P Implementation of a) Nand gate b) Nor gate c) Exor gate d) 2:1 Mux
4. RESULTS AND DISCUSSIONS
In this section effect of frequency on energy consumption is analyzed and compared with the results of standard
CMOS. Energy saving factor (ESF) of all above said adiabatic techniques is determined at 1 MHz's Moreover different
techniques compared for area consumed.

6. Proceedings of the International Conference on Emerging Trends in Engineering and Management (ICETEM14)
30 – 31, December 2014, Ernakulam, India
235
4.1 Effect of frequency on energy consumption
Amount of energy consumed by adiabatic circuit depends upon frequency of operation. Effect of frequency on
various adiabatic combinational circuits is analyzed. Analysis is tabulated in Table 1 to Table 4 and shown graphically in
Fig.6.Results shown below indicate that at low frequencies energy consumption increases for both CMOS and adiabatic
techniques due to leakage current that flows in transistors. From above it is seen that energy consumption is minimum in
ECRL and maximum in PFAL. As frequency of operation is increased energy consumption decreases and is minimum at
about 10 KHz. For mid frequency ranges PFAL is most efficient technique and all are better than standard CMOS. As
frequency of operation increases energy consumption stars increasing in all the three techniques. At higher frequencies at
about 10MHz, behaviour of adiabatic families remain no longer adiabatic, thus energy consumption of adiabatic logic
devices increases whereas for CMOS it is independent of frequency.
Table 1: Energy consumption of Nand at different frequencies
Table 2: Energy consumption of Nor at different frequencies
Table 3: Energy consumption of Exor at different frequencies
Frequency
CMOS
Energy
(p j)
ECRL
Energy
(p j)
PFAL
Energy
(p j)
2N-2N2P
Energy
(p j)
100 Hz 8.787 4.81 13.634 8.86
1 KHz 5.291 .712 1.427 1.10
10 KHz 4.89 .465 .316 .5056
100 KHz 4.92 .724 .333 .7286
1 MHz 4.93 1.503 .800 1.504
10 MHz 4.93 5.824 3.87 5.824
Frequency
CMOS
Energy
(p j)
ECRL
Energy
(p j)
PFAL
Energy
(p j)
2N-2N2P
Energy
(p j)
100 Hz 8.630 4.87 13.34 8.946
1 KHz 5.301 .720 1.430 1.111
10 KHz 4.97 .466 .312 .5085
100 KHz 4.94 .724 .333 .7295
1 MHz 4.92 1.509 .797 1.5113
10 MHz 4.82 5.729 3.7 5.810
Frequency
CMOS
Energy
(pj)
ECRL
Energy
(p j)
PFAL Energy
(p j)
2N-2N2P
Energy
(p j)
100 Hz 7.421 5.14 17.04 8.877
1 KHz 3.69 .786 1.786 1.173
10 KHz 3.33 .562 .346 .599
100 KHz 3.28 .900 .347 .905
1 MHz 3.28 1.85 .870 1.861
10 MHz 3.27 7.386 4.67 7.53

7. Proceedings of the International Conference on Emerging Trends in Engineering and Management (ICETEM14)
30 – 31, December 2014, Ernakulam, India
236
Table 4: Energy consumption of 2:1 mux at different frequencies
Fig.6: Energy consumption comparison of a) Nand gate b) Nor gate c) Exor gate d) 2:1 Mux
4.2 Transistor count
Main disadvantage of adiabatic technique is transistor count. No of transistors used, are greater than
corresponding CMOS device.Transistor used are maximum for PFAL and 2N-2N2P and minimum for traditional CMOS.
Table 5 shows transistor count comparison.
Table 5: Number of transistors used to form a circuit
Frequency
CMOS
Energy
(p j)
ECRL
Energy
(p j)
PFAL
Energy
(p j)
2N-2N2P
Energy
(p j)
100 Hz 21.70 10.07 30.85 17.71
1 KHz 12.47 1.582 3.29 2.359
10 KHz 9.911 1.151 .7 1.229
100 KHz 9.845 1.861 .749 1.870
1 MHz 9.811 3.815 1.857 3.828
10 MHz 9.800 14.805 9.889 15.367
Circuit CMOS ECRL PFAL 2N-2N2P
Nand 4 6 8 8
Nor 4 6 8 8
Exor 8 10 12 12
2:1Mux 8 10 12 12

8. Proceedings of the International Conference on Emerging Trends in Engineering and Management (ICETEM14)
30 – 31, December 2014, Ernakulam, India
237
4.3 Energy saving factor
Table 6 shows the ESF of various adiabatic families for different combinational circuits calculated at 1MHz.
From table it can be seen that PFAL has best energy saving factor i.e. PFAL is most efficient.
Table 6: Energy saving factor
5. CONCLUSION
It is concluded from above that energy consumption at lower frequencies is minimum in case of ECRL
followed by CMOS, 2N2N2P and PFAL i.e. leakage losses are minimum in ECRL. As frequency of operation increases
energy consumption starts decreasing. It is minimum at about 10 KHz. At 10KHz and above PFAL is most efficient
adiabatic logic technique followed by 2N2N2P and ECRL. At 10MHz and above process remains no longer adiabatic as
a result energy consumption of all three adiabatic techniques becomes greater than CMOS. Frequency of operation of
adiabatic logic could be increased to few hundred of MHz if load capacitance is reduced. Area consumption of adiabatic
logic is greater than standard CMOS which is its main disadvantage. Thus its applications are limited, for example a pace
maker where energy saving is main target.
REFERENCES
[1] Y.Moon, and D. K.Jeong, “An Efficient Charge Recovery Logic Circuit”, IEEE Journal of Solid-State Circuits,
31(4), 1996 , 514-522.
[2] A.Vetuli,S. D.Pascoli, and L. M. Reyneri, “Positive Feedback in Adiabatic Logic”, IEEE Electronics letters,
32(20), 1996, 1867-1869.
[3] E.Amirante,A. B. Stoffi, andJ.Fischer, "Variation of power dissipation in adiabatic logic gates", Institute for
Technical Electronics, Technical University Munich.
[4] A.Schlaffer and J. A. Nossek, “Is there a connection between adiabatic switching and reversible
computing?”,Institute for Network Theory and Circuit Design, Munich University of Technology.
[5] W. C.Athas, L.Svensson,J. G. Koller,N.Tzartzanis, andE. Y. Chou, “Low-Power Digital Systems Based on
Adiabatic-Switching Principles”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2(4), 1994,
398-407.
[6] P.Teichmann, Adiabatic Logic(Springer series in advanced Microelectronics, 34, 2012)
[7] A. Blotti, S.Di Pascoli, and R.Saletti, "Simple Model for Positive Feedback Adiabatic Logic Power Consumption
Estimation", IEEE Electronics letters, 36(2), 2000, 116-118.
[8] Praveer Saxena, Swati Dhamani, Dinesh Chandra and Sampath Kumar V, “Modified Two Phase Drive Adiabatic
Dynamic CMOS Logic”, International Journal of Electronics and Communication Engineering & Technology
(IJECET), Volume 3, Issue 2, 2012, pp. 141 - 147, ISSN Print: 0976- 6464, ISSN Online: 0976 –6472.
Circuit ECRL PFAL 2N-2N2P
Nand 3.28 6.16 3.277
Nor 3.26 6.17 3.255
Exor 1.77 3.77 1.762
2:1 Mux 2.571 5.283 2.562