The document proposes and evaluates energy recovery flip-flops that operate with a single-phase sinusoidal clock to reduce power consumption. A resonant clock generator is designed to produce the sinusoidal clock signal. Simulations show the proposed flip-flops achieve over 80% delay reduction and 47% power reduction compared to conventional designs. An H-tree clock network distributes the sinusoidal clock signal. Total power savings of up to 80% are achieved compared to square wave clocking schemes. Clock gating is also proposed to further reduce power when the flip-flops are inactive.
Power and Clock Gating Modelling in Coarse Grained Reconfigurable SystemsMDC_UNICA
Power reduction is one of the biggest challenges in modern systems and tends to become a severe issue dealing with complex scenarios. To provide high-performance and exibility, designers often opt for coarse-grained recongurable (CGR) systems. Nevertheless, these systems require specic attention to the power problem, since large set of resources may be underutilized while computing a certain task.
This paper focuses on this issue. Targeting CGR devices, we propose a way to model in advance power and clock gating costs on the basis of the functional, technological and architectural parameters of the baseline CGR system. The
proposed flow guides designers towards optimal implementations, saving designer eort and time.
FPGA IMPLEMENTATION OF UNIVERSAL SHIFT REGISTER FOR ASYNCHRONOUS DATA SAMPLINGEditor IJMTER
Now a days power consumption plays a vital role in vlsi circuits. The growing market of
mobiles, battery-powered electronic devices demands the design of electronic circuits with low
power consumption.To design a low power circuit, energy efficiency from the clock element is an
important issue.There are different technique for the energy efficiency. One technique for efficiency
is the use of double edge-triggered flip-flops (DETFFs), since they can maintain the same throughput
as single edge-triggered flip-flops (SETFFs) while only using half of the clock frequency. Doubleedge triggered (DET) flip-flops are bistable flip-flop circuits in which data is latched at either edge of
the clock signal. Using such flip-flops permits the rate of data processing to be preserved while using
lower clock. Therefore, power consumption in DETFF based circuit may be reduced. The DETFF
designs provide the best performance not only in power but also in speed. Clock gating is another
well-accepted technique to reduce the dynamic power of idle modules or idle cycles, like the power
wasted by timing components during the time when the system is idle. Clock gating means disabling
the clock signal when the input data does not alter the stored data. However, incorporating clock
gating with DETFFs to further reduce dynamic power consumption introduces an asynchronous data
sampling (i.e., a change in output between clock edges). In this paper are discussing two different
methods to avoid asynchronous data sampling and implement this using universal shift register.
With the rise of containerization, as well as the established adoption of virtualization technologies, run-time power and energy management is becoming one of the key challenges in modern cloud computing. This is also fundamental as power consumption contributes to the 20% of the Total Cost of Ownership of a datacenter and energy costs will exceed hardware costs in the near future. In this context, several goals towards power optimization can be achieved. On the one hand, power capping can be enforced and on top of that the system should be able to maximize performance. On the other hand, when performance are critical, the system should be able to provide a minimum SLA and optimize power consumption without violating it. Within this context, we propose a common autonomic methodology based on the ODA control loop for containers and virtual machines. The proposed methodology is able to achieve 25% power savings for containers and can improve performance under a power cap for virtual machines.
Power and Clock Gating Modelling in Coarse Grained Reconfigurable SystemsMDC_UNICA
Power reduction is one of the biggest challenges in modern systems and tends to become a severe issue dealing with complex scenarios. To provide high-performance and exibility, designers often opt for coarse-grained recongurable (CGR) systems. Nevertheless, these systems require specic attention to the power problem, since large set of resources may be underutilized while computing a certain task.
This paper focuses on this issue. Targeting CGR devices, we propose a way to model in advance power and clock gating costs on the basis of the functional, technological and architectural parameters of the baseline CGR system. The
proposed flow guides designers towards optimal implementations, saving designer eort and time.
FPGA IMPLEMENTATION OF UNIVERSAL SHIFT REGISTER FOR ASYNCHRONOUS DATA SAMPLINGEditor IJMTER
Now a days power consumption plays a vital role in vlsi circuits. The growing market of
mobiles, battery-powered electronic devices demands the design of electronic circuits with low
power consumption.To design a low power circuit, energy efficiency from the clock element is an
important issue.There are different technique for the energy efficiency. One technique for efficiency
is the use of double edge-triggered flip-flops (DETFFs), since they can maintain the same throughput
as single edge-triggered flip-flops (SETFFs) while only using half of the clock frequency. Doubleedge triggered (DET) flip-flops are bistable flip-flop circuits in which data is latched at either edge of
the clock signal. Using such flip-flops permits the rate of data processing to be preserved while using
lower clock. Therefore, power consumption in DETFF based circuit may be reduced. The DETFF
designs provide the best performance not only in power but also in speed. Clock gating is another
well-accepted technique to reduce the dynamic power of idle modules or idle cycles, like the power
wasted by timing components during the time when the system is idle. Clock gating means disabling
the clock signal when the input data does not alter the stored data. However, incorporating clock
gating with DETFFs to further reduce dynamic power consumption introduces an asynchronous data
sampling (i.e., a change in output between clock edges). In this paper are discussing two different
methods to avoid asynchronous data sampling and implement this using universal shift register.
With the rise of containerization, as well as the established adoption of virtualization technologies, run-time power and energy management is becoming one of the key challenges in modern cloud computing. This is also fundamental as power consumption contributes to the 20% of the Total Cost of Ownership of a datacenter and energy costs will exceed hardware costs in the near future. In this context, several goals towards power optimization can be achieved. On the one hand, power capping can be enforced and on top of that the system should be able to maximize performance. On the other hand, when performance are critical, the system should be able to provide a minimum SLA and optimize power consumption without violating it. Within this context, we propose a common autonomic methodology based on the ODA control loop for containers and virtual machines. The proposed methodology is able to achieve 25% power savings for containers and can improve performance under a power cap for virtual machines.
Lecture 2: Electrical load demand analysis and management Eyad Adnan
Lecture 2: Electrical load demand analysis and management ;
.. Estimate and Review Load & energy demand assessment
... determine the figure of demand daily kwh consumption for specific building/customers
... Establish Work Plan to Get daily KWH
......Optimizing energy consumption by using potentials for opportunities conservation tools and measures
Slides from the June 6, 2016, webinar on Advanced WEC Dynamics and Controls, hosted by Sandia National Laboratories for the US Department of Energy. SAND2016-5473 PE
Profit based unit commitment for GENCOs using Parallel PSO in a distributed c...IDES Editor
In the deregulated electricity market, each
generating company has to maximize its own profit by
committing suitable generation schedule termed as profit
based unit commitment (PBUC). This article proposes a
Parallel Particle Swarm Optimization (PPSO) solution to the
PBUC problem. This method has better convergence
characteristics in obtaining optimum solution. The proposed
approach uses a cluster of computers performing parallel
operations in a distributed environment for obtaining the
PBUC solution. The time complexity and the solution quality
with respect to the number of processors in the cluster are
thoroughly tested. The method has been applied to 10 unit
system and the results show that the proposed PPSO in a
distributed cluster constantly outperforms the other methods
which are available in the literature.
This chapter will focus on the optimization and security of a power system. basically it will focus on economic dispatch analysis without considering transmission line losses.
The transformation of a fixed speed wind turbine to a variable
speed topology through the installation of an autonomous
conversion system enables to maximize the Return
on Investment (RoI) of the wind turbine.
Voltage stability Analysis using GridCalAnmol Dwivedi
Power system voltage stability is characterized as being capable of maintaining load voltage magnitudes within specified operating limits under steady state conditions. This presentation deals with the modeling of two standard power systems test cases i.e the Nordic-32 and the Nordic-68, comparing the power flows results obtained from GridCal against PSS/E, finding the respective P-V curves for the two test cases using the continuation power flow under contingencies, and finally proposing a graph-based test statistic which can be used for an imminent voltage instability. The simulations are carried out using an open-source power system software called GridCal and the scripts for this project are written in python.
Lecture 2: Electrical load demand analysis and management Eyad Adnan
Lecture 2: Electrical load demand analysis and management ;
.. Estimate and Review Load & energy demand assessment
... determine the figure of demand daily kwh consumption for specific building/customers
... Establish Work Plan to Get daily KWH
......Optimizing energy consumption by using potentials for opportunities conservation tools and measures
Slides from the June 6, 2016, webinar on Advanced WEC Dynamics and Controls, hosted by Sandia National Laboratories for the US Department of Energy. SAND2016-5473 PE
Profit based unit commitment for GENCOs using Parallel PSO in a distributed c...IDES Editor
In the deregulated electricity market, each
generating company has to maximize its own profit by
committing suitable generation schedule termed as profit
based unit commitment (PBUC). This article proposes a
Parallel Particle Swarm Optimization (PPSO) solution to the
PBUC problem. This method has better convergence
characteristics in obtaining optimum solution. The proposed
approach uses a cluster of computers performing parallel
operations in a distributed environment for obtaining the
PBUC solution. The time complexity and the solution quality
with respect to the number of processors in the cluster are
thoroughly tested. The method has been applied to 10 unit
system and the results show that the proposed PPSO in a
distributed cluster constantly outperforms the other methods
which are available in the literature.
This chapter will focus on the optimization and security of a power system. basically it will focus on economic dispatch analysis without considering transmission line losses.
The transformation of a fixed speed wind turbine to a variable
speed topology through the installation of an autonomous
conversion system enables to maximize the Return
on Investment (RoI) of the wind turbine.
Voltage stability Analysis using GridCalAnmol Dwivedi
Power system voltage stability is characterized as being capable of maintaining load voltage magnitudes within specified operating limits under steady state conditions. This presentation deals with the modeling of two standard power systems test cases i.e the Nordic-32 and the Nordic-68, comparing the power flows results obtained from GridCal against PSS/E, finding the respective P-V curves for the two test cases using the continuation power flow under contingencies, and finally proposing a graph-based test statistic which can be used for an imminent voltage instability. The simulations are carried out using an open-source power system software called GridCal and the scripts for this project are written in python.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
An Efficient Execution of Clock Gating Technique for Logic CircuitsIJTET Journal
Clock gating has been heavily used in reducing the power consumption of the clock network by limiting its activity factor. Fundamentally, clock gating reduces the dynamic power dissipation by disconnecting the clock from an unused circuit block. This result in three major components of power consumption: power consumed by combinational logic whose values are changing on each clock edge; power consumed by flip-flops; power consumed by the clock tree in the design. Here clock gating approach is done for various logic circuits in response to examine its application.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
Performance Comparison of Various Clock Gating Techniquesiosrjce
Clock signal have been a great source of power dissipation in synchronous circuits because of high
frequency and load. So , by using clock gating one can save power by reducing unnecessary switching activity
inside the gated module. Here four gating methods are discussed and their power dissipation is compared. The
most popular is synthesis-based, deriving clock enabling signals based on the logic of the underlying system. It
unfortunately leaves the majority of the clock pulses driving the flip flops (FFs) redundant. A data driven
method stops most of those and yields higher power savings, but its implementation is complex and application
dependent. A third method called auto gated FFs (AGFF) is simple but yields relatively small power savings.
Another novel method called Look Ahead Clock Gating (LACG) is presented, which combines all the three.It
avoids the tight timing constraints of AGFF and data driven by allotting a full clock cycle for the computation of
the enabling signals and their propagation.
Energy Consumption Saving in Embedded Microprocessors Using Hardware Accelera...TELKOMNIKA JOURNAL
This paper deals with the reduction of power consumption in embedded microprocessors.
Computing power and energy efficiency are becoming the main challenges for embedded system
applications. This is, in particular, the caseof wearable systems. When the power supply is provided by
batteries, an important requirement for these systems is the long service life. This work investigates a
method for the reduction of microprocessor energy consumption, based on the use of hardware
accelerators. Their use allows to reduce the execution time and to decrease the clock frequency, so
reducing the power consumption. In order to provide experimental results, authors analyze a case of study
in the field of wearable devices for the processing of ECG signals. The experimental results show that the
use of hardware accelerator significantly reduces the power consumption.
Dynamic Power Reduction of Digital Circuits by ClockGatingIJERA Editor
In this paper we have presented clock gating process for low power VLSI (very large scale integration) circuit design. Clock gating is one of the most quite often used systems in RTL to shrink dynamic power consumption without affecting the performance of the design. One process involves inserting gating requisites in the RTL, which the synthesis tool translates to clock gating cells in the clock-path of a register bank. This helps to diminish the switching activity on the clock network, thereby decreasing dynamic power consumption within the design. Due to the fact the translation accomplished via the synthesis tool is solely combinational; it is referred to as combinational clock gating. This transformation does not alter the behavior of the register being gated.
In today’s modern electronics industries energy or power efficiency is most important feature to increase the speed, portability, reliability, popularity and efficiency of electronic products. Reduction in power consumption or low power requirement for a system adds features of low cost, high speed, more efficiency and reliability. CMOS technology is a popular name in the field of low power systems. In the field of CMOS technology various methods are used to make the systems more power efficient like, use of Sleepy transistors, Stack method in which transistor length or width is increased to get reduction in leakage power, use of pre-computation technique with the use of BDD (Binary Decision Diagram), use of SRAM (Static Random Access Memory) for high speed operations. In this paper we survey low power systems in which various techniques are used to reduce the power consumption in different circuit areas of the system to get more power efficient and cost effective electronic systems.
Control Scheme for an IPM Synchronous Generator Based-Variable Speed Wind Tur...IJMTST Journal
This paper proposes a control strategy for an IPM synchronous generator-based variable speed wind turbine this control technique is simple and has many advantages over indirect vector control technique as in this scheme, the requirement of the continuous rotor position is eliminated as all the calculations are done in the stator reference frame and can eliminate some of the drawbacks of traditional indirect vector control scheme. This scheme possesses advantages such as lesser parameter dependence and reduced number of controllers compared with the traditional indirect vector control scheme Furthermore, the system is unaffected to variation in parameters because stator resistance is the only required criteria. This control technique is implemented in MATLAB/Sim power systems and the simulation results shows that this suggested control technique works well and can operate under constant and varying wind speeds. Finally, a sensorless speed estimator is implemented, which enables the wind turbine to operate without the mechanical speed sensor.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and development of grid tie inverter with closed loop spwm single stag...eSAT Journals
Abstract The project aims the devise topology of single stage, three switch, closed loop SPWM control photovoltaic inverter for grid tie residential application. Predictable buck-boost GTI used in photovoltaic application are of manifold stage inverter systems, encompass dc-ac-dc converters added to achieve a raised dc voltage before inversion. Additional stage require more power machinery and also more power loss results, Even though a two-stage buck-boost inverter can reach significantly high power capability, which introduces circuit density as well as adds up the cost. In disparity with existing system project proposes the intend of a three-switch single stage grid connected buck-boost inverter, where switching losses to a great extent reduced as number of switches and also flyback, buck boost function principles are applied to match up with solar energy accessibility variation. For switching power circuit blend of square wave and SPWM is used, with kind of combination switching frequency reduces to such a level where switching losses significantly reduced. To realize Grid synchronization Strategy sine wave beginning from grid will be used as orientation signal for SPWM. To regulate inverter immediate ac output closed loop control scheme is engaged. Implementation of simple controller format with which output is stabilized as fast as probable. Advantages of this method are established by simulation of a grid-connected single-stage three switch, closed loop SPWM buck-boost inverter.. Keywords: GTI, Buck-Boost, SPWM, and Square wave etc…
Adiabatic describe the thermodynamic processes in which there is no energy exchange with the environment, and therefore very less dissipated energy loss. These circuits are low power circuits which use reversible logic to conserve energy. Adiabatic logic works with the concept of switching activities which reduces the power by giving stored energy back to the supply. The main design changes are focused on power clock which plays the vital role in the principle of operation. This has been used because many adiabaticcircuits use a combined power supply and clock, or a power clock (Four Phase).To achieve this, the power supply of adiabatic logic circuits have used time varying voltage charging signal, in contrast to traditional non-adiabatic systems that have generally used constant voltage charging from a fixed-voltage power supply. Thereby the circuit topology and operation of the circuit has been changed so that the source current of CMOS transistor change its direction and goes back to the supply(Recovery) when the power clock falls from VDD to zero. Power efficient blocks can be designed by using adiabatic logic which can be used in combinational and sequential circuits. The simulation of the designs is done using a backend tool called MENTOR GRAPHICS in 130nm technology
DESIGN AND IMPLEMENTATION OF AREA AND POWER OPTIMISED NOVEL SCANFLOPVLSICS Design
The power consumption of IC during test mode is higher than its normal mode. This brings the power as one of the major design constraints for today’s low power design technologies. In normal scan based test circuits most of the power consumed due to the switching activity of scanflops during shift and capture cycles. In this paper a novel scanflop is presented which reduces the switching activity of the scanflop for clock and it reduces the power consumption of the circuit and it also reduces area and test time too. The proposed Dual Mode One Latch Double Edge Triggered (DMOL-DET) scanflop which shift the two bits of test vector in a clock cycle, during its test mode and captures the single data in a clock cycle during its data mode. The design and functionality of the proposed scanflop is discussed and compared with the different flipflops which shows that the proposed scan flop reduces the test time and clock switching activity by 50%, area by 30% and static power by 25%.
DESIGN AND IMPLEMENTATION OF LOW POWER ALU USING CLOCK GATING AND CARRY SELEC...IAEME Publication
CPUs in general-purpose personal computers, such as desktops and laptops, dissipate significantly more power in the order of few watts because of their higher complexity and speed. ALU is a fundamental building block of CPU. It does all process related to arithmetic and logic operations. As the operations become more complex, the ALU become more complex, more expensive, takes up more space in the CPU and contributes more power dissipation within the CPU. Hence power consumption of ALU is a major issue in the designing of CPU.
Duty Cycle Corrector Using Pulse Width ModulationVLSICS Design
In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is done with respect to clock signals. It uses the edges of the clock to sample the data. So, it becomes very much necessary to see to it that the clock signals are properly received specially in receiver circuits where data sampling is done, mainly in Double data rate(DDR) circuits. Due to effects such as jitter, skew, interference, device mismatches etc., duty cycle gets affected. We come up with duty cycle correctors that ensure 50% duty cycle of the clock signals. A duty cycle corrector (DCC) with analog feedback is proposed and simulated in 45nm process technology node. The duty cycle corrector operates for MHz frequency range covering the duty cycle from 35%-65%, with +/- 1.5% accuracy. The design is simple and the power consumption is 1.01mW.
International Journal of VLSI design & Communication Systems (VLSICS) VLSICS Design
In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is done with respect to clock signals. It uses the edges of the clock to sample the data. So, it becomes very much necessary to see to it that the clock signals are properly received specially in receiver circuits where data sampling is done, mainly in Double data rate(DDR) circuits. Due to effects such as jitter, skew, interference, device mismatches etc., duty cycle gets affected. We come up with duty cycle correctors that ensure 50% duty cycle of the clock signals. A duty cycle corrector (DCC) with analog feedback is proposed and simulated in 45nm process technology node. The duty cycle corrector operates for MHz frequency range covering the duty cycle from 35%-65%, with +/- 1.5% accuracy. The design is simple and the power consumption is 1.01mW.
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
DevOps and Testing slides at DASA ConnectKari Kakkonen
My and Rik Marselis slides at 30.5.2024 DASA Connect conference. We discuss about what is testing, then what is agile testing and finally what is Testing in DevOps. Finally we had lovely workshop with the participants trying to find out different ways to think about quality and testing in different parts of the DevOps infinity loop.
Alt. GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using ...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
Enhancing Performance with Globus and the Science DMZGlobus
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Elevating Tactical DDD Patterns Through Object CalisthenicsDorra BARTAGUIZ
After immersing yourself in the blue book and its red counterpart, attending DDD-focused conferences, and applying tactical patterns, you're left with a crucial question: How do I ensure my design is effective? Tactical patterns within Domain-Driven Design (DDD) serve as guiding principles for creating clear and manageable domain models. However, achieving success with these patterns requires additional guidance. Interestingly, we've observed that a set of constraints initially designed for training purposes remarkably aligns with effective pattern implementation, offering a more ‘mechanical’ approach. Let's explore together how Object Calisthenics can elevate the design of your tactical DDD patterns, offering concrete help for those venturing into DDD for the first time!
SAP Sapphire 2024 - ASUG301 building better apps with SAP Fiori.pdfPeter Spielvogel
Building better applications for business users with SAP Fiori.
• What is SAP Fiori and why it matters to you
• How a better user experience drives measurable business benefits
• How to get started with SAP Fiori today
• How SAP Fiori elements accelerates application development
• How SAP Build Code includes SAP Fiori tools and other generative artificial intelligence capabilities
• How SAP Fiori paves the way for using AI in SAP apps
Le nuove frontiere dell'AI nell'RPA con UiPath Autopilot™UiPathCommunity
In questo evento online gratuito, organizzato dalla Community Italiana di UiPath, potrai esplorare le nuove funzionalità di Autopilot, il tool che integra l'Intelligenza Artificiale nei processi di sviluppo e utilizzo delle Automazioni.
📕 Vedremo insieme alcuni esempi dell'utilizzo di Autopilot in diversi tool della Suite UiPath:
Autopilot per Studio Web
Autopilot per Studio
Autopilot per Apps
Clipboard AI
GenAI applicata alla Document Understanding
👨🏫👨💻 Speakers:
Stefano Negro, UiPath MVPx3, RPA Tech Lead @ BSP Consultant
Flavio Martinelli, UiPath MVP 2023, Technical Account Manager @UiPath
Andrei Tasca, RPA Solutions Team Lead @NTT Data
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024Albert Hoitingh
In this session I delve into the encryption technology used in Microsoft 365 and Microsoft Purview. Including the concepts of Customer Key and Double Key Encryption.
The Art of the Pitch: WordPress Relationships and SalesLaura Byrne
Clients don’t know what they don’t know. What web solutions are right for them? How does WordPress come into the picture? How do you make sure you understand scope and timeline? What do you do if sometime changes?
All these questions and more will be explored as we talk about matching clients’ needs with what your agency offers without pulling teeth or pulling your hair out. Practical tips, and strategies for successful relationship building that leads to closing the deal.
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf91mobiles
91mobiles recently conducted a Smart TV Buyer Insights Survey in which we asked over 3,000 respondents about the TV they own, aspects they look at on a new TV, and their TV buying preferences.
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf
G352734
1. Mashkoor Alam et al. Int. Journal of Engineering Research and Application www.ijera.com
Vol. 3, Issue 5, Sep-Oct 2013, pp.27-34
www.ijera.com 27 | P a g e
A Noble Design of Energy Recovery Flip-Flops
Mashkoor Alam1
and Rajendra Prasad2
1, 2
Department of Electronics & Telecommunication Engineering, KIIT University Bhubaneswar
Abstract
The power consumption of the clock tree dominates over 40% of the total power in high performance VLSI
designs. Hence, low power clocking schemes are promising approaches for low power design. We propose
energy recovery clocked flip-flops that enable energy recovery from the clock network, resulting in significant
energy savings. These flip-flops operate with a single-phase sinusoidal clock which can be generating with high
efficiency. In Cadence 180nm CMOS technology, we implemented these energy recovery clocked flip flops
through an H tree clock network driven by a resonant clock generator to generate a sinusoidal clock. The
proposed flip-flops exhibit more than 80% delay reduction, 47% power reduction, as compared to the
conventional energy recovery flip-flop. Simulation results show a power reduction of 90% on the clock tree and
total power saving of up to 80% as compared to the conventional square wave clocking schemes and flip flops.
In this paper, we also propose clock gating solution for the energy recovery clocked flip flops reduces their
power and delay. A pipelined array multiplier is designed which show a total power savings of 25%-69% as
compared to the same multiplier using conventional square wave clocking scheme and corresponding flip-flops.
I. Introduction
Flip flops are ubiquitous element in CMOS
circuits based designs which make the major portion
of the synchronous circuits. As results, the structure of
flip flop used in circuits has a large impact on system
power consumption. However, the type of flip flop
used to determines the amount of clock load, which
directly affects dynamic power consumption Pdyn of
circuits.
Thus, it is prudent to come up with
techniques to reduce the power consumption of flip
flops to reduce the overall system power consumption
[2]. Also the power dissipated in clock distribution
network is 30% to 60% of the total system power. As
the power budget of today’s portable digital circuit is
severely limited, it is important to reduce the power
dissipation in the flip flop.
Timing elements, latches and flip-flops, are
critical for the performance of digital systems because
of the tight timing constraints and requirements of low
power [3]. Short set up time and hold time are also
required for performance, but often overlooked. In a
complex system it is very often necessary to have the
ability to scan the data in and out during the test and
diagnostic process.
Energy recovery is a technique for low power
digital circuits [6]. Energy recover circuits achieve
low energy dissipation by restricting current to flow
across devices with low voltage drop and by recycling
the energy stored on the capacitors by using an
oscillating supply voltage. In this paper, we apply
energy recovery techniques to the clock network since
the clock signal is most capacitive signal. The
proposed energy recovery clocking scheme recycles
the energy from the capacitance in each cycle of the
clock. For an efficient clock generation, we use a
sinusoidal clock signal.
In this paper, we proposed high performance
and low power energy recovery flip flop that operate
with a single phase sinusoidal clock. The proposed flip
flops reduction in delay and power as compared to the
conventional four phase transmission gate energy
recovery flip flop. The energy recovery clocked flip
flops are clocked through an H-tree clocking network.
A resonant clock generator circuit was designed to
generate a sinusoidal clock and drive the clock
network and flip flops. We implemented the same
clock tree using square wave clocked flip- flops.
Clock gating is another popular technique for
reducing clock power [7]. Even though energy
recovery clocking results in substantial reduction in
clock power, there still remains some energy loss on
the clock network due to resistance of the clock
network and the energy loss in the oscillator itself due
to non adiabatic switching. In this paper, we propose
clock gating solutions for the energy recovery clock.
We modify the design of the existing energy recovery
clocked flip-flops to incorporate a power saving
feature that eliminates any energy loss on the internal
clock and other nodes of the flip flops. Applying the
proposed clock gating technique to the flip-flips
reduces their power by a substantial amount 1000
times during the sleep mode. However, the added
feature has negligible power and delay overhead when
flip-flops are in the active mode.
For high performance is increase the clock frequency
with the technology scaling. But in deep sub
micrometer generation’s higher performance is
obtained by parallelism in the architecture level [4].
Deeply pipelined systems exhibit inherent parallelism
that requires higher fan out at the register outputs.
RESEARCH ARTICLE OPEN ACCESS
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These impacts the requirements for higher flip flops
driving strengths. The impact of the clock skew on the
minimum cycle time increases in deep sub micrometer
designs as the clock skew does not follow the
technology scaling. Thus the ability to absorb the
clock skew without impact on setup time becomes
important. The amount of cycle time taken out by the
flip flop consists of the sum of setup time and clock to
output delay [5]. Therefore, the true measure of the
flip flop delay is the time between the latest point of
data arrival and corresponding output transition.
The remainder of this paper is organized as
follows. In section 2, include system integration the
energy recovery clock generation and clock-tree
implementation. In section 3, the proposed energy
recovery clocked flip-flops are described. In section 4,
extensive simulation results of individual flip-flops
and their comparisons are presented. In section 5, the
clock gating approaches are proposed for energy
recovery clocked flip-flops. In section 6, includes the
design of an energy recovery clocked pipelined
multiplier. Finally, the conclusion of this paper in
section 7.
II. Energy Recovery Clock Generator
The energy recovery clock generator is a
single phase resonant clock generator as shown in
figure 1. Transistor M1 receives a reference pulse to
pull-down the clock signal to ground when clock
reaches its minimum, thereby maintaining the
oscillation of the resonant circuit. This transistor is
large transistor, and driven by a chain of progressively
sized inverters. The oscillation frequency of this
resonant clock is determined by
.......................... 1
Fig 1(a): Resonant energy recovery clock generator
(b) Non-energy recovery clock driver
Where C is the total capacitance connected to
the clock tree including parasitic capacitances of the
clock tree and gate capacitances with clock inputs of
flip flops. The frequency of reference signal is same as
the oscillation frequency of the resonant circuit. Find
the value of C. first with a given L and with the REF
signal at zero, the whole system, including the flip
flops are simulated. The clock signal shows a
decaying oscillating waveform settling down to Vdd/2.
From this waveform, the natural decaying frequencies
are measured, and then by using equation 1, the value
of C is calculated. The system consisting of the energy
recovery clock generator, and flip flops are simulated
at the frequency of 250 MHz with different data
switching activities.
Fig. 2 Output Waveform of Energy Recovery Clock
Generator
III. Energy Recovery Flip-Flops and
Proposed Energy Recovery Flip-Flops
3.1 Differential Conditional Capturing
Energy Recovery Flip-Flops
Differential amplifier circuits accept small
input small signals are amplify them to generate small
rail to rail swings [8]. They are used extensively in
memory core and in low swing bus drivers to either
improve performance or reduce power dissipation.
The energy recovery clock is applied to a
minimum sized inverter skewed for fast high to low
transition. Such skewing creates a sharp high to low
transition on CLKB to ensure correct timing for the
flip flop operation. The minimum sizing of inverter
reduces its short circuit power caused by slow rising
of the input clock. The clock signals CLK and inverter
output CLKB is applied to transistors MN1 and MN2.
The series combination of these transistors conduct for
a short period of time during the rising transition of
the clock when both the CLK and CLKB signals have
voltage above the threshold voltage of the NMOS
transistors. Since the clock inverter is skewed for fast
high to low transitions, the conducting period occurs
only during the rising transitions of the clock, but not
on the falling transition. In this way, conducting pulse
is generated during the rising transition of the clock. A
cascade of three inverters instead of one can give a
slightly sharper falling edge for the inverted clock
CLKB. However, due to slow rising nature of energy
recovery clock, enough delay can be generated by a
single inverter.
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Fig.3 Differential Conditional Capturing Energy
Recovery Flip Flop
The above figure 3 show the Differential
Conditional Capturing Energy Recovery flip flops. It
is a dynamic flip flop because it operates in a
precharge and evaluate phase occurs. However,
instead of using the clock for precharging, small pull-
up PMOS transistors MP1 and MP2 are used for
charging the precharge nodes. The DCCER flip flop
uses a NAND based SET or RESET latch for the
storage mechanism. The conditional capturing is
implemented by using feedback from the output to the
control NMOS transistors MN3 and MN4 in the
evaluation paths. Therefore, if the state of the input
data D and DB is same as that of the output Q and QB,
both left and right evaluation paths are turned off
preventing SET and RESET from being discharged.
This results in power saving at low data switching
activities when input data remains idle for more than
one clock cycle.
3.2 Proposed Work of Differential Energy
Recovery Flip-Flops
Fig.4 Proposed Differential Conditional Capturing
Energy Recovery Flip Flop
The above figure 4 shows my proposed
Differential Conditional Capturing Energy Recovery
Flip Flop. This is also dynamic flip flop. The
Transistors MN3 and MN4 are removed. This flips
flop uses also a NAND based SET or RESET latch for
mechanism. Therefore, the input of data D and DB are
same as that of the output Q and QB. This results in
power saving at low data switching activities when
input data remains idle for more than one clock cycle.
The size of DCCER flip flop is smaller and faster than
previous DCCER flip flop.
Fig.5 The output Waveform of DCCER Flip Flop
As can be seen in waveform of DCCER flip
flop and proposed DCCER flip flop, CLK signal is
generally less than Vdd/2 during a significant part of
the conducting window. Therefore, a large transistor is
used for MN1. However, since there are four stacked
transistors in the evaluation path, significant charge
sharing may occur when three of them become ON
simultaneously. Sized pull up PMOS transistors MP1
and MP2 instead of clock controlled precharge
transistors ensures a constant path to Vdd which helps
to reduce the effect of charge sharing. Another
property of the circuit that helps reduce charge sharing
is that clock transistor MN1, which is largest the
transistor in the evaluation path, is placed at the
bottom of the stack. Therefore, the diffusion
capacitance of the source terminal of MN1 is
grounded and does not contribute to the charge
sharing.
3.2 Single Ended Conditional Capturing
Energy Recovery Flip-Flops
The above figure 6 shows a Single Ended
Conditional Capturing Energy Recovery flip flop.
SCCER is a single ended version of the DCCER flip
flop. The transistor MN3 controlled by the output QB,
provides conditional capturing. The right hand side
evaluation path is static and does not require
conditional capturing. Placing MN3 above MN4 in the
stack reduces the charge sharing.
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Fig.6 Single Ended Conditional Capturing Energy
Recovery Flip Flop
3.4 Proposed Work of Single Ended Conditional
Capturing Energy Recovery Flip-Flops
Fig. 7 Proposed of Single Ended Conditional
Capturing Energy Recovery Flip Flop
The above figure 7 shows my proposed
Single Ended Conditional Capturing Energy Recovery
Flip Flop. The PMOS MP1 is directly connected to the
energy recovery clock signal and Transistor MN3 is
removed. When the clock voltage exceeds the
threshold voltage of the clock transistor MN1
evaluation occurs. At the onset of the evaluation, the
difference between the data inputs D and DB results in
an initial small voltage difference is then amplified by
the cross coupled inverter. When the clock voltage fall
below Vdd-Vtp, then PMOS transistor MP1 are
precharge. Therefore, if the state of the input data D
and DB are same as that of the output Q and QB. The
energy is recovered from the clock input capacitance
of transistor MN1 and MP1 by applying a sinusoidal
clock generated using a resonant clock generator.
These results in the power saving at low data
switching activities when input data remain idle for
more than one clock cycle.
Fig. 8 the waveform of Single Ended Conditional
Capturing Energy Recovery Flip Flop
IV. Simulation Results and Comparisions
All the flip flops are simulated using 180nm
process technology with a supply voltage of 1.8V in
Cadence Virtuoso tool. Netlists were extracted from
schematic and simulated using ADEL. However, since
the FPTG flip-flop is a dual-edge triggered flip-flop, it
was designed to operate at a clock frequency of
250MHz. Figure 9 illustrates our timing definition.
Delay is measured between 50% points of signal
transitions. Setup time is a time from when data
becomes stable to the rising transition of the clock.
Hold time is the time from the rising transition of the
clock to the earliest time that data may change after
being sampled.
Fig. 9 Waveform of trimming definition
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Table1. Summary of Numerical Results of Flip-Flops with 250 MHz Sinusoidal Clock
Flip Flop D-Q
delay(ps)
Setup
Time(ps)
Hold
Time(ps)
Clk-Q
delay(ps)
Power
(µW)
PDP*
(fJ) No. of
Transistor
Area
(µm2
)
FPTG 2350 -130 830 2470 455.7 1070.9 16 236.7
DCCER 405 143 175 190 225.5 91.33 18 150
Proposed DCCER 390 125 160 176.3 209.8 81.82 16 136.9
SCCER 325 280 45 150.4 185.5 60.29 17 210.5
Proposed SCCER 310 255 15 123.5 160.7 49.81 16 196.8
* Power is for long setup time; Power Delay Product (PDP) is the product of Power and D-Q delay
Table2. Summary of Power Consumption of Flip-
Flops with different Input
Flip Flop Square Wave
Clock Power
(µW)
Energy Recovery
Clock Power
(µW)
Percentage
of Power
Reduction
DCCER 415.7 225.5 45.75
Proposed
DCCER
395.6 209.8 46.96
SCCER 359.5 185.5 48.4
Proposed
SCCER
315.7 160.7 49.0
The proposed flip flops are compared with
previous flip flop. For individual flip flop
simulations, an ideal sinusoidal clock are used. It is
apparent that the delays of the FPTG flip-flop are
much larger as compared to the proposed flip-flops.
The energy recovery clock shows the lowest power
with all flip flops compared to square wave and sine
wave clock. In order to compared with the square
wave clocking.
The energy recovery systems show less
power consumption as compared to the square wave
clocking. The energy recovery clocking scheme
reduces the power due to the clock distribution by
more than 90% compared to non energy recovery
clocking.
Table 3 Power Dissipated on Clock Tree
Flip-
Flops
Clock
Tree
Power
(mW)
Clock
Tree
Capacitor
(pF)
Clock
Power/
Load
(mW/pF)
Percenta
ge of
Energy
Recovery
FPTG 52.51 42.01 1.25 0
DCCER 3.096 46.83 0.066 94.7
Proposed
DCCER
2.976 45.97 0.065 94.3
SCCER 2.894 44.68 0.065 94.8
Proposed
SCCER
2.763 43.57 0.064 94.7
The numerical results of the power
dissipated on the clock tree in each system and the
percentage of energy recovered from the clock
network of the energy recovery clocked flip-flops.
The clock tree capacitance shown includes the wiring
capacitance of the clock network and gate
capacitance shown by the flip-flop clock inputs.
V. Energy Recovery Clock Gating
Technique
The clock power in idle periods can be
reduced by the application of clock gating technique
to the energy recovery clock. In this section, we
propose technique for applying clock gating to the
energy recovery clocking system in order to obtained
additional power savings in the idle mode The energy
recovery clocked flip flops cannot save power during
sleep mode if the clock is still running. There are two
components of power dissipation inside flip flops:
internal clock circuit power (power of logic gates
connected to the clock) and the remaining circuit
power (power of the rest of the flip flop circuit). We
separated the clock circuit power from the remaining
circuit power in our power measurements. Disabling
the clock circuit in the idle state can eliminate both
the clock circuit and remaining circuit power. Hence,
disabling of the inverter gates is the proposed
approach to implementing clock gating inside energy
recovery clocked flip flop. This can be done by
replacing the inverter gate with a NOR gate as shown
in fig.10.
The NOR gate has two inputs: the clock signal
and the enable signal. In active mode, the enable
signal is low so the NOR gate behaves just like an
inverter and flip flop operates just like the original
flip flop. In the idle state, the enable signal is set to
high which disables the internal clock by setting the
output of the NOR gate to be zero. Figure 10 shows
the circuit diagram and its output waveform.
Fig.10 Clock Gating DCCER Flip Flop
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Fig.11 Proposed Clock Gating DCCER Flip Flop
Fig.12 Waveform of Clock Gating Flip-Flops
Fig. 13 Clock Gating of SCCER Flip Flop
Fig. 14 Clock Gating of Proposed SCCER Flip Flop
Fig. 15 Waveform of Clock Gating Flip Flop
Table4. Power Consumed by Flip Flop with Active
Mode
Original Flip Flop in
Active Mode
Flip Flop with Clock
gating in Active Mode
Flip
Flop
Rema
ining
Circu
it
Powe
r
(µW)
Interna
l Clock
Power
(µW)
Tota
l
Pow
er
(µW
)
Rema
ining
Circui
t
Powe
r
(µW)
Intern
al
Clock
Power
(µW)
Total
Pow
er
(µW)
DCCE
R
83.2 19.8 103.
0
83.5 19.8 103.
3
Propos
ed
DCCE
R
80.1 18.3 98.4 80.5 18.3 98.8
SCCE
R
75.2 20.2 95.4 74.4 20.2 94.6
Propos
ed
SCCE
R
70.3 18.3 88.6 69.2 18.3 87.5
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Table5. Power Consumed by Flip Flop with Sleep
Mode
Original Flip Flops in
Sleep Mode
Flip Flops with Clock
Gating in Sleep Mode
Flip
Flop
Rema
ining
Circui
t
Powe
r
(µW)
Intern
al
Clock
Powe
r
(µW)
Tota
l
Pow
er
(µW
)
Remai
ning
Circuit
Power
(nW)
Intern
al
Clock
Powe
r
(nW)
Tota
l
Pow
er
(nW
)
DCCER 83.2 19.8 103.
0
5.4 4.5 9.9
Propose
d
DCCER
80.1 18.3 98.4 2.2 3.5 5.7
SCCER 75.2 20.2 95.4 8.5 3.5 11.0
Propose
d
SCCER
70.3 18.3 88.6 5.7 3.0 8.7
The results for the power consumed during
the sleep (clock gated) mode. Power results
significant savings when the clock gating is applied
to the flip-flops during idle state. Power saving of
more than 1000 times are obtained during the idle
state when compared to the power consumed without
clock gating. The power saving increase with
increase in the data switching activity.
Table6. Observation of Delays with Clock Gating
Original Flip-Flops Flip-Flops with Clock
Gating
Flips
-
Flop
s
Setu
p
Time
(ps)
Hold
Time
(ps)
CL
K-Q
Del
ay
(ps)
D-Q
Dela
y
(ps)
Setu
p
Tim
e
(ps)
Hol
d
Ti
me
(ps)
CLK
-Q
Dela
y
(ps)
D-Q
Dela
y
(ps)
DCC
ER
143 175 190 405 143 175 201 417
Prop
osed
DCC
ER
125 160 176.
3
390 125 160 180.
5
401
SCC
ER
280 45 150.
4
325 280 45 155.
9
287
Prop
osed
SCC
ER
255 15 123.
5
310 255 15 129.
5
316
Table 6 shows the delay comparisons between the
original flip-flops and flip-flops with clock gating.
The results show that the clock gating addition has no
impact on setup and hold time of the flip-flops while
CLK-Q delay and D-Q delay are increased.
VI. Pipelined Array Multiplier
To demonstrate the feasibility and
effectiveness of the proposed energy recovery
clocking scheme and flip flops, a pipelined using the
proposed clocking scheme. The multiplier is 8x8 bit
pipelined multiplier pipelined with SCCER flip flops
and DCCER flip flops. The clock input of all flip
flops are connected together an H-tree type of clock.
The logic part of the design is composed of AND
gate and full adder gates. A similar multiplier has
been designed using transmission gate flip flop and
square wave clock. The clock tree in this multiplier
was also H-tree. However, buffer was inserted to
properly propagate the square wave clock through the
clock network. Results show a power reduction of
70% on the clock tree and total power savings of
25%-69% as compared to the same multiplier using
conventional square wave clocking scheme and
corresponding flip flops.
Fig.16 Pipelined Array Multiplier
VII. Conclusion
We proposed energy recovery clocked flip
flops that enable energy recovery from the clock
network, resulting in significant total energy saving
compared to the square wave clocking. The proposed
flip flops operate with a single phase sinusoidal
clock, which can be generated with high efficiency.
We implemented 1024 proposed energy recovery
clocked flip-flops through an H-tree clock network
driven by resonant clock generator, generating a
sinusoidal clock. Simulation results show a power
reduction of 90% on the clock tree and power saving
of up to 80% as compared to the same
implementation using conventional square wave
clocking scheme and flip flops. We applied clock
gating to energy recovery clocked flip-flops. Clock
gating in energy recovery clocked flip flops result in
significant power saving during the idle state of the
flip flops without any considerable overhead
compared to the original flip-flops. Energy recovery
clocked pipelined multiplier with an integrated
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resonant clock-generator, generating a sinusoidal
clock. Results show a power reduction of 70% on the
clock tree and total power savings of 25%-69% as
compared to the same multiplier using conventional
square wave clocking scheme and corresponding flip-
flops. The results demonstrate the feasibility and
effectiveness of the energy recovery clocking scheme
in reducing total power consumption.
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Mashkoor Alam
I completed M. Tech with Electronics &
Telecommunication, specialization in
VLSI Design & Embedded System from
KIIT University Bhubaneswar. I have
done B.Sc. Engg. With Electronics &
Communication Engineering from Ramgobind
Institute of Technology Koderma which is affiliated
by Vinoba Bhava University Hazaribag in 2008.
Rajendra Prasad
Rajendra Prasad is with KIIT University
in the school of Electronics and
Telecommunication as an Assistant
Professor. He did his B. Tech from
Satyabama University, Chennai in the year 2009. He
completed his M. Tech from VIT University, Vellore
in the year 2011.