Pll Basic Linkedin2

PLL Basics 2-28-2009
Stan Goldman
Goldman Technology

Goldman Technology 1/26/2012 Page 1 1

PLL Basics Agenda

• History
• Applications
• Overview of PLLs
• Background information
• Control Systems
• Test and Measurement
• References and Background Material

Goldman Technology 1/26/2012 Page 2

History

• De Bellescize in 1932
– Synchronous reception of radio signals
– Received audio amplified to speaker
• Television, 1st wide spread use
– Synchronization of horizontal and vertical scan
in television


Applications
• Frequency multiplier by multiplying the frequency
of the reference oscillator.
• Modulator by adding the modulating signal to the
phase error.
• Demodulator by tracking the changes in
modulation to the reference input.
• Coherent receiver by operating as a narrow band
tunable filter to track the carrier frequency.
• Data synchronizer by operating as a narrow band
tunable filter to recover the clock.

Serializer/Deserializer


Hard Disk Drive


Wireless

CELL PHONE


KEY PLL DESIGN REQUIREMENTS

• Architecture
• Loop Stability
• Frequency Range
• Time Jitter


PLL Control System Block Diagram
With Phase Relationships

θo
θi θi θ0
n mf

[Goldman 2007 p19]


Key Signals of Interest within a PLL

• Input frequency or reference frequency
• Output frequency
• Tune voltage or current input to the VCO or CCO
• Phase error (comparison of the positive edge of the
reference input signal to the phase detector with the
positive edge of the feed back signal from the VCO to
the phase detector with the positive edge of the reference
input as the trigger source)


Ideal VCO Transfer Function,
Transduces Voltage to Frequency (Edges)

ωout=ωoff+Kv Vtune ωout=∆θout/∆t

1 E9

8 E8

To = 2 M Td

4 E8

0

[Goldman 2007 p3]


Relationship of Phase/Frequency in VCO,
(1/s transfer function relationship)

• Mathematical description of a phase modulated signal, from Taub and
Shilling, Principles of Communication Systems, p117 and modified with
PLL terminology:
 
V o( t ) V a⋅ cos  ω ⋅ t + K ⋅ ⌠ V ( t ) dt

 c v

⌡
tune
   ⌠ 
d 
ω ω c⋅ t + K v⋅  V tune( t ) dt ω c + K v⋅ V tune( t )
Instantaneous Frequency dt  
⌡
 

Deviation of instantaneous frequency ω − ωc⋅ t Kv⋅ Vtune( t)
fo
from ωc which equals ω ref in modeling 2⋅ π 2⋅ π

⌠
Instantaneous phase θ ω c⋅ t + K v⋅  V tune( t ) dt
oi 
⌡

Deviation of instantaneous phase
⌠
K v⋅  V tune( t) dt
1
θ θ − ω c⋅ t K v⋅ ⋅ V tune( s )
o 
⌡ s


Digital Phase Detector Timing and Response to Ramped VCO Phase

VDD D UP
Q
RIN
C Q
CL

VDD DOWN
D Q
VCOIN
C Q
CL
Reset


Ideal Phase Detector Transfer Function,
Transduces Frequency (Edge) Differences to Voltage
Vpdavg=Kd θe (5MHz Ref. Freq.)

-200 -100 0 100 200
Ref. – VCO Edge (ns) [Goldman 2007 p2]


Output of Analog Phase Detector vs Phase Error (-cos)
with Various Measures of Abscissa

[Goldman 2007 p18]

Example of Lock, Digital Loop
(In Phase)

[Goldman 2007 p4]


Mathematical Relationship of Phase and Frequency (Analog Phase Detector)
Phase detector as a mixer (analog multiplier)

Mixing of Two Signals Signal Definition

V1(t) V2(t) = Vp1Vp2 cos(ωrf t + θe ) cos(ωlo t )
V1(t)= Vp1 cos(ωrft+ θe )
where:
Using the trigonometric identity for products of a trigonometric function:
V1(t)= Source 1 signal,
Vp1= Maximum amplitude of source 1 (volts),
V1(t) V2(t)=Vp1Vp2 0.5 [cos ( ωrf t- ωlo t + θe ) +cos( ωrf t + ωlo t + θe )]
ωrf= Angular frequency of a Signal at the RF port of the mixer (rad./sec),
where: = 2 π frf,
V1(t) V2(t) = Mixing process. θe= Phase error difference between signal 1 and 2 (rad.), and
t= Time variable (seconds).
Eliminating the high frequency product V2(t) = Vp2 cos(ωlo t )
with a low pass filter yields where:
V2(t)= Source 2 signal,
V1(t) V2(t) =Vp1 Vp2 0.5 [ cos(ωrf t - ωlo t + θe ) ] Vp2= Maximum amplitude of source 2 (volts), and
ωlo= Angular frequency of a signal at the LO port of a mixer (rad./sec).
=Vpbeat cos( ωbeat t + θe )

where:
ωbeat = ωrf - ωlo for ωrf > ωlo,
Vpbeat = Vp1 Vp2 x 0.5 x mixer losses, and
= The resulting voltage level after mixing (volts).

Slope
V pds
d
( )
V pbeat ⋅cos θ e ( )
V pbeat ⋅sin θ e
dθ e
where:

Vpds ( φ)= Phase detector phase slope (volts).
Phase Detector Gain

Vpds(θe) = Vpbeat sin(θe ) Kd=Vpbeat


Charge Pump Output Transduces Frequency (Edge) Differences to
Current, Kp=I/(2 π)


Loop Classifications

[Goldman 2007 p8]


Loop Classifications (Continued)

[Goldman 2007 p8]


Example of Lock, Analog Loop (Sinewaves)
Phase detector as a mixer (analog multiplier)

VCO Tune Voltage


Vtune, Input, and Output Signals, Locked (Quadrature)


Vtune, Input, and Output Signals, During Acquisition,
Searching For Lock

In phase for higher tune voltage Out of phase for lower tune voltage


PLL TRANSFER FUNCTION AND CONTROL SYSTEMS THEORY

• Control System's General Equation for a Closed Loop
Co G (s)
=
Ri 1 ± G ( s ) ⋅ H ( s )
- =For positive feedback,
+ =For negative feedback,
Co
R i =The closed-loop transfer function,

G(s)=Forward transfer function,
H(s)=Feedback transfer function,
G(s) H(s)=Open-loop transfer function, and
G(s) H(s)=Ratio of 1 and angle of 0 deg for positive feedback
and 180 deg for negative feedback are the
conditions for oscillation.
• Closed Loop PLL Transfer Function from General Equation
θo G( s )
(s)
θi 1 G( s ) . H ( s )
θ0
=Output phase (rad) and
θi =Input phase (rad).


Judging Stability from Step Response
Freqeuncy (Hz)
6 10 4

.035 Damping
4 deg. Phase Margin 3 10 4

~90% Overshoot
0
4
6 10

.2 Damping
22 deg. Phase Margin 3 10 4

~60% Overshoot
0
4
6 10

.42 Damping 4
45 deg. Phase Margin 3 10

~40% Overshoot
0
0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.01

Time (s)
[Goldman 2007 p20]
30 deg or 45 deg. Phase Margin are levels supported in references


PLL Basic Block Diagram
For Cascade of Transfer functions for Open Loop Gain

[Goldman 2007 p22]


Type 2 Second Order Open Loop Gain Function (Active Filter)

Cascade of Transfer functions for Open Loop Gain
G(s)H(s)= (Phase Detector Gain)(Filter Transfer Function)
(VCO Transfer Function)(Divider Transfer Function)
Substitute and Rearrange for Open Loop Gain Expression
K d. K v
G( s ) . H ( s ) . 1 . s . C. R 1
2
n mf . C . R 1 s 2

Substitute and Rearrange for Closed Loop Gain Expression

Kd
= Phase detector gain (volts/radian), = Capacitor in the operational amplifier's
Kv = VCO transfer function gain C feedback path (F),
constant (radians/second/volt), = Resistor in operational amplifier's
R1
n mf = Integer divider value, feedback path (ohms) and,
= Loop Frequency Multiplication Factor, = Resistor at the negative input terminal
= Output frequency/ input frequency, R2 of the operational amplifier (ohms).


Converting to Servo Terminology
Closed Loop Gain Expression
. s. 2 ζ
2 .
n mf . ω n 1
G( s ) ωn
1 G( s ) . H ( s ) s
2
s . 2 . ζω ωn
2
n

Error Expression
2
1 s
1 G( s ) . H ( s ) s
2
s . 2 . ζω ωn
2
n

Open loop gain Expression

. s.2 ζ
2 1 .
G( s ) . H ( s ) ωn . 1
s
2 ωn


Synthesis of Loop Component Values from Servo Terminology

Kd. Kv R2. C Kd. Kv
• Active Filter ωn ζ .
R1. C. n mf 2 R1. C. nmf

For selected C value, damping factor, and natural frequency
and given Kd and Kv

Kd.Kv 2. ζ
R1 R2
2
ω n .C.nmf ω .C n

• Passive Filter
Kd. Kv Kd.Kv
ωn 1. 1
ζ . R .C
R1 R2 . C. n mf 2 R1 R2 .Cnmf 2
. Kd.Kv

K v . Ip . R 2
• Charge Pump K v . Ip
ωn 2 . π . n mf
2. π . C. n mf ζ
2.ω n


Charge Pump PLL with Regulator

•Charge pump can not drive high current load
•1 pin for external components


Loop Stability, Bode Plot

Magnitude

Phase Margin
Phase

Gain Margin

[Goldman 2007 p27]


Graphical Relationship of Natural Frequency to 0 dB Crossover Frequency

[Goldman 2007 p29]


Open Loop Response
(ASIC APLL External Components ) 32, 71, 147 MHz

71 MHz

32 MHz

147 MHz
147 MHz

32 MHz

71 MHz


Closed Loop Response (APLL)

32 MHz

71 MHz

147 MHz


Error Function Response


Test and Measurement of PLL (Brief)

• Spurious signals, hold in range, and
lock range
• Frequency Switching Time
• Jitter


Spurious Signals

[Goldman 2007 p357]


Hold In Range, Lock In Range

[Goldman 2007 p355]


Jitter Measurements

• Oscilloscope (Time Domain)
• Modulation Domain Analyzer
• Spectrum Analyzer ( Frequency Domain)


Jitter, Oscilloscope

[Goldman 2007 p388]


Relationship of Modulation Domain to
Spectrum Analyzer and Oscilloscope

F

T

V

[Goldman 2007 p378]


Oscilloscope Measurement of 1 and Multiple Periods

1 clo ck p eriod oscilloscop e m easurem ent w ith jitter FM m odulation

1 p eriod scope m easurem ent
1
T

1

6 clock periods o scilloscope m easurem ent w ith jitter F M m odulation

6 th period scop e m easurem ent
1
T

1 [Goldman 2007 p380]


Frequency Switching Time, Modulation Domain Analyzer

[Goldman 2007 p358]


Comparison Table of Measured Data with Comparable PLL References

VCO Output power supply
Area Frequency sensitivity, %-
Description Processes Power (mm2) (MHz) Jitter fvco/%-Vdd Comments

Simulated, Supply
S. Sidropoulos Controlled Ring VCO,
VLSI '00 .35um 3.3V 21.5mW@500MHz 0.047 30-650 .06%/1% wide BW

Regulator included,
J.M. Ingino 44ps p-p at single ended ring
ISSCC '01 .15um 3.3V 132mW@4GHz 1.48 600- 4000 700MHz .007%/1% CCO

Supply Controled
Ring VCO, wide BW,
H. Ahn JSSC '00 .25um 1.9V 25mW@320MHz 0.087 17-1320 0.32%/1% 2.5MHZ BW
K. Minami CICC Single ended ring
'01 .1um 1.2V 30mW at 2000MHz 0.15 500-2350 21ps p-p CCO

Maneatis ISSCC Differential ring
'03 .13um 1.5V 7mW at 240MHz 0.18 30-650 48ps p-p VCO, self biased
155ps p-p Differential ring
Hozer ISSCC '02 .13um 1.5V 7mW at 200MHz 0.16 10-350 360MHz VCO, VCR
All Digital PLL, diff.
Fahim TCAS '03 .25um 1.9V 3.12mW at 160MHz 30-160 130ps p-p ring VCO

DCAS 2008 .065um 1.2V 1mW at 240MHz 0.06 12-600 80ps p-p 0.02%/1%


Recommended PLL Books

1. Stanley
Goldman, Phase Locked Loop Engineering Handbook,
Artech House, Boston, 2007.
2. Roland Best, Phase Locked Loops Design Simulation, & Applications,
McGraw Hill, New York, 1997.
3. Behzad Razavi, Monolithic Phase-Locked Loops and Clock Recovery
Circuits, EEE Press, New York 1996.
4. James A. Crawford, Frequency Synthesizer Design Handbook, Artech
House, Boston.
5. William Egan, Frequency Synthesis by Phase-Lock, Wiley Interscience,
New York, 1981.
6. Floyd Martin Gardner, Phaselock Techniques, Wiley Interscience, New
York, 1979.


Recommended Background Books

Feedback Control Systems by Charles L. Phillips and Royce
D. Harbor
The Fast Fourier Transform by E. Oran Brigham
Network Analysis by Van Valkenburg
Analysis and Design of Analog Integrated Circuits by Paul
R. Gray and Robert G. Meyer
Principles of CMOS VLSI Design by Neil H. E. Weste and
Kamran Eshraghian
Principles of Communicaton Systems by H. Taub and D. L.
Schilling


External Websites

• Texas Instruments, High Performance PLLs
http://www.ti.com/sc/docs/products/msp/clock/pll/overview.htm
• National Semiconductor
http://www.national.com/appinfo/wireless/
• Frequency Response Analysis and Design Tutorials
http://me.www.ecn.purdue.edu/~me475/ctm/freq/freq.html
• Chip Directory
http://icat.snu.ac.kr/chipdir/f/pll.htm
• Phase Locked Loop Fundamentals ( Minicircuits)
http://www.minicircuits.com/appnote/vco15-10.pdf
• Monolithic CMOS RF Transceiver (Berkeley)
http://kabuki.eecs.berkeley.edu/rf/rf.html
• Analog IC Design, Dr Hellums (UTD)
http://www.utdallas.edu/~hellums/
• PLLs , Stan Goldman
http://home.tx.rr.com/sgold_1


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