The document describes characterization and reliability testing of the EPA120B-100P transistor using the ZVxPlus application. It outlines the measurement setup and calibration process, and demonstrates DC and RF transistor characterization through IV curves, S-parameters, and time domain signals. Advanced displays show dynamic load lines and small-signal parameters. Measurements are exported to ADS for model verification.

1. ZVxPlus Application:
Transistor Characterization,
Reliability and
Model Verification
April 2009

2. Outline
 The Device Under Test (DUT): EPA120B-100P
 Measurement Setup
 “Fire and Go...”
 Calibration and Deembedding Process
 DC IV Application
 DC+RF Measurement
• Frequency Domain
• Time Domain
• Terminating Impedances
 Advanced Display: Dynamic lines
 Model Verification
 Conclusions
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3. EPA120B-100P
 EPA120B-100P
• high efficiency heterojunction power FET
• power output: + 29.0dBm typ.
• power gain: 11.5dB typ. @ 12 GHz
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4. Measurement Setup
Vg Vd
Port 3
Excitation
Source a1 b1 b2 a2 a3
Synchroniser
20 dB 20 dB
Port 1 Port 2
DUT
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5. “Fire and Go...”
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6. DUT properly working? (1)
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7. DUT properly working? (2)
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8. Next Step?
Calibration
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9. DC Calibration
Vg Vd
Excitation Port 3
a1 b1 b2 a2 a3
Source Synchroniser
20 dB 20 dB
Port 1 Port 2
L L
o o
a a
d d
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10. RF Calibration
Vg Vd
Excitation Port 3
a1 b1 b2 a2 a3
Source Synchroniser
20 dB 20 dB
Port 1 Port 2
O O
S T S
M M
PWM
HPR
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11. DUT in pinch off?
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12. Some words about deembedding
Cal Plane A1 Cal Plane B1 Cal Plane B2 Cal Plane A2
i1(t) i1(t) i2(t) i2(t)
v1(t) v1(t) v2(t) v2(t)
The DUT is placed on a PCB
→ using calibration plane A1 and A2 we measure the behaviour of the DUT AND PCB
→ using Multiline TRL (thru-reflect-line) we move the calibration plane to the DUT
we measure the behaviour ONLY of the DUT
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13. Some words about deembedding
 Include package
Using the FET Model,
provided by the manufacturer
the package can be included
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14. DUT in pinch off (with deembedding)
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15. ICE DC IV Application
Capability to force the control variables
in the calibration plane
Defining limits at
DC source and
in calibration plane
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16. ZVxPlus: Frequency Domain Characterisation - Phase
Vgs=-0.6V, Vds=5V f0=1GHz amplitude phase
Pin=-25dBm Pin=0dBm
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17. ZVxPlus: Time Domain Characterisation
Vgs=-0.6V, Vds=5V f0=1GHz
a1
Pin=0dBm
b1
Pin=-25dBm
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18. ZVxPlus: Time Domain Characterisation – Pinch Off
Vgs=-1.3V, Vds=5V f0=1GHz
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19. ZVxPlus: Terminating Impedances
Output Impedance with Open termination
at fundamental and 2 harmonics
Output Impedance with 50 Ohm termination
at fundamental and 2 harmonics
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20. ZVxPlus: Dynamic Loadline
Vgs=-0.6V, Vds=4V f0=1GHz Pin = 0 dBm
Compare the static Vgate with the dynamic Vgate through color Z-axis
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21. ZVxPlus: Dynamic Gm and Input Capacitance
Dynamic Gm
“Dynamic Input Capacitance”
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22. Exporting Measurements
a1(f)
b1(f) ADS
a2(f) CITIfile
b2(f)
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23. Model Verification in ADS
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24. Measurement vs Simulation
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25. Conclusions
 Prepare measurement setup and ICE
 Calibration steps
 Deembedding capability
 DC and RF Transistor Characterization
 Basic Displays
 Advanced Displays: Dynamic Lines
 Model Verification
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