1. Goldman Research
PLL Basics 2-28-2009
Stan Goldman
Goldman Research
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2. Goldman Research
PLL Basics Agenda
• History
• Applications
• Overview of PLLs
• Background information
• Control Systems
• Test and Measurement
• References and Background Material
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History
• De Bellescize in 1932
– Synchronous reception of radio signals
– Received audio amplified to speaker
• Television, 1st wide spread use
– Synchronization of horizontal and vertical scan in
television
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Applications
• Frequency multiplier by multiplying the frequency of the
reference oscillator.
• Modulator by adding the modulating signal to the phase error.
• Demodulator by tracking the changes in modulation to the
reference input.
• Coherent receiver by operating as a narrow band tunable filter to
track the carrier frequency.
• Data synchronizer by operating as a narrow band tunable filter to
recover the clock.
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Serializer/Deserializer
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Hard Disk Drive
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Wireless
CELL PHONE
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KEY PLL DESIGN REQUIREMENTS
• Architecture
• Loop Stability
• Frequency Range
• Time Jitter
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9. Goldman Research
PLL Control System Block Diagram
With Phase Relationships
θo
θi
θi θ0
n mf
[Goldman 2007 p19]
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Key Signals of Interest within a PLL
• Input frequency or reference frequency
• Output frequency
• Tune voltage or current input to the VCO or CCO
• Phase error (comparison of the positive edge of the
reference input signal to the phase detector with the
positive edge of the feed back signal from the VCO to the
phase detector with the positive edge of the reference input
as the trigger source)
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Ideal VCO Transfer Function,
Transduces Voltage to Frequency (Edges)
ωout=ωoff+Kv Vtune
ωout=∆θout/∆t
1 E9
8 E8
To = 2 M Td
4 E8
0
[Goldman 2007 p3]
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Relationship of Phase/Frequency in VCO,
(1/s transfer function relationship)
• Mathematical description of a phase modulated signal, from Taub and Shilling,
Principles of Communication Systems, p117 and modified with PLL terminology:
 
 ω ⋅ t + K ⋅ ⌠ V ( t ) dt

V o( t ) V a⋅ cos
c 
v tune
⌡
   
⌠
d  V ( t ) dt
ω ω c⋅ t + K v⋅ ω c + K v⋅ V tune( t )
dt   tune
Instantaneous Frequency ⌡
 
ω − ωc⋅ t Kv⋅ Vtune( t)
Deviation of instantaneous frequency
fo
from wc which equals wref in modeling 2⋅ π 2⋅ π
⌠
ω c⋅ t + K v⋅  V tune( t ) dt
Instantaneous phase θ

oi
⌡
Deviation of instantaneous phase
⌠
K v⋅  V tune( t) dt
1
θ θ − ω c⋅ t K v⋅ ⋅ V tune( s )

o
⌡ s
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13. Goldman Research
Digital Phase Detector Timing and Response to Ramped VCO Phase
UP
VDD D Q
RIN
C Q
CL
DOWN
VDD D Q
VCOIN
C Q
CL
Reset
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Ideal Phase Detector Transfer Function,
Transduces Frequency (Edge) Differences to Voltage
Vpdavg=Kd θe (5MHz Ref. Freq.)
-100 0 100 200
-200
Ref. – VCO Edge (ns) [Goldman 2007 p2]
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Output of Analog Phase Detector vs Phase Error (-cos)
with Various Measures of Abscissa
[Goldman 2007 p18]
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16. Goldman Research
Example of Lock, Digital Loop
(In Phase)
[Goldman 2007 p4]
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Mathematical Relationship of Phase and Frequency (Analog Phase Detector)
Phase detector as a mixer (analog multiplier)
Signal Definition
Mixing of Two Signals
V1(t)= Vp1 cos(ωrft+ θe )
V1(t) V2(t) = Vp1Vp2 cos(ωrf t + θe ) cos(ωlo t )
where:
V1(t)= Source 1 signal,
Using the trigonometric identity for products of a trigonometric function:
Vp1= Maximum amplitude of source 1 (volts),
ωrf= Angular frequency of a Signal at the RF port of the mixer (rad./sec),
V1(t) V2(t)=Vp1Vp2 0.5 [cos ( ωrf t- ωlo t + θe ) +cos( ωrf t + ωlo t + θe )]
= 2 π frf,
θe= Phase error difference between signal 1 and 2 (rad.), and
where:
t= Time variable (seconds).
V1(t) V2(t) = Mixing process.
V2(t) = Vp2 cos(ωlo t )
Eliminating the high frequency product where:
with a low pass filter yields V2(t)= Source 2 signal,
Vp2= Maximum amplitude of source 2 (volts), and
ωlo= Angular frequency of a signal at the LO port of a mixer (rad./sec).
V1(t) V2(t) =Vp1 Vp2 0.5 [ cos(ωrf t - ωlo t + θe ) ]
=Vpbeat cos( ωbeat t + θe )
where:
ωbeat = ωrf - ωlo for ωrf > ωlo,
Vpbeat = Vp1 Vp2 x 0.5 x mixer losses, and
= The resulting voltage level after mixing (volts).
Slope
() ()
d
V pbeat ⋅cos θ e V pbeat ⋅sin θ e
V pds
dθ e
where:
Phase Detector Gain
Vpds ( φ)= Phase detector phase slope (volts).
Kd=Vpbeat
Vpds(θe) = Vpbeat sin(θe )
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18. Goldman Research
Charge Pump Output Transduces Frequency (Edge) Differences
to Current, Kp=I/(2 π)
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19. Goldman Research
Loop Classifications
[Goldman 2007 p8]
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20. Goldman Research
Loop Classifications (Continued)
[Goldman 2007 p8]
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21. Goldman Research
Example of Lock, Analog Loop (Sinewaves)
Phase detector as a mixer (analog multiplier)
VCO Tune Voltage
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Vtune, Input, and Output Signals, Locked (Quadrature)
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Vtune, Input, and Output Signals, During Acquisition,
Searching For Lock
In phase for higher tune voltage Out of phase for lower tune voltage
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24. Goldman Research
PLL TRANSFER FUNCTION AND CONTROL SYSTEMS THEORY
• Control System's General Equation for a Closed Loop
Co G (s)
=
Ri 1 ± G ( s ) ⋅ H ( s )
- =For positive feedback,
+ =For negative feedback,
Co
R i =The closed-loop transfer function,
G(s)=Forward transfer function,
H(s)=Feedback transfer function,
G(s) H(s)=Open-loop transfer function, and
G(s) H(s)=Ratio of 1 and angle of 0 deg for positive feedback
and 180 deg for negative feedback are the
conditions for oscillation.
• Closed Loop PLL Transfer Function from General Equation
θo G( s )
(s)
θi G( s ) . H ( s )
1
θ0
=Output phase (rad) and
θi =Input phase (rad).
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Judging Stability from Step Response
Freqeuncy (Hz)
4
6 10
.035 Damping
3 10 4
4 deg. Phase Margin
~90% Overshoot 0
4
10
6
.2 Damping
3 10 4
22 deg. Phase Margin
~60% Overshoot
0
6 10 4
.42 Damping 4
3 10
45 deg. Phase Margin
~40% Overshoot
0
0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.01
0.009
Time (s)
[Goldman 2007 p20]
30 deg or 45 deg. Phase Margin are levels supported in references
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26. Goldman Research
PLL Basic Block Diagram
For Cascade of Transfer functions for Open Loop Gain
[Goldman 2007 p22]
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Type 2 Second Order Open Loop Gain Function (Active Filter)
Cascade of Transfer functions for Open Loop Gain
G(s)H(s)= (Phase Detector Gain)(Filter Transfer Function)
(VCO Transfer Function)(Divider Transfer Function)
Substitute and Rearrange for Open Loop Gain Expression
K d. K v
. 1 . s . C. R
G( s ) . H ( s ) 1
2
n mf . C . R 1 s 2
Substitute and Rearrange for Closed Loop Gain Expression
Kd
= Phase detector gain (volts/radian), = Capacitor in the operational amplifier's
C
= VCO transfer function gain feedback path (F),
Kv
constant (radians/second/volt), = Resistor in operational amplifier's
R1
= Integer divider value, feedback path (ohms) and,
n mf
= Loop Frequency Multiplication Factor, = Resistor at the negative input terminal
= Output frequency/ input frequency, of the operational amplifier (ohms).
R2
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Converting to Servo Terminology
Closed Loop Gain Expression
. s. 2 ζ
.
2
n mf . ω n 1
ωn
G( s )
G( s ) . H ( s )
1 2
2
s . 2 . ζω ωn
s n
Error Expression
2
1 s
G( s ) . H ( s )
1 2
2
s . 2 . ζω ωn
s n
Open loop gain Expression
. s.2 ζ
.
1
2
ωn
G( s ) . H ( s ) . 1
ωn
2
s
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Synthesis of loop component values from servo terminology
R2. C Kd. Kv
Kd. Kv
ζ .
ωn
R1. C. nmf
2
R1. C. n mf
• Active Filter
For selected C value, damping factor, and natural frequency
and given Kd and Kv
Kd.Kv 2. ζ
R1 R2
ω .C
2
ω n .C.nmf n
• Passive Filter
Kd. Kv Kd.Kv
1. 1
ωn ζ . R .C
R2 . C. n mf 2 R1 R2 .Cnmf 2
R1 . Kd.Kv
K v . Ip . R 2
K v . Ip
• Charge Pump
2 . π . n mf
ωn
ζ
2. π . C. n mf
2.ω n
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30. Goldman Research
Charge Pump PLL with Regulator
•Charge pump can not drive high current load
•1 pin for external components
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31. Goldman Research
Loop Stability, Bode Plot
Magnitude
Phase Margin
Phase
Gain Margin
[Goldman 2007 p27]
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32. Goldman Research
Graphical Relationship of Natural Frequency to 0 dB Crossover Frequency
[Goldman 2007 p29]
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Open Loop Response
(ASIC APLL External Components ) 32, 71, 147 MHz
71 MHz
32 MHz
147 MHz
147 MHz
32 MHz
71 MHz
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34. Goldman Research
Closed Loop Response (APLL)
32 MHz
71 MHz
147 MHz
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35. Goldman Research
Error Function Response
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36. Goldman Research
Test and Measurement of PLL (Brief)
• Spurious signals, hold in range, and lock range
• Frequency Switching Time
• Jitter
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Spurious Signals
[Goldman 2007 p357]
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38. Goldman Research
Hold In Range, Lock In Range
[Goldman 2007 p355]
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Jitter Measurements
• Oscilloscope (Time Domain)
• Modulation Domain Analyzer
• Spectrum Analyzer ( Frequency Domain)
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Jitter, Oscilloscope
[Goldman 2007 p388]
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Relationship of Modulation Domain to
Spectrum Analyzer and Oscilloscope
F
T
V
[Goldman 2007 p378]
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Oscilloscope Measurement of 1 and Multiple Periods
1 clo ck p eriod oscilloscop e m easurem ent w ith jitter FM m odulation
1 p eriod scope m easurem ent
1
T
1
6 clock periods o scilloscope m easurem ent w ith jitter F M m odulation
6 th period scop e m easurem ent
1
T
1 [Goldman 2007 p380]
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43. Goldman Research
Frequency Switching Time, Modulation Domain Analyzer
[Goldman 2007 p358]
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44. Goldman Research
Comparison Table of Measured Data with Comparable PLL References
power supply
Area VCO Output sensitivity, %-
Description Processes Power (mm2) Frequency (MHz) Jitter fvco/%-Vdd Comments
Simulated, Supply
S. Sidropoulos Controlled Ring VCO,
VLSI '00 .35um 3.3V 21.5mW@500MHz 0.047 30-650 .06%/1% wide BW
J.M. Ingino ISSCC 44ps p-p at Regulator included,
'01 .15um 3.3V 132mW@4GHz 1.48 600- 4000 700MHz .007%/1% single ended ring CCO
Supply Controled Ring
VCO, wide BW, 2.5MHZ
H. Ahn JSSC '00 .25um 1.9V 25mW@320MHz 0.087 17-1320 0.32%/1% BW
K. Minami CICC '01 .1um 1.2V 30mW at 2000MHz 0.15 500-2350 21ps p-p Single ended ring CCO
Maneatis ISSCC Differential ring VCO,
'03 .13um 1.5V 7mW at 240MHz 0.18 30-650 48ps p-p self biased
Differential ring VCO,
Hozer ISSCC '02 .13um 1.5V 7mW at 200MHz 0.16 10-350 155ps p-p 360MHz VCR
All Digital PLL, diff. ring
Fahim TCAS '03 .25um 1.9V 3.12mW at 160MHz 30-160 130ps p-p VCO
DCAS 2008 .065um 1.2V 1mW at 240MHz 0.06 12-600 80ps p-p 0.02%/1%
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45. Goldman Research
Recommended PLL Books
1. Stanley
Goldman, Phase Locked Loop Engineering Handbook, Artech House,
Boston, 2007.
2. Roland Best, Phase Locked Loops Design Simulation, & Applications, McGraw Hill, New
York, 1997.
3. Behzad Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits, EEE Press,
New York 1996.
4. James A. Crawford, Frequency Synthesizer Design Handbook, Artech House, Boston.
5. William Egan, Frequency Synthesis by Phase-Lock, Wiley Interscience, New York, 1981.
6. Floyd Martin Gardner, Phaselock Techniques, Wiley Interscience, New York, 1979.
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46. Goldman Research
Recommended Background Books
Feedback Control Systems by Charles L. Phillips and Royce D. Harbor
The Fast Fourier Transform by E. Oran Brigham
Network Analysis by Van Valkenburg
Analysis and Design of Analog Integrated Circuits by Paul R. Gray and
Robert G. Meyer
Principles of CMOS VLSI Design by Neil H. E. Weste and Kamran
Eshraghian
Principles of Communicaton Systems by H. Taub and D. L. Schilling
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External Websites
• Texas Instruments, High Performance PLLs
http://www.ti.com/sc/docs/products/msp/clock/pll/overview.htm
• National Semiconductor
http://www.national.com/appinfo/wireless/
• Frequency Response Analysis and Design Tutorials
http://me.www.ecn.purdue.edu/~me475/ctm/freq/freq.html
• Chip Directory
http://icat.snu.ac.kr/chipdir/f/pll.htm
• Phase Locked Loop Fundamentals ( Minicircuits)
http://www.minicircuits.com/appnote/vco15-10.pdf
• Monolithic CMOS RF Transceiver (Berkeley)
http://kabuki.eecs.berkeley.edu/rf/rf.html
• Analog IC Design, Dr Hellums (UTD)
http://www.utdallas.edu/~hellums/
• PLLs , Stan Goldman
http://home.tx.rr.com/sgold_1
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