This document discusses instruction pipelining in processors. It explains that pipelining allows multiple instructions to be overlapped in execution by dividing processing into stages like fetch, decode, execute, and writeback. Pipelining improves processor throughput and performance by keeping the pipeline stages continuously busy. While pipelining can significantly increase processor speed, it also introduces complexity and potential issues like pipeline stalls if instructions are dependent on each other.

1. PIPELINE
PROCESSING
Created by
Suraj Das

2. INDEX
▪ Introduction
▪ Pipeline Case – Non Pipeline vs. Pipeline
▪ Pipeline Processors
▪ Instruction Pipeline
▪ Timing Diagram for Instruction Pipeline Operation
▪ Pipeline Performance: Clock & Timing
▪ Pipeline Performance: Speedup & Efficiency
▪ Advantages of Pipeline
▪ Disadvantages of Pipeline

3. INTRODUCTION

4.  Pipelining is a speed-up technique where multiple instructions are
overlapped in execution on a processor.
 The elements of a pipeline are often executed in parallel or in time-
sliced fashion; in that case, some amount of buffer storage is often
inserted between elements.
 Buffer or data buffer:
• It is a region of physical memory storage used to temporarily
store data while.
• It is moved from one place to another.

10.  Write result (W R)
 Operation Briefly Explained
 Fetch instruction (Fl)
 Decode instruction (Dl)
 Calculate operands (CO)
 Fetch operands (FO) & Execute instructions (El)
• The IF stage is responsible for Obtaining the requested instruction from memory. The instruction
and the program counter are stored in the register as temporary storage.
• The Dl stage is responsible for decoding the instruction and sending Out the various control lines
to the other parts Of the processor.
• The CO stage is where any calculations are performed. The main component in this Stage is the
ALU. The ALU is made up Of arithmetic, logic and capabilities.
• The FO and El Stages are responsible for storing and loading values to and from memory. They are
also responsible for input and output from the processor respectively.
• The WO stage is responsible for writing the result Of a calculation, memory access or input into
the register file.

12. PIPELINE PERFORMANCE: CLOCK & TIMING

13. PIPELINE PERFORMANCE: SPEEDUP & EFFICIENCY

14. Advantages of Pipeline

15. Disadvantages of Pipeline

16. THE END
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