2. What is pipelining?
โข A technique used in advanced microprocessors where the
microprocessor begins executing a second instruction before the first
has been completed
โข Multiple instructions are overlapped in execution
โข Process of instruction execution is divided into two or more steps, called pipe stages
or pipe segments
โข Different stage are completing different parts of different instructions in parallel
โข The stages are connected one to the next to form a pipe
โข Instructions enter at one end, progress through the stages, and exit at the other end
โข Unlike some speedup techniques, it is not visible to the programmer/compiler.
3.
4. Characteristics of pipelining
โข Hardware or software implementation โ pipelining can be implemented in either software
or hardware.
โข Large or Small Scale โ Stations in a pipeline can range from simplistic to powerful, and a
pipeline can range in length from short to long.
โข Buffered or unbuffered flow โ One stage of pipeline sends data directly to another one or
a buffer is place between each pairs of stages.
โข Synchronous or asynchronous flow โ A synchronous pipeline operates like an assembly
line: at a given time, each station is processing some amount of information. A
asynchronous pipeline, allow a station to forward information at any time.
โข Automatic Data Feed Or Manual Data Feed โ Some implementations of pipelines use a
separate mechanism to move information, and other implementations require each stage
to participate in moving information
5. Types of pipelining
โข Software Pipelining
โข Can Handle Complex Instructions
โข Allows programs to be reused
โข Hardware Pipelining
โข Help designer manage complexity โ a complex task can be divided into smaller, more
manageable pieces.
โข Hardware pipelining offers higher performance
6. Effects of pipelining
โข Time in ns per instruction goes up
โข Number of cycles per instruction goes up (note the increase in clock
speed)
โข Total execution time goes down, resulting in lower time per instruction
โข Average cycles per instruction increases slightly
โข Under ideal conditions:
โข speedup = ratio of elapsed times between successive instruction completions
= number of pipeline stages = increase in clock speed
7. Instruction pipelining
โข An instruction pipeline increases the performance of a processor by overlapping the
processing of several different instructions
โข Consists of five stages:
โข Instruction fetch (IF): the instruction is fetched from memory and placed in the
instruction register (IR)
โข Instruction decode (ID): identification of the operation to be performed
โข Execution (EX): the instruction is executed
โข Memory read/write (ME): stage is responsible for storing and loading values to and
from memory. It also responsible for input or output from the processor.
โข Write back (WB): The results of the operation are written to the destination register.
8. Timings
โข Estimated timing for each stage of instruction:
โข Instruction fetch โ 2ns
โข Instruction decode โ 1ns
โข Execution โ 2ns
โข Memory and I/O โ 2ns
โข Write Back โ 1ns
9. Hazards
โข There are three types of hazards that can happen while pipelined
execution:
โข Structural hazards
โข Data hazards
โข Control hazards
10. Hazards (cont.)
โข Structural hazards
โข different instructions in different stages (or the same stage) conflicting for the
same resource
โข Data hazards
โข an instruction cannot continue because it needs a value that has not yet been
generated by an earlier instruction
โข Control hazards
โข fetch cannot continue because it does not know the outcome of an earlier
branch โ special case of a data hazard
11. Data hazard
โข Data hazard caused by data dependences
โข There are three data dependences:
โข Read-After-Write (RAW)
โข Write-After-Write (WAW)
โข Write-After-Read (WAR)
12. Read-After-Write
IF ID EX M WB
IF ID EX M WB
ADD R1, R2, R3
SUB R4, R1, R5
Read R2 and R3 Add R2 and R3 Write result to R1
Read R1 and R5
Next instruction tries to read an operand before previous instruction writes it Extremely common hazard
13. Write-After-Write
IF ID EX M M1 M2 M3 WB
IF ID EX M WB
ADD R1, R2, R3
SUB R1, R4, R5
Read R2 and R3 Add R2 and R3 Write result to R1
Write result to R1
Next instruction tries to write an operand before previous instruction writes it
14. Write-After-Read
IF ID EX M WB
IF ID EX M WB
ADD R1, R2, R3
SUB R2, R1, R5
Read R2 and R3 Write result to R1
Write result to R2
Next instruction tries to write an operand before previous instruction reads it. Happens if pipeline is out-order
15. Dealing with data hazard
โข We can solve data hazard problem with stalling
โข Stalling
โข halting the flow of instructions until the required result is ready to be used
โข wastes processor time by doing nothing while waiting for the result.
16. IF ID EX M WB
ADD R1, R2, R3
SUB R4, R1, R5
IF ID EX M WB
IF ID EX M WB
IF ID EX M WB
IF ID EX M WB
STALL
STALL
STALL
18. ๐๐๐๐๐๐ข๐ ๐๐๐๐ ๐๐๐๐๐๐๐๐๐๐ =
๐ถ๐๐ผ ๐ข๐๐๐๐๐๐๐๐๐๐
1 + ๐๐๐๐๐๐๐๐ ๐ ๐ก๐๐๐ ๐๐๐๐๐ ๐๐ฆ๐๐๐๐ ๐๐๐ ๐๐๐ ๐ก๐๐ข๐๐ก๐๐๐
CPI unpipelined = depth of pipeline
IF ID EX M WB
IF ID EX M WB
IF ID EX M WB
Pipeline depth
๐บ๐๐๐๐ ๐๐ ๐๐๐๐ ๐๐๐๐๐๐๐๐๐๐ =
๐ท๐๐๐๐๐๐๐ ๐ ๐๐๐๐
๐ + ๐ท๐๐๐๐๐๐๐ ๐๐๐๐๐ ๐๐๐๐๐ ๐๐๐๐๐๐ ๐๐๐ ๐๐๐๐๐๐๐๐๐๐๐
19. Advantages and disadvantages
โข Advantages:
โข More efficient use of processor
โข Quicker time of execution of large number of instructions
โข Disadvantages:
โข Pipelining involves adding hardware to the chip
โข Inability to continuously run the pipeline at full speed because of pipeline
hazards which disrupt the smooth execution of the pipeline.
