Parallel computing is a type of computation in which many calculations or the execution of processes are carried out simultaneously. Large problems can often be divided into smaller ones, which can then be solved at the same time. There are several different forms of parallel computing: bit-level, instruction-level, data, and task parallelism. Parallelism has been employed for many years, mainly in high-performance computing, but interest in it has grown lately due to the physical constraints preventing frequency scaling. As power consumption (and consequently heat generation) by computers has become a concern in recent years, parallel computing has become the dominant paradigm in computer architecture, mainly in the form of multi-core processors.
An explicitly parallel program must specify concurrency and interaction between concurrent subtasks.
The former is sometimes also referred to as the control structure and the latter as the communication model.
A multi-core processor is a single computing component with two or more independent actual processing units (called "cores"), which are units that read and execute program instructions. The instructions are ordinary CPU instructions (such as add, move data, and branch), but the multiple cores can run multiple instructions at the same time, increasing overall speed for programs amenable to parallel computing. Manufacturers typically integrate the cores onto a single integrated circuit die (known as a chip multiprocessor or CMP), or onto multiple dies in a single chip package.
This document discusses parallel processing architectures SIMD and MIMD. It defines serial processing as executing tasks sequentially on a single CPU. Parallel processing uses multiple CPUs concurrently by dividing a problem into parts. SIMD involves multiple processors executing the same instruction on different data simultaneously. MIMD uses multiple autonomous processors executing different instructions on different data, allowing more flexibility. Examples of each model are provided.
Modern processors are faster than memory
So Processors may waste time for accessing memory
Its purpose is to make the main memory appear to the processor to be much faster than it actually is
The document discusses parallelism and techniques to improve computer performance through parallel execution. It describes instruction level parallelism (ILP) where multiple instructions can be executed simultaneously through techniques like pipelining and superscalar processing. It also discusses processor level parallelism using multiple processors or processor cores to concurrently execute different tasks or threads.
The document discusses different types of parallel computer architectures, including shared-memory multiprocessors. It describes taxonomy of parallel computers including SISD, SIMD, MISD, and MIMD models. For shared-memory multiprocessors, it outlines consistency models including strict, sequential, processor, weak and release consistency. It also discusses UMA and NUMA architectures, cache coherence protocols like MESI, and examples of multiprocessors using crossbar switches or multistage networks.
Parallel computing is a type of computation in which many calculations or the execution of processes are carried out simultaneously. Large problems can often be divided into smaller ones, which can then be solved at the same time. There are several different forms of parallel computing: bit-level, instruction-level, data, and task parallelism. Parallelism has been employed for many years, mainly in high-performance computing, but interest in it has grown lately due to the physical constraints preventing frequency scaling. As power consumption (and consequently heat generation) by computers has become a concern in recent years, parallel computing has become the dominant paradigm in computer architecture, mainly in the form of multi-core processors.
An explicitly parallel program must specify concurrency and interaction between concurrent subtasks.
The former is sometimes also referred to as the control structure and the latter as the communication model.
A multi-core processor is a single computing component with two or more independent actual processing units (called "cores"), which are units that read and execute program instructions. The instructions are ordinary CPU instructions (such as add, move data, and branch), but the multiple cores can run multiple instructions at the same time, increasing overall speed for programs amenable to parallel computing. Manufacturers typically integrate the cores onto a single integrated circuit die (known as a chip multiprocessor or CMP), or onto multiple dies in a single chip package.
This document discusses parallel processing architectures SIMD and MIMD. It defines serial processing as executing tasks sequentially on a single CPU. Parallel processing uses multiple CPUs concurrently by dividing a problem into parts. SIMD involves multiple processors executing the same instruction on different data simultaneously. MIMD uses multiple autonomous processors executing different instructions on different data, allowing more flexibility. Examples of each model are provided.
Modern processors are faster than memory
So Processors may waste time for accessing memory
Its purpose is to make the main memory appear to the processor to be much faster than it actually is
The document discusses parallelism and techniques to improve computer performance through parallel execution. It describes instruction level parallelism (ILP) where multiple instructions can be executed simultaneously through techniques like pipelining and superscalar processing. It also discusses processor level parallelism using multiple processors or processor cores to concurrently execute different tasks or threads.
The document discusses different types of parallel computer architectures, including shared-memory multiprocessors. It describes taxonomy of parallel computers including SISD, SIMD, MISD, and MIMD models. For shared-memory multiprocessors, it outlines consistency models including strict, sequential, processor, weak and release consistency. It also discusses UMA and NUMA architectures, cache coherence protocols like MESI, and examples of multiprocessors using crossbar switches or multistage networks.
Michael Flynn proposed a taxonomy in 1966 to classify computer architectures based on the number of instruction streams and data streams. The four classifications are: SISD (single instruction, single data stream), SIMD (single instruction, multiple data streams), MISD (multiple instructions, single data stream), and MIMD (multiple instructions, multiple data streams). SISD corresponds to the traditional von Neumann architecture, SIMD is used for array processing, MIMD describes most modern parallel computers, and MISD has never been implemented.
This document discusses hardware and software parallelism in computer systems. It defines hardware parallelism as parallelism enabled by the machine architecture through multiple processors or functional units. Software parallelism refers to parallelism exposed in a program's control and data dependencies. Modern computer architectures require support for both types of parallelism to perform multiple tasks simultaneously. However, there is often a mismatch between the hardware and software parallelism available. For example, a dual-processor system may be able to execute 12 instructions in 6 cycles, but the program's inherent parallelism may only allow completing the instructions in 7 cycles. Achieving optimal parallelism requires coordination between hardware design and software programming.
This document evaluates the performance of four memory consistency models (sequential consistency, processor consistency, weak consistency, and release consistency) for shared-memory multiprocessors using simulation studies of three applications (MP3D, LU, and PTHOR). The results show that sequential consistency performs significantly worse than the other models. Surprisingly, processor consistency performs almost as well as release consistency and better than weak consistency for one application, indicating that allowing reads to bypass pending writes provides more benefit than allowing writes to pipeline.
Distributed shared memory (DSM) is a memory architecture where physically separate memories can be addressed as a single logical address space. In a DSM system, data moves between nodes' main and secondary memories when a process accesses shared data. Each node has a memory mapping manager that maps the shared virtual memory to local physical memory. DSM provides advantages like shielding programmers from message passing, lower cost than multiprocessors, and large virtual address spaces, but disadvantages include potential performance penalties from remote data access and lack of programmer control over messaging.
This document discusses parallel programming concepts including threads, synchronization, and barriers. It defines parallel programming as carrying out many calculations simultaneously. Advantages include increased computational power and speed up. Key issues in parallel programming are sharing resources between threads, and ensuring synchronization through locks and barriers. Data parallel programming is discussed where the same operation is performed on different data elements simultaneously.
The document discusses cache coherence in multiprocessor systems. It describes the cache coherence problem that can arise when multiple processors have caches and can access shared memory. It then summarizes two primary hardware solutions: directory protocols which maintain information about which caches hold which memory lines; and snoopy cache protocols where cache controllers monitor bus traffic to maintain coherence without a directory. Finally it mentions a software-based solution relying on compiler analysis and operating system support.
This document discusses cache coherence in single and multiprocessor systems. It provides techniques to avoid inconsistencies between cache and main memory including write-through, write-back, and instruction caching. For multiprocessors, it discusses issues with sharing writable data, process migration, and I/O activity. Software solutions involve compiler and OS management while hardware uses coherence protocols like snoopy and directory protocols.
The document provides an overview of parallel processing and multiprocessor systems. It discusses Flynn's taxonomy, which classifies computers as SISD, SIMD, MISD, or MIMD based on whether they process single or multiple instructions and data in parallel. The goals of parallel processing are to reduce wall-clock time and solve larger problems. Multiprocessor topologies include uniform memory access (UMA) and non-uniform memory access (NUMA) architectures.
This presentation talks about Real Time Operating Systems (RTOS). Starting with fundamental concepts of OS, this presentation deep dives into Embedded, Real Time and related aspects of an OS. Appropriate examples are referred with Linux as a case-study. Ideal for a beginner to build understanding about RTOS.
The document discusses multithreading and how it can be used to exploit thread-level parallelism (TLP) in processors designed for instruction-level parallelism (ILP). There are two main approaches for multithreading - fine-grained and coarse-grained. Fine-grained switches threads every instruction while coarse-grained switches on long stalls. Simultaneous multithreading (SMT) allows a processor to issue instructions from multiple threads in the same cycle by treating instructions from different threads as independent. This converts TLP into additional ILP to better utilize the resources of superscalar and multicore processors.
Faster microprocessor design presentation in American International University-Bangladesh (AIUB). Presentation was taken under the subject "SELECTED TOPICS IN ELECTRICAL AND ELECTRONIC ENGINEERING (PROCESSOR AND DSP HARDWARE DESIGN WITH SYSTEM VERILOG, VHDL AND FPGAS) [MEEE]", as a final semester student of M.Sc at AIUB.
This document discusses multiprocessor systems, including their interconnection structures, interprocessor arbitration, communication and synchronization, and cache coherence. Multiprocessor systems connect two or more CPUs with shared memory and I/O to improve reliability and enable parallel processing. They use various interconnection structures like buses, switches, and hypercubes. Arbitration logic manages shared resources and bus access. Synchronization ensures orderly access to shared data through techniques like semaphores. Cache coherence protocols ensure data consistency across processor caches and main memory.
This document discusses multicore computers and their organization. It describes how hardware performance issues around increasing parallelism and power consumption led to the development of multicore processors. Multicore computers combine two or more processors on a single chip for improved performance. The main variables in multicore organization are the number of cores, levels of cache memory, and whether cache is shared.
The document provides an overview of Hadoop and its ecosystem. It discusses the history and architecture of Hadoop, describing how it uses distributed storage and processing to handle large datasets across clusters of commodity hardware. The key components of Hadoop include HDFS for storage, MapReduce for processing, and an ecosystem of related projects like Hive, HBase, Pig and Zookeeper that provide additional functions. Advantages are its ability to handle unlimited data storage and high speed processing, while disadvantages include lower speeds for small datasets and limitations on data storage size.
The document summarizes the history and evolution of non-relational databases, known as NoSQL databases. It discusses early database systems like MUMPS and IMS, the development of the relational model in the 1970s, and more recent NoSQL databases developed by companies like Google, Amazon, Facebook to handle large, dynamic datasets across many servers. Pioneering systems like Google's Bigtable and Amazon's Dynamo used techniques like distributed indexing, versioning, and eventual consistency that influenced many open-source NoSQL databases today.
This presentation discusses Dynamic RAM (DRAM) and its types. It begins by explaining what RAM is and how it provides faster access for the CPU than the hard disk. It then covers that DRAM is the main memory in computers and must be refreshed periodically to prevent data loss. The main types of DRAM discussed are SDRAM, DDR, RDRAM, and DRAM memory modules. Specific details are provided about the features and operation of each DRAM type. Major memory manufacturers are also listed.
Multithreading allows exploiting thread-level parallelism (TLP) to improve processor utilization. There are several categories of multithreading:
- Superscalar simultaneous multithreading interleaves instructions from multiple threads within a single out-of-order processor core to reduce idle resources.
- Coarse-grained multithreading switches between threads on long-latency events like cache misses to hide latency.
- Fine-grained multithreading interleaves threads at a finer instruction granularity in in-order cores.
- Multiprocessing physically separates threads onto multiple processor cores.
Audio Version available in YouTube Link : https://www.youtube.com/AKSHARAM?sub_confirmation=1
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Computer Architecture and Organization
V semester
Anna University
By
Babu M, Assistant Professor
Department of ECE
RMK College of Engineering and Technology
Chennai
Flynn's taxonomy classifies computer architectures based on the number of instruction and data streams. The main categories are:
1) SISD - Single instruction, single data stream (von Neumann architecture)
2) SIMD - Single instruction, multiple data streams (vector/MMX processors)
3) MIMD - Multiple instruction, multiple data streams (most multiprocessors including multi-core)
Multiprocessor architectures can be organized as shared memory (SMP/UMA) or distributed memory (message passing/DSM). Shared memory allows automatic sharing but can have memory contention issues, while distributed memory requires explicit communication but scales better. Achieving high parallel performance depends on minimizing sequential
Unit IV discusses parallelism and parallel processing architectures. It introduces Flynn's classifications of parallel systems as SISD, MIMD, SIMD, and SPMD. Hardware approaches to parallelism include multicore processors, shared memory multiprocessors, and message-passing systems like clusters, GPUs, and warehouse-scale computers. The goals of parallelism are to increase computational speed and throughput by processing data concurrently across multiple processors.
Michael Flynn proposed a taxonomy in 1966 to classify computer architectures based on the number of instruction streams and data streams. The four classifications are: SISD (single instruction, single data stream), SIMD (single instruction, multiple data streams), MISD (multiple instructions, single data stream), and MIMD (multiple instructions, multiple data streams). SISD corresponds to the traditional von Neumann architecture, SIMD is used for array processing, MIMD describes most modern parallel computers, and MISD has never been implemented.
This document discusses hardware and software parallelism in computer systems. It defines hardware parallelism as parallelism enabled by the machine architecture through multiple processors or functional units. Software parallelism refers to parallelism exposed in a program's control and data dependencies. Modern computer architectures require support for both types of parallelism to perform multiple tasks simultaneously. However, there is often a mismatch between the hardware and software parallelism available. For example, a dual-processor system may be able to execute 12 instructions in 6 cycles, but the program's inherent parallelism may only allow completing the instructions in 7 cycles. Achieving optimal parallelism requires coordination between hardware design and software programming.
This document evaluates the performance of four memory consistency models (sequential consistency, processor consistency, weak consistency, and release consistency) for shared-memory multiprocessors using simulation studies of three applications (MP3D, LU, and PTHOR). The results show that sequential consistency performs significantly worse than the other models. Surprisingly, processor consistency performs almost as well as release consistency and better than weak consistency for one application, indicating that allowing reads to bypass pending writes provides more benefit than allowing writes to pipeline.
Distributed shared memory (DSM) is a memory architecture where physically separate memories can be addressed as a single logical address space. In a DSM system, data moves between nodes' main and secondary memories when a process accesses shared data. Each node has a memory mapping manager that maps the shared virtual memory to local physical memory. DSM provides advantages like shielding programmers from message passing, lower cost than multiprocessors, and large virtual address spaces, but disadvantages include potential performance penalties from remote data access and lack of programmer control over messaging.
This document discusses parallel programming concepts including threads, synchronization, and barriers. It defines parallel programming as carrying out many calculations simultaneously. Advantages include increased computational power and speed up. Key issues in parallel programming are sharing resources between threads, and ensuring synchronization through locks and barriers. Data parallel programming is discussed where the same operation is performed on different data elements simultaneously.
The document discusses cache coherence in multiprocessor systems. It describes the cache coherence problem that can arise when multiple processors have caches and can access shared memory. It then summarizes two primary hardware solutions: directory protocols which maintain information about which caches hold which memory lines; and snoopy cache protocols where cache controllers monitor bus traffic to maintain coherence without a directory. Finally it mentions a software-based solution relying on compiler analysis and operating system support.
This document discusses cache coherence in single and multiprocessor systems. It provides techniques to avoid inconsistencies between cache and main memory including write-through, write-back, and instruction caching. For multiprocessors, it discusses issues with sharing writable data, process migration, and I/O activity. Software solutions involve compiler and OS management while hardware uses coherence protocols like snoopy and directory protocols.
The document provides an overview of parallel processing and multiprocessor systems. It discusses Flynn's taxonomy, which classifies computers as SISD, SIMD, MISD, or MIMD based on whether they process single or multiple instructions and data in parallel. The goals of parallel processing are to reduce wall-clock time and solve larger problems. Multiprocessor topologies include uniform memory access (UMA) and non-uniform memory access (NUMA) architectures.
This presentation talks about Real Time Operating Systems (RTOS). Starting with fundamental concepts of OS, this presentation deep dives into Embedded, Real Time and related aspects of an OS. Appropriate examples are referred with Linux as a case-study. Ideal for a beginner to build understanding about RTOS.
The document discusses multithreading and how it can be used to exploit thread-level parallelism (TLP) in processors designed for instruction-level parallelism (ILP). There are two main approaches for multithreading - fine-grained and coarse-grained. Fine-grained switches threads every instruction while coarse-grained switches on long stalls. Simultaneous multithreading (SMT) allows a processor to issue instructions from multiple threads in the same cycle by treating instructions from different threads as independent. This converts TLP into additional ILP to better utilize the resources of superscalar and multicore processors.
Faster microprocessor design presentation in American International University-Bangladesh (AIUB). Presentation was taken under the subject "SELECTED TOPICS IN ELECTRICAL AND ELECTRONIC ENGINEERING (PROCESSOR AND DSP HARDWARE DESIGN WITH SYSTEM VERILOG, VHDL AND FPGAS) [MEEE]", as a final semester student of M.Sc at AIUB.
This document discusses multiprocessor systems, including their interconnection structures, interprocessor arbitration, communication and synchronization, and cache coherence. Multiprocessor systems connect two or more CPUs with shared memory and I/O to improve reliability and enable parallel processing. They use various interconnection structures like buses, switches, and hypercubes. Arbitration logic manages shared resources and bus access. Synchronization ensures orderly access to shared data through techniques like semaphores. Cache coherence protocols ensure data consistency across processor caches and main memory.
This document discusses multicore computers and their organization. It describes how hardware performance issues around increasing parallelism and power consumption led to the development of multicore processors. Multicore computers combine two or more processors on a single chip for improved performance. The main variables in multicore organization are the number of cores, levels of cache memory, and whether cache is shared.
The document provides an overview of Hadoop and its ecosystem. It discusses the history and architecture of Hadoop, describing how it uses distributed storage and processing to handle large datasets across clusters of commodity hardware. The key components of Hadoop include HDFS for storage, MapReduce for processing, and an ecosystem of related projects like Hive, HBase, Pig and Zookeeper that provide additional functions. Advantages are its ability to handle unlimited data storage and high speed processing, while disadvantages include lower speeds for small datasets and limitations on data storage size.
The document summarizes the history and evolution of non-relational databases, known as NoSQL databases. It discusses early database systems like MUMPS and IMS, the development of the relational model in the 1970s, and more recent NoSQL databases developed by companies like Google, Amazon, Facebook to handle large, dynamic datasets across many servers. Pioneering systems like Google's Bigtable and Amazon's Dynamo used techniques like distributed indexing, versioning, and eventual consistency that influenced many open-source NoSQL databases today.
This presentation discusses Dynamic RAM (DRAM) and its types. It begins by explaining what RAM is and how it provides faster access for the CPU than the hard disk. It then covers that DRAM is the main memory in computers and must be refreshed periodically to prevent data loss. The main types of DRAM discussed are SDRAM, DDR, RDRAM, and DRAM memory modules. Specific details are provided about the features and operation of each DRAM type. Major memory manufacturers are also listed.
Multithreading allows exploiting thread-level parallelism (TLP) to improve processor utilization. There are several categories of multithreading:
- Superscalar simultaneous multithreading interleaves instructions from multiple threads within a single out-of-order processor core to reduce idle resources.
- Coarse-grained multithreading switches between threads on long-latency events like cache misses to hide latency.
- Fine-grained multithreading interleaves threads at a finer instruction granularity in in-order cores.
- Multiprocessing physically separates threads onto multiple processor cores.
Audio Version available in YouTube Link : https://www.youtube.com/AKSHARAM?sub_confirmation=1
subscribe the channel
Computer Architecture and Organization
V semester
Anna University
By
Babu M, Assistant Professor
Department of ECE
RMK College of Engineering and Technology
Chennai
Flynn's taxonomy classifies computer architectures based on the number of instruction and data streams. The main categories are:
1) SISD - Single instruction, single data stream (von Neumann architecture)
2) SIMD - Single instruction, multiple data streams (vector/MMX processors)
3) MIMD - Multiple instruction, multiple data streams (most multiprocessors including multi-core)
Multiprocessor architectures can be organized as shared memory (SMP/UMA) or distributed memory (message passing/DSM). Shared memory allows automatic sharing but can have memory contention issues, while distributed memory requires explicit communication but scales better. Achieving high parallel performance depends on minimizing sequential
Unit IV discusses parallelism and parallel processing architectures. It introduces Flynn's classifications of parallel systems as SISD, MIMD, SIMD, and SPMD. Hardware approaches to parallelism include multicore processors, shared memory multiprocessors, and message-passing systems like clusters, GPUs, and warehouse-scale computers. The goals of parallelism are to increase computational speed and throughput by processing data concurrently across multiple processors.
SIMD (single instruction, multiple data) parallel processors exploit data-level parallelism by performing the same operation on multiple data points simultaneously using a single instruction. Vector processors are a type of SIMD parallel processor that operate on 1D arrays of data called vectors. They contain vector registers that can hold multiple data elements and functional units that perform arithmetic and logical operations in a pipelined fashion on entire vectors. Array processors are another type of SIMD machine composed of multiple identical processing elements that perform computations in lockstep under the control of a single instruction unit. Early examples include the ILLIAC IV and Cray X1 supercomputers. Multimedia extensions like MMX provide SIMD integer operations to improve performance of multimedia applications.
This document discusses parallel processors, specifically single instruction multiple data (SIMD) processors. It provides details on vector processors and array processors. Vector processors utilize vector instructions that operate on arrays of data called vectors. They have vector registers, functional units, and load/store units. Array processors perform parallel computations on large data arrays using multiple identical processing elements. The document describes dedicated memory and global memory organizations for array processors. It provides examples of early SIMD machines like ILLIAC IV.
Flynn's classification categorizes computer architectures based on the number of instruction and data streams. There are four categories: SISD, SIMD, MISD, and MIMD. SISD refers to a single instruction single data architecture, like a typical CPU. SIMD uses a single instruction on multiple data streams, like GPUs. MISD uses multiple instructions on a single data stream. MIMD uses multiple instructions and data streams, like modern multiprocessor systems.
This document discusses multi-core processor architectures. It begins by explaining that multi-core processors contain multiple processor cores on a single chip or die. Each core can run threads independently and in parallel. The document then covers topics like how operating systems schedule threads across multiple cores, why multi-core architectures became prevalent, different memory models for multi-cores, and challenges like maintaining cache coherence across private caches when data is shared. It also compares multi-core designs to simultaneous multithreading approaches.
This document discusses parallel architecture and parallel programming. It begins by introducing the traditional von Neumann architecture and serial computation model. It then defines parallel architecture, noting its use of multiple processors to solve problems concurrently by breaking work into discrete parts that can execute simultaneously. Key concepts in parallel programming models are also introduced, including shared memory, message passing, and data parallelism. The document outlines approaches for designing parallel programs, such as automatic and manual parallelization, as well as domain and functional decomposition. It concludes by mentioning examples of parallel algorithms and case studies in parallel application development using Java mobile agents and threads.
This document discusses parallel architecture and parallel programming. It begins with an introduction to von Neumann architecture and serial computation. Then it defines parallel architecture, outlines its benefits, and describes classifications of parallel processors including multiprocessor architectures. It also discusses parallel programming models, how to design parallel programs, and examples of parallel algorithms. Specific topics covered include shared memory and distributed memory architectures, message passing and data parallel programming models, domain and functional decomposition techniques, and a case study on developing parallel web applications using Java threads and mobile agents.
BIL406-Chapter-2-Classifications of Parallel Systems.pptKadri20
This document discusses various classifications of parallel computer systems. It describes:
1. Flynn's taxonomy which divides systems into SISD, SIMD, MISD and MIMD based on their processing structure and instruction streams. SISD refers to traditional CPUs while MIMD allows for multiple independent instruction streams.
2. Examples of parallel architectures like the Cray-1 supercomputer, Connection Machine, and Transputers. The Cray-1 used vector processing to perform operations in parallel while Connection Machine had thousands of simple processors.
3. Different levels of parallelism from bit-level to instruction-level to job-level, with varying granularity of computation. Finer grain allows more
This document discusses multi-core processor architectures. It begins by explaining single-core processors and then introduces multi-core processors, which place multiple processor cores on a single chip. Each core can run threads independently and in parallel. The document discusses how operating systems schedule threads across multiple cores. It also covers challenges like cache coherence when multiple cores access shared memory. Overall, the document provides an overview of multi-core processors and how they exploit thread-level parallelism.
This document discusses key concepts and terminologies related to parallel computing. It defines tasks, parallel tasks, serial and parallel execution. It also describes shared memory and distributed memory architectures as well as communications and synchronization between parallel tasks. Flynn's taxonomy is introduced which classifies parallel computers based on instruction and data streams as Single Instruction Single Data (SISD), Single Instruction Multiple Data (SIMD), Multiple Instruction Single Data (MISD), and Multiple Instruction Multiple Data (MIMD). Examples are provided for each classification.
fundamentals of digital communication Unit 5_microprocessor.pdfshubhangisonawane6
The document discusses the evolution of microprocessors from single-core to multi-core architectures. It describes how multi-core processors have multiple processing cores on a single chip to improve performance and efficiency. Each core can independently execute threads simultaneously for parallel processing. The document outlines the key components involved in the instruction cycle of a microprocessor, including registers like the program counter and memory address registers. It also discusses how multicore processors benefit applications that can distribute processing across multiple threads.
This document discusses various models of parallel computer architectures. It begins with an overview of Flynn's taxonomy, which classifies computer systems based on the number of instruction and data streams. The main categories are SISD, SIMD, MIMD, and MISD. It then covers parallel computer models in more detail, including shared-memory multiprocessors, distributed-memory multicomputers, classifications based on interconnection networks and parallelism. It provides examples of different parallel architectures and references papers on advanced computer architecture and parallel processing.
This document discusses different types of parallel processing architectures including single instruction single data stream (SISD), single instruction multiple data stream (SIMD), multiple instruction single data stream (MISD), and multiple instruction multiple data stream (MIMD). It provides details on tightly coupled symmetric multiprocessors (SMPs) and non-uniform memory access (NUMA) systems. It also covers cache coherence protocols like MESI and approaches to improving processor performance through multithreading and chip multiprocessing.
Array Processors & Architectural Classification Schemes_Computer Architecture...Sumalatha A
This document discusses array processors and architectural classification schemes. It describes how array processors use multiple arithmetic logic units that operate in parallel to achieve spatial parallelism. They are capable of processing array elements and connecting processing elements in various patterns depending on the computation. The document also introduces Flynn's taxonomy, which classifies architectures based on their instruction and data streams as SISD, SIMD, MIMD, or MISD. Feng's classification and Handlers classification schemes are also overviewed.
This document discusses parallel processing and multiple processor architectures. It covers single instruction, single data stream (SISD); single instruction, multiple data stream (SIMD); multiple instruction, single data stream (MISD); and multiple instruction, multiple data stream (MIMD) architectures. It then discusses the taxonomy of parallel processor architectures including tightly coupled symmetric multiprocessors (SMPs), non-uniform memory access (NUMA) systems, and loosely coupled clusters. It covers parallel organizations for these different architectures.
The timing behavior of the OS must be predictable - services of the OS: Upper bound on the execution time!
2. OS must manage the timing and scheduling
OS possibly has to be aware of task deadlines;
(unless scheduling is done off-line).
3. The OS must be fast
This document discusses multiprocessor systems. It begins by explaining the reasons for using multiprocessors, including improving performance by using multiple CPUs. It then describes different types of multiprocessor symmetry and architectures, such as symmetric multiprocessing (SMP) and non-uniform memory access (NUMA). The document also discusses instruction and data streams, processor coupling in tightly-coupled and loosely-coupled systems, and communication architectures like message passing and shared memory. Finally, examples of multiprocessor systems like the HP Superdome are provided.
This document outlines the objectives, modules, and content of a course on parallel computing architectures. The course aims to enable students to describe computer architecture, measure performance, and summarize parallel architectures. It covers parallelism concepts, parallel architectures like multiprocessors and multicomputers, and parallel programming. The first module introduces parallelism theory, architectural development, and performance attributes. It discusses parallelism conditions, program partitioning, and system interconnects.
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1. Velammal Engineering College
Department of Computer Science
and Engineering
Welcome…
Slide Sources: Patterson & Hennessy COD book
website (copyright Morgan Kaufmann) adapted
and supplemented
Mr. A. Arockia Abins &
Ms. R. Amirthavalli,
Asst. Prof,
CSE,
Velammal Engineering College
3. Syllabus – Unit IV
UNIT-IV PARALLELISM
Introduction to Multicore processors and other shared memory
multiprocessors - Flynn's classification: SISD, MIMD, SIMD, SPMD
and Vector - Hardware multithreading: Fine-grained, Coarse-grained and
Simultaneous Multithreading (SMT) - GPU architecture: NVIDIA GPU
Architecture, NVIDIA GPU Memory Structure
4. Topics:
• Introduction to Multicore processors
• Other shared memory multiprocessors
• Flynn’s classification:
o SISD,
o MIMD,
o SIMD,
o SPMD and Vector
• Hardware multithreading
• GPU architecture
4
6. Multicore processors
• What is a Processor?
o A single chip package that fits in a socket
o Cores can have functional units, cache, etc.
associated with them
• The main goal of the multi-core design is to provide
computing units with an increasing processing power.
• A multicore processor is a single computing
component with two or more “independent”
processors (called "cores").
• known as a chip multiprocessor or CMP
6
7. EXAMPLES
dual-core processor with 2 cores
• e.g. AMD Phenom II X2, Intel Core 2 Duo E8500
quad-core processor with 4 cores
• e.g. AMD Phenom II X4, Intel Core i5 2500T
hexa-core processor with 6 cores
• e.g. AMD Phenom II X6, Intel Core i7 Extreme Ed. 980X
octa-core processor with 8 cores
• e.g. AMD FX-8150, Intel Xeon E7-2820
7
11. Number of core types
Homogeneous (symmetric) cores:
• All of the cores in a homogeneous multicore
processor are of the same type; typically the core
processing units are general-purpose central
processing units that run a single multicore
operating system.
• Example: Intel Core 2
Heterogeneous (asymmetric) cores:
• Heterogeneous multicore processors have a mix of
core types that often run different operating systems
and include graphics processing units.
• Example: IBM's Cell processor, used in the Sony
PlayStation 3 video game console
11
15. Shared Memory Multiprocessors
• A system with multiple CPUs “sharing” the same
main memory is called multiprocessor.
• In a multiprocessor system all processes on the
various CPUs share a unique logical address space,
which is mapped on a physical memory that can be
distributed among the processors.
• Each process can read and write a data item simply
using load and store operations, and process
communication is through shared memory.
15
16. Shared Memory Multiprocessors
• Processors communicate through shared variables in
memory, with all processors capable of accessing
any memory location via loads and stores.
16
18. • Single address space multiprocessors come in two styles.
o Uniform Memory Access (UMA)
o Non-Uniform Memory Access (NUMA)
UMA Architecture:
• In the first style, the latency to a word in memory does
not depend on which processor asks for it. Such
machines are called uniform memory access (UMA)
multiprocessors.
NUMA/DSMA Architecture:
• In the second style, some memory accesses are much
faster than others, depending on which processor asks
for which word, typically because main memory is divided
and attached to different microprocessors or to different
memory controllers on the same chip.
• Such machines are called nonuniform memory access
(NUMA) multiprocessors.
18
19. Types:
• The shared-memory multiprocessors fall into two
classes, depending on the number of processors
involved, which in turn dictates a memory
organization and interconnect strategy.
• They are:
1. Centralized shared memory (Uniform Memory
Access)
2. Distributed shared memory (NonUniform Memory
Access)
19
23. Flynn's classification:
• In 1966, Michael Flynn proposed a
classification for computer architectures based
on the number of instruction steams and data
streams (Flynn’s Taxonomy).
o SISD (Single Instruction stream, Single Data
stream)
o SIMD (Single Instruction stream, Multiple Data
streams)
o MISD (Multiple Instruction streams, Single Data
stream)
o MIMD (Multiple Instruction streams, Multiple Data
streams)
23
25. SISD
• SISD machines executes a single instruction on individual
data values using a single processor.
• Based on traditional Von Neumann uniprocessor
architecture, instructions are executed sequentially or
serially, one step after the next.
• Until most recently, most computers are of SISD type.
• Conventional uniprocessor
25
27. SIMD
• An SIMD machine executes a single instruction on
multiple data values simultaneously using many
processors.
• Since there is only one instruction, each processor does
not have to fetch and decode each instruction. Instead, a
single control unit does the fetch and decoding for all
processors.
• SIMD architectures include array processors.
27
28. SIMD
• Data level parallelism:
o Parallelism achieved by performing the same operation on independent
data.
28
29. MISD
• Each processor executes a different sequence of instructions.
• In case of MISD computers, multiple processing units operate on one single-
data stream .
• This category does not actually exist. This category was included in the
taxonomy for the sake of completeness.
29
32. MIMD
• MIMD machines are usually referred to as
multiprocessors or multicomputers.
• It may execute multiple instructions simultaneously,
contrary to SIMD machines.
• Each processor must include its own control unit that will
assign to the processors parts of a task or a separate
task.
• It has two subclasses: Shared memory and distributed
memory
32
34. Analogy of Flynn’s Classifications
• An analogy of Flynn’s classification is the check-in desk at an airport
SISD: a single desk
SIMD: many desks and a supervisor with a megaphone giving instructions that every desk obeys
MIMD: many desks working at their own pace, synchronized through a central database
34
36. Processor Organizations
Computer Architecture
Classifications
Single Instruction, Single Instruction, Multiple Instruction
Multiple Instruction
Single Data Stream Multiple Data Stream Single Data Stream
Multiple Data Stream
(SISD) (SIMD) (MISD) (MIMD)
Uniprocessor Vector Array Shared Memory Multicomputer
Processor Processor (tightly coupled) (loosely
coupled)
37. Vector
• more elegant interpretation of SIMD is called a vector architecture
• the vector architectures pipelined the ALU to get good performance at lower
cost
• to collect data elements from memory, put them in order into a large set of
registers, operate on them sequentially in registers using pipelined
execution units.
• then write the results back to memory
37
42. Hardware multithreading
• A thread is a lightweight process with its own instructions
and data.
• Each thread has all the state (instructions, data, PC,
register state, etc.) necessary to allow it to execute.
• Multithreading (MT) allows multiple threads to share the
functional units of a single processor.
42
43. Hardware multithreading
• Increasing utilization of a processor by switching to
another thread when one thread is stalled.
• Types of Multithreading:
o Fine-grained Multithreading
• Cycle by cycle
o Coarse-grained Multithreading
• Switch on event (e.g., cache miss)
o Simultaneous Multithreading (SMT)
• Instructions from multiple threads executed concurrently in the same
cycle
43
45. Fine-grained MT
Idea: Switch to another thread every cycle such
that no two instructions from the thread are in the
pipeline concurrently
Advantages
+ No need for dependency checking between instructions
(only one instruction in pipeline from a single thread)
+ No need for branch prediction logic
+ Otherwise-bubble cycles used for executing useful instructions
from different threads
+ Improved system throughput, latency tolerance, utilization
46. Fine-grained MT
Idea: Switch to another thread every cycle such
that no two instructions from the thread are in the
pipeline concurrently
Disadvantages
- Extra hardware complexity: multiple hardware contexts, thread
selection logic
- Reduced single thread performance (one instruction fetched every
N cycles)
- Resource contention between threads in caches and memory
- Dependency checking logic between threads remains (load/store)
48. 48
Coarse-grained MT switches threads only on
costly stalls, such as L2 misses.
The processor is not slowed down (by thread
switching), since instructions from other threads
will only be issued when a thread encounters a
costly stall.
Since a CPU with coarse-grained MT issues
instructions from a single thread, when a stall
occurs the pipeline must be emptied.
The new thread must fill the pipeline before
instructions will be able to complete.
49. 49
Coarse-grained MT switches threads only on
costly stalls, such as L2 misses.
Advantages:
– thread switching doesn’t have to be essentially
free and much less likely to slow down the execution of an
individual thread
Disadvantage:
– limited, due to pipeline start-up costs, in its ability
to overcome throughput loss
Pipeline must be flushed and refilled on thread
switches
51. Questions
• Define thread.
• What is mean by hardware multithreading?
• Types of multithreading
June 2015
ILP Limits and Multithreading 51
52. Simultaneous Multithreading
52
Simultaneous multithreading (SMT) is a
variation on MT to exploit TLP simultaneously
with ILP.
SMT is motivated by multiple-issue processors
which have more functional unit parallelism than a
single thread can effectively use.
Multiple instructions from different threads can be
issued
57. Speedup
• Speedup measures increase in running time due to
parallelism. The number of PEs is given by n.
• Based on running times, S(n) = ts/tp , where
o ts is the execution time on a single processor, using the fastest known
sequential algorithm
o tp is the execution time using a parallel processor.
• For theoretical analysis, S(n) = ts/tp where
o ts is the worst case running time for of the fastest known sequential algorithm
for the problem
o tp is the worst case running time of the parallel algorithm using n PEs.
57
59. Amdahl’s law:
“It states that the potential speedup gained by the parallel execution of a
program is limited by the portion that can be parallelized.”
59
61. Question:
• When parallelizing an application, the ideal speedup is speeding up by the
number of processors. What is the speedup with 8 processors if 60% of the
application is parallelizable?
61
62. Question:
• When parallelizing an application, the ideal speedup is speeding up by the
number of processors. What is the speedup with 8 processors if 80% of the
application is parallelizable?
62
63. QUESTION:
• Suppose that we are considering an enhancement that runs 10 times faster
than the original machine but is usable only 40% of the time. What is the
overall speedup gained by incorporating the enhancement.?
63
64. Question
• Suppose you want to achieve a speed-up of 90
times faster with 100 processors. What
percentage of the original computation can be
sequential?
64
65. Question
• Suppose you want to achieve a speed-up of 90
times faster with 100 processors. What
percentage of the original computation can be
sequential?
65
66. Question
• Suppose you want to perform two sums: one is a sum of 10
scalar variables, and one is a matrix sum of a pair of two-
dimensional arrays, with dimensions 10 by 10. For now
let’s assume only the matrix sum is parallelizable. What
speed-up do you get with 10 versus 40 processors?
• Next, calculate the speed-ups assuming the matrices grow
to 20 by 20.
66
68. Graphics processing unit (GPU)
• It is a processor optimized for 2D/3D graphics, video, visual computing, and display.
• It is highly parallel, highly multithreaded multiprocessor optimized for visual
computing.
• It provide real-time visual interaction with computed objects via graphics images,
and video.
• Heterogeneous Systems: combine a GPU with a CPU
68