This document discusses array processors and architectural classification schemes. It describes how array processors use multiple arithmetic logic units that operate in parallel to achieve spatial parallelism. They are capable of processing array elements and connecting processing elements in various patterns depending on the computation. The document also introduces Flynn's taxonomy, which classifies architectures based on their instruction and data streams as SISD, SIMD, MIMD, or MISD. Feng's classification and Handlers classification schemes are also overviewed.
Very long instruction word or VLIW refers to a processor architecture designed to take advantage of instruction level parallelism
This type of processor architecture is intended to allow higher performance without the inherent complexity of some other approaches.
Motivation for a specialized MAC (Hidden and exposed terminals, Near and far terminals), SDMA, FDMA, TDMA, CDMA, Wireless LAN/(IEEE 802.11)
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Multiprocessor system is an interconnection of two or more CPUs with memory and input-output equipment
The components that forms multiprocessor are CPUs IOPs connected to input –output devices , and memory unit that may be partitioned into a number of separate modules.
Multiprocessor are classified as multiple instruction stream, multiple data stream (MIMD) system.
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On the basis of these scenarios and optimization goals, the design of networking protocols in wireless sensor networks are derived
A proper service interface is required and integration of WSNs into larger network contexts.
Very long instruction word or VLIW refers to a processor architecture designed to take advantage of instruction level parallelism
This type of processor architecture is intended to allow higher performance without the inherent complexity of some other approaches.
Motivation for a specialized MAC (Hidden and exposed terminals, Near and far terminals), SDMA, FDMA, TDMA, CDMA, Wireless LAN/(IEEE 802.11)
Mobile Network Layer: IP and Mobile IP Network Layers, Packet Delivery and Handover Management, Location Management, Registration, Tunneling and Encapsulation, Route Optimization, DHCP
Multiprocessor system is an interconnection of two or more CPUs with memory and input-output equipment
The components that forms multiprocessor are CPUs IOPs connected to input –output devices , and memory unit that may be partitioned into a number of separate modules.
Multiprocessor are classified as multiple instruction stream, multiple data stream (MIMD) system.
How to put these nodes together to form a meaningful network.
How a network should function at high-level application scenarios .
On the basis of these scenarios and optimization goals, the design of networking protocols in wireless sensor networks are derived
A proper service interface is required and integration of WSNs into larger network contexts.
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2. Array Processors Contd…
• Array processors leverage parallel computing by implementing
multiple arithmetic logic units i.e. processing elements in a
synchronized way.
• The processing elements operate in a parallel fashion.
• Now consider that if we replicate the ALUs and all ALUs are working
in parallel then we can say that we have achieved spatial
parallelism.
• Array processors are also capable of processing array elements.
3. • There are multiple ALUs that are connected in parallel with the
control unit using a data routing network.
• Each ALU in the system i.e., processing elements (PE) consists of the
processor(P) and local memory(M).
• The pattern in which the processing elements are interconnected
depends on the specific computation to be performed by the control
unit.
Array Processors Contd…
4. • The scalar instructions are implicitly executed in the control unit
whereas the vector instructions are broadcasted to the parallel
connected processing elements.
• The operands are fetched directly from the local memories.
• The instruction fetch and instruction decode is done by the control
unit and in this way the vector instructions are executed in a
distributed manner.
Array Processors Contd…
5.
6. • However, the different array processors may be using different kinds
of interconnection networks for connecting the processing
elements.
• The array processors are somewhat complex as compared to the
pipelined processors.
Array Processors Contd…
7. Multiprocessor Systems
• Multiprocessor system supports parallel computing by using a set of
interactive processors that have shared resources.
• In a multiprocessor system, there are multiple processors and
processors that have access to a common set of memory modules,
peripheral devices, and other input-output devices.
• However, the entire system with multiple processors is controlled by
a single operating system.
• It is the responsibility of the operating system to provide
interaction between the multiple processors present in the system.
• Even though the processors share memories, peripheral devices,
and I/O, each processor in the multiprocessor system has a local
memory and even some private devices.
8. • Communication between the processors can be achieved with the
help of shared memories or through the interrupted network.
• The interconnection between the shared memories, I/O devices,
and multiple processors in the system can be determined in three
different ways:
• Time shared common bus
• Crossbar switch network
• Multiport memories
• Using a multiprocessor system improves the throughput, flexibility,
availability, and reliability of the system.
Multiprocessor Systems Contd…
12. Flynn’s Classification Taxonomy
• Flynn's taxonomy distinguishes multi-processor computer
architectures according to how they can be classified along the two
independent dimensions of Instruction Stream and Data Stream.
• Each of these dimensions can have only one of two possible states:
Single or Multiple.
• The matrix below defines the 4 possible classifications according to
Flynn:
13. SISD- (Single Instruction Single Data)
• A serial (non-parallel) computer
• Single Instruction: Only one instruction stream is being acted on by
the CPU during any one clock cycle
• Single Data: Only one data stream is being used as input during any
one clock cycle
• Deterministic execution
• This is the oldest type of computer
• Examples: older generation mainframes, minicomputers,
workstations and single processor/core PCs.
15. Single Instruction, Multiple Data (SIMD)
• A type of parallel computer
• Single Instruction: All processing units execute the same instruction
at any given clock cycle
• Multiple Data: Each processing unit can operate on a different data
element
• Best suited for specialized problems characterized by a high degree of
regularity, such as graphics/image processing.
16. Single Instruction, Multiple Data (SIMD) Contd…
• Synchronous (lockstep) and deterministic execution
• Two varieties: Processor Arrays and Vector Pipelines
• Examples:
• Processor Arrays: Thinking Machines CM-2, MasPar MP-1 & MP-2,
ILLIAC IV
• Vector Pipelines: IBM 9000, Cray X-MP, Y-MP & C90, Fujitsu VP, NEC
SX-2, Hitachi S820, ETA10
• Most modern computers, particularly those with graphics processor
units (GPUs) employ SIMD instructions and execution units.
18. Multiple Instruction, Multiple Data (MIMD)
• A type of parallel computer
• Multiple Instruction: Every processor may be executing a different
instruction stream
• Multiple Data: Every processor may be working with a different data
stream
• Currently, the most common type of parallel computer - most modern
supercomputers falls into this category.
• Examples: most current supercomputers, networked parallel computer
clusters and "grids", multi-processor SMP computers, and multi-core PCs.
• Note: many MIMD architectures also include SIMD execution sub-
components
20. Multiple Instruction, Single Data (MISD)
• A type of parallel computer
• Multiple Instruction: Each processing unit operates on the data
independently via separate instruction streams.
• Single Data: A single data stream is fed into multiple processing
units.
• Few (if any) actual examples of this class of parallel computers have
ever existed.
• Some conceivable uses might be:
• multiple frequency filters operating on a single signal stream
• multiple cryptography algorithms attempting to crack a single coded
message.